Patent Application
20110298490
With the evolution of electronic devices, there is a continual demand for enhanced speed, capacity and efficiency in various areas including electronics. With this quest for efficiency, there may be a corresponding concern for reducing power consumption. Consequently, there remain unmet needs relating to power reduction solutions that reduce asymmetrical aging.
The asymmetrical aging control system may be better understood with reference to the following figures. The components within the figures are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the asymmetrical aging control system. Moreover, in the figures, like reference numerals designate corresponding parts or blocks throughout the different views.
While the asymmetric aging control system is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and subsequently are described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the asymmetric aging control system to the particular forms disclosed. In contrast, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the asymmetric aging control system as defined by this document.
As used in the specification and the appended claim(s), the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Similarly, “optional” or “optionally” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event or circumstance occurs and instances where it does not.
At some point, the ASIC 130 may need to exchange data with devices that previously were not connected, such as computer system 117 or device 119. To minimize power, the dedicated circuits 167-169 may have been in a low power state, such as an inactive state, because the elements 147-149 were empty. While in this low power state, the AACS 120 actively varies these dedicated circuits in a manner that minimizes power consumption, while preventing asymmetrical aging. When the computer system 117 connects to the element 147, a control signal disables the AACS 120 asymmetrical aging control of the dedicated circuit 167 and subsequently enables the dedicated circuit 167 communication with element 147. In response, the AACS 120 stops actively varying the dedicated circuit 167, while still actively varying the element 169. Thus, the AACS 120 may only minimize power consumption, while preventing asymmetrical aging for dedicated circuits in a low power state.
The environmental drawing is only one of many possible environments where the AACS 120 may be used. For example, numerous alternative implementations may result from adding more than one ASIC or having the ASIC 130 exchange data between more than one group of elements. In an alternative implementation, the AACS 120 may be included within another type of device, such as a security system, server, or the like. For that implementation, the elements 140 may be expansion slots for additional security feeds or increased server capacity respectively; the device 117 may be a video camera or a hard disk drive. In short, the AACS 120 may be used in any environment where there are unutilized components that may be used at some time in the future.
The dedicated circuit 210 may include numerous devices 220 that use a scan path, or scan ring, 225. For example, the devices 220 may be data flip-flops that may utilize a scan path arrangement for serially passing data from one flip-flop to the next. While the scan path 225 is shown with logic devices 220 that make the ring, the dedicated circuit also includes a cloud 230. This cloud is a pictorial representation of various logic devices that may either receive from or transmit data to one of the logic devices 220 within the scan path. As illustrated, this cloud of logic devices may receive the input signal 212 directly or the input signal may be sent to a device 232 on the scan path 225. Also, the cloud 230 may directly receive data from or transmit data to one of the devices 220 on this scan path. Similarly, the output signals 214 may come directly from the cloud 230. Alternatively, the output signal may come directly from either device 234 or device 236. In another implementation, the cloud may also receive the output signal from the device 234. Moreover, these are merely a few of the many possible implementations of the dedicated circuit 210.
The asymmetric control logic 310 also includes a register 314 and a counter 316 that receives a functional clock; this register and counter are elements within the generator 180 described with reference to
Finally, the block diagram 300 can also include an output device 330 that prevents the output signal 309 from changing state when AACS is enabled. As a result, dedicated circuit 320 appears inactive to other circuits. Note that output signal 309 may be a single output or a multitude of outputs that need to be placed into an inactive state. This output device controls when the output signal 309 leaves this dedicated circuit. The output device 330 may be a single logic gate, combination of logic gates, or a state machine. For example, this output device may be an AND gate in one implementation.
The operation of the block diagram 300 may vary depending on whether it is either active or inactive. The register 314 may be a scan register that transmits a pseudo-random pattern to the selection device 317. In contrast, the control logic 312 may transmit scan data and an enable to this same selection device. By receiving a functional clock, the counter 316 may transmit a first count signal that the selection device 318 receives and a second count signal that the selection device 319 receives. The first count signal may differ from the second count signal by one, two, or the like. For example, the count signal to the selection device 319 may toggle at twice the rate of the count signal to 318. In the implementation illustrated in
Using the asymmetric aging control logic 310, it injects pseudo-random data for each scan cycle and then evaluates the data from the previous scan cycle during the capture cycle. More specifically, the counter 316 may transmit the first count signal to the selection device 318 using the most significant bit, or MSB. Using the MSB to clock the register 314 also allows generation of new random data for each scan cycle. When the selection device 318 receives this first count signal, this selection device may enable a scan mode, such that the selection device 317 transmits the pseudo-random data received from the register 314. At some point later, the first count signal may change state such that the selection device 318 may enable a capture mode. In this mode, the previously scanned data propagates through the sub-chip 320. To facilitate the switching between a scan mode and a capture mode, the counter 316 transmits a second count signal to the selection device 319 using the MSB-1, which has a frequency of approximately twice the frequency of the signal sent to the MSB. Consequently, the asymmetrical aging control 310 toggles both a scan path associated with the scan mode and a functional path associated with the capture mode. The selection device 319 toggles the clock input of the dedicated circuit 320 by using the second count signal and the functional clock. This toggling may be done at one of many frequencies, such as approximately 1 Hz, 1.5 Hz, 2 Hz, or some other suitable frequency.
In block 410, asymmetric aging control (AAC) may be enabled on all dedicated circuits associated with the element group 140. Elements may be any kind of sub-system, such as port logic or any low frequency use function where the circuit is off for an extended period of time. This enabling may be done during an initialization mode. Block 410 is followed by block 420. In this block, the AAC is disabled for all active dedicated circuits. In other words, active dedicated circuits are dedicated circuits that will be currently utilized. This block may include additional blocks used in assessing the state of all dedicated circuits and categorizing them as dedicated circuits to be activated or dedicated circuits to be inactivated. For example, dedicated circuits to be inactivated may include dedicated circuits that may be for adding capacity at some point in the future, but may not be desired at this point.
Block 430 follows block 420. In block 430, all associated dedicated circuits may be activated. This activation may be done by performing whatever tasks necessary to enable to the dedicated circuits to execute under normal operating conditions, which may vary from system to system. In block 440, all the dedicated circuit's states are monitored. This monitoring may be done programmatically, mechanically, or by some other suitable technique. For a programmatic solution, this monitoring may involve periodically sending a test signal and assessing whether the resulting signal is either inside or outside of a given threshold. Alternatively, this monitoring may be done mechanically by applying a predetermined voltage and waiting until the addition of a dedicated circuit causes a state change or variation from the threshold. In addition, this block may determine whether a dedicated circuit should be inactivated or if the AAC should be inactivated. This determination may involve analyzing either a dedicated circuit's possible functionality relative to overall system needs or additional capacity, such as bandwidth or storage.
If a dedicated circuit should be activated, block 450 receives a dedicated circuit activate request. In response to receiving this request, block 450 disables the AAC on the associated dedicated circuit. This process may involve identifying the dedicated circuit mentioned in the request, identifying the AAC associated with dedicated circuit, and transmitting a disable for AAC via associated signal 305 for example. In block 460, the associated dedicated circuit is activated. This may involve fully powering the associated dedicated circuit.
If a dedicated circuit should be de-activated, block 470 receives a dedicated circuit de-activate request. In response to receiving this request, block 470 deactivates the associated dedicated circuit via associated signal 305 for example. This process may involve identifying the dedicated circuit mentioned in the request, identifying the AAC associated with the dedicated circuit and transmitting a disable for the identified dedicated circuit. In block 480, the AAC is activated. This may involve toggling as described with reference to
While various embodiments of the asymmetric aging control system have been described, it may be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of this system. Although certain aspects of the asymmetric aging control system may be described in relation to specific techniques or structures, the teachings and principles of the present system are not limited solely to such examples. All such modifications are intended to be included within the scope of this disclosure and the present asymmetric aging control system and protected by the following claim(s).
