Patent Application
20130176060
The technical field of this invention is clock timing circuits.
VLSI hardware modules designed to be used in a variety of products have become increasingly important as the complexity and cost of designing complex products has increased. Texas Instruments has recently labeled such modules as generic engineering modules (GEM). In these modules there are multiple clock domains allowing for operation of various parts of the chip at frequencies optimized for speed and power dissipation trade-off. Multiple clocks entering a GEM megamodule, although synchronous to each other, can cause on-chip variations (OCV) also known as clock skew.
Clock dividers used to generate the optimized frequency clock signals typically reside as separate hardware blocks adjacent to a centrally located phase-locked loop (PLL). This commonly used technique establishes tight control over the occurrence of clock edges at multiple frequencies. These clock dividers issue clocks to the various domains within the GEM. The GEM is subject to OCV issues having to do with clock balancing (skew reduction) and static-timing analysis (STA) closure difficulties.
In prior art, clock dividers 112, 113 and 114 often reside at a central location near the PLL and within the megamodule. These dividers generate sub-multiple frequency clocks supplementing the highest speed clock coming directly from PLL 101 via delay element 102. Normally one or more clocks generated by dividing the PLL clock down to sub-multiples of the PLL clock are needed to optimize the design for speed and power dissipation. Test clock input (TCK) 131 allows use of test clock to be substituted for the free-running PLL-based clocks during test operations. FIG. 1 illustrates PLL clock and three sub-multiple clocks. These are: PLL frequency clock 121; PLL frequency divided by two clock 122; PLL frequency divided by three clock 123; and PLL frequency divided by four clock 124.
Synchronization of these clocks is controlled by signals from outside the GEM, which guarantees that each clock starts at the identical time.
This invention definitively establishes the occurrence of various clock edges used in a design, balancing clock edges at various locations within the chip. Clocks entering a chip from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers at remote locations on the chip minimizing uncertainty of the edge occurrence. These special purpose clock dividers often reside at multiple locations within the GEM. They generate the highest speed clock coming directly from the PLL and one or more local clocks by dividing the PLL clock down to sub-multiples. The synchronization of the clocks is controlled by signals from outside the GEM. This guarantees that each clock starts at a tightly controlled time. Because the clocks are distributed at the remote points-of-use physically inside GEM, it is straightforward to control the required clock enables for different modes: functional; and design-for-test (DFT).
These and other aspects of this invention are illustrated in the drawings, in which:
The GEM clock dividers of the present invention are designed to support the following features: Alignment at power-up reset (POR); EFUSE Programmable chain divider ratio, tie-off or EFUSE switching; Design for Test (DFT) clock shaper support; CATSCAN support; and Test-mode support. GEM dividers continue to run even when their outputs are gated off.
Each clock generator module contains two major blocks: respective finite state machines 205, 215 and 225; and respective clock gating elements 206, 216 and 226. Input signals to each clock generator include: PLL clock 203; corresponding two bit divide ratio command Div_A[1:0], Div_B[1:0] and Div_C[1:0] coded as according to Table 1; and corresponding two bit selection signals SELA[1:0], SELB[1:0] and SELC[1:0] coded according to Table 2.
The clocking system of the present invention illustrated in
Table 1 lists the coding of the two bit divide ratio commands Div_A[1:0], Div_B[1:0] and Div_C[1:0]. As illustrated in
Table 2 lists the coding for the two bit clock signals SELA[1:0], SELB[1:0] and SELC[1:0]. Note that one such two-bit code is supplied to each clock generator. The three commands SELA[1:0], SELB[1:0] and SELC[1:0] are coded the same.
The required clock frequencies in the divider are generated from one high-speed clock locally by controlling the enable for the clock gate of each clock. On-chip variation in the clock tree is greatly reduced in such an implementation since frequency division is implemented locally.
Finite state machines 300 and 320 generate enables to clock gates 318 and 338, which in turn generate actual clocks 316 and 336. The outputs of these state machines are just control signals [Q] and not the actual clock. The description that follows refers to clock generator 300 at the top of
Register 304 is set to an initial state by a clear signal 319 from the PLL. This signal makes sure that all state machines are in the same initial state. Register 304 is a multiple bit counter, the number of bits depending on the clock that needs to be generated. Multiplexer 302 supplies input data bits to register 304. One input of multiplexer 302 is the output of incrementer 303. The other input 305 is a reset value which is typically the same value used to initialize the state machine. Select signal 301 for multiplexer 302 results from comparison of the register output [Q] and a pre-defined value that depends on the clock to be generated. For example, this value will be “001” to generate a clock whose frequency is PLL clock 203 divided by 2. When the register output [Q] equals this value “001”, select signal 301 causes multiplexer 302 to pick input 305 which initializes the register to its reset value. This initial value could be “000.” Thus the output Q will toggle between “000” and “001”. For a state machine that is responsible for generating PLL clock divided by 3, this sequence will be “000”, “001”, “010”, and then back to “000”, the initial state.
Register 304 a bank of registers. The clock input to register 304 is an ungated PLL Clock 308. Each clock feeding modules required in the system will have its own state machine or multiple machines depending on the requirements of the module. For example, a module that requires PLL divided-by-2 clock will have only one such finite state machine generating a single clock functional enable 325.
A module that needs to switch between multiple clocks based on either a tie-off or electrical fuse (effuse) value will have multiple state machines. Each state machine generates a separate enable. As an example, consider a module that requires PLL clock 203 divided by 2, 3 and 4, but requires only one to be active at a time with the flexibility to switch between. This example requires three state machines, each generating a gating output similar to clock functional enable 325. These will be multiplexed based on divider ratio signals Div_Ratio_A 317 or Div_Ratio_B 337.
A large number of such combinations are possible depending on the type and number of state machine and enables employed. These enables are then multiplexed with other enables in the system, which could be a DFT enable 340, or an enable that requires the module to use an external clock 341. This is determined by the signal SEL[1:0] 315, which is active when the module is in test mode rather than in functional mode. SEL[1:0] is also active if the clock used by this module is an internally generated clock or an external clock.
The module clock generator function of
In
Table 3 shows a reduction in both the set-up time uncertainty and the hold time uncertainty from about 200 psec in the prior art to much less than 200 psec using the invention.
Since the duty-cycle of the divided clocks is not 50%, two additional requirements must be met in order to use this type of pulse-controlled dividers successfully. These are:
Certain hard-macros (SRAMs) and special cells have clock duty-cycle requirements. Before using this divider implementation, the duty cycle requirement of all the cells should be carefully reviewed; and
If negative-edge triggered flops are used in the design, they will essentially be timed at frequency of f_0501 using this divider implementation.
