1. Field of the Invention
Embodiments of the present invention generally relate to asynchronous sample rate conversion using polynomial interpolation in digital signal processing.
2. Description of the Related Art
Many audio systems are required to handle audio streams with various sample rates, from the low rates found in many .WAV files such as 8 kHz to the high rates of consumer audio equipment such as 48 kHz. Rather than processing the audio at the sample rate of the audio signal, such audio systems may perform sample rate conversion (SRC) to convert an input sample rate to a common sample rate at which the processing is performed. For integer ratio sample rates, SRC can be performed by interpolation, low pass filtering, and decimation. However, filters for digital SRC can be cumbersome when input and output sample rates have a very large least common multiple, or the conversion ratio is irrational or slowly changing.
The irrational or slowly changing case is typically called an asynchronous sample rate conversion (ASRC), and a well-known conversion technique oversamples an input signal, converts it to a continuous signal by zeroth-order hold (ZOH), and then samples the continuous signal at the output sample period. However, to reduce ZOH distortion, the oversampling ratio has to be very large. For example, the ratio of 216 has been reported to be adequate to achieve 16 bit accuracy. However, a large oversampling ratio requires a large number of filter coefficients and thus a larger amount of memory for storing the coefficients.
An alternative approach is to use polynomial interpolation. With polynomial interpolation, a fixed length of polynomial coefficients allows any high oversampling ratio up to infinity without loss of performance in terms of frequency response. Thus, ZOH is no longer necessary. Further, if the input signal bandwidth is known a priori to be narrow enough compared with the both input/output sample rates, a polynomial interpolator running stand-alone works sufficiently as a whole SRC system. If it is not the case, the polynomial interpolator can be used with a simple oversampler or downsampler. For example, United States Patent Publication No. 2009/0077149, entitled “Asynchronous Sampling Rate Conversion,” presents an SRC system that first oversamples the input signal by an integer ratio, followed by a polynomial interpolator. United States Patent Publication No. 2009/0319065, entitled “Efficient Asynchronous Sample Rate Conversion,” presents another example in which a polynomial interpolator first converts the input sample rate to multiple of the sample rate of the output, which is then processed with a simple downsampler. U.S. Patent Publication No. 2009/0077149 and U.S. Patent Publication No. 2009/0319065 are incorporated by reference herein in their entirety.
Embodiments of the invention relate to methods for sample rate conversion of an input signal using a polynomial interpolator with minimax stopband attenuation. In one aspect, a method for sample rate conversion of an input signal is provided that uses a time-varying polyphase filter having a discrete polyphase index m. The method includes computing a discrete time index k at which an output sample is to be generated as a maximum integer result of Mt where M is an oversampling ratio and t is a time of the output sample, mapping the discrete time index k to an input sample index T and the discrete polyphase index m wherein k=TM+m, and applying a time-varying polyphase filter to an input sample at input sample index T to generate an output sample at the time index k, where the discrete polyphase index m is used together with a set of polynomials to compute the time-varying polyphase filter coefficients.
In another aspect, a method for sample rate conversion of an input signal is provided that uses a time-varying polyphase filter having a continuous polyphase index τ. The method includes determining an output sample time t, mapping the output sample time t to an input sample index T and the continuous polyphase index τ where t=T+τ, 0≦τ<1, and applying a time-varying polyphase filter to an input sample at input sample index T to generate an output sample at the output sample time t, where the continuous polyphase index τ is used together with a set of polynomials to compute the time-varying polyphase filter coefficients.
Particular embodiments in accordance with the invention will now be described, by way of example only, and with reference to the accompanying drawings:
Specific embodiments of the invention will now be described in detail with reference to the accompanying figures. Like elements in the various figures are denoted by like reference numerals for consistency.
Embodiments of the invention provide sample rate conversion using a design method for a polynomial interpolator that minimizes stop-band error. That is, in contrast to prior art design methods, the new design method minimizes the highest stop-band ripple in the frequency domain. This is done by applying a weight function that is adaptively updated in each iteration of the weighted least squares polynomial fitting. The polynomial coefficients are optimized such that the frequency response of the polynomial filter is as close to the ideal response for audio SRC applications as possible. Due to its “minimax” characteristics, the new design method out performs other types of polynomial interpolators such as the polynomial interpolator described in U.S. Patent Publication No. 2009/0077149, B-Spline polynomical interpolators, and the Lagrange polynomial interpolators in terms of frequency response. Several modifications to the design method such as drooping of the pass-band response to further improve the stop-band attenuation and optimizations to reduce the computational load of the design method are also provided.
The oversampling filter plays a role of reducing the mirror components that were generated by the zero-insertion. ZOH is performed to simulate a pseudo continuous signal from the oversampled signal (
As
As can be seen in
The mirror images can be eliminated by a low-pass filter H(z) that has stop-bands in such mirror regions (
As per
k=└Mt┘, (4)
where the └•┘ operator maps to the maximum integer that does not exceed the original value (i.e., truncation). Using the time index k, the signal y(k) is calculated and goes out as an output sample.
The above procedure illustrates a conceptual implementation of an SRC that is not used in practice because of the number of zero-multiplications of Eq. 3. Instead, a polyphase implementation of H(z) is typically employed to avoid such unnecessary calculations. When the index k at which an output sample is to be created is determined, the input sample index T and the polyphase index m can be uniquely determined such that
k=TM+m, 0≦m<M. (5)
Substituting Eq. 1 into Eq. 3,
In Eq. 6, pl(m) is a set of M polyphase filters with length 2L and s(T−l) are the buffered input samples.
where α<1. U.S. Patent Publication No. 2009/0077149 suggests that the ROM size for storing pl(m) can be drastically reduced by replacing it with a polynomial,
where N is the order of the polynomial. From Eq. 6, a class of polynomial interpolator is derived as
where l is the input sample count when the input/output sample rate ratio is fixed, or otherwise by an adaptive ratio tracker such as those found in U.S. Patent Publication No. 2009/0319065, U.S. Pat. No. 7,345,600, and D. Wenzel and J. Speidel, “A Digital Asynchronous Sample-Rate Converter for Digital Video Signals,” IEEE Trans. Consumer Electronics, vol. 46, no. 1, pp. 207-214, February 2000.
Once t is determined, Eq. 4 is used to determine k and Eq. 5 is used to determine T and m. Then, as per Eq. 8, the index m is used by the coefficient calculator 406 to calculate the filter coefficients while the input sample index T determines the input samples from the buffer 402 to be processed with the polynomial filter 404 to produce the output signal y(k).
The interpolation formula of Eq. 8 can be extended to continuous interpolation. That is, once the fractional output time t is given, the output signal y(t) can be computed without time truncation to k. Similar to Eq. 5, there is a unique projection of t to integer part T and fractional part τ, such that
t=T+τ, 0≦τ<1. (9)
Then, Eq. 8 is modified to
Thus, the ZOH module (see
The SRC systems 400 of
U.S. Patent Publication No. 2009/0077149 discloses an SRC system 500 as shown in
U.S. Patent Publication No. 2009/0319065 discloses an SRC system 600 as shown in
The SRC system 600 works for any conversion ratio for downsampling. However, for upsampling, an anti-mirror filter should be appended to eliminate the mirror images remaining in the range [Fin/2μFout/2].
As previously mentioned, the SRC system 500 of
Several possible SRC systems that incorporate a polynomial interpolator have been described. A design method for a polynomial filter that may be used in such SRC systems is now derived.
As per Eq. 6, the definition of the set of polyphase filters pl(m) is given by
pl(m)=h(lM+m). (12)
The Fourier transform of pl(m), P(m,ejω) may be calculated to be
where j2=−1. Using Eq. 11 and Eq. 13, the ideal response of the polyphase filter {tilde over (P)}(m,ejω) is given as
The actual frequency response of the polyphase filter pl(m) after using the polynomial interpolator of Eq. 7 is
Thus, the design problem reduces to an optimization problem for cl,n such that
J=∥εm(ejω)∥ (16)
is minimized, where ε is the error function defined by
εm(ejω)={tilde over (P)}(m,ejω)−P(m,ejω). (17)
Eq. 16 may be solved in the minimax sense, i.e., by iterating the weighted least squares solution while adaptively updating the weight function. For the least squares solution, Eq. 16 can be rewritten as
where W(ω) is the weight function and * denotes the conjugate. The least-squares solution is derived by taking partial derivatives of Eq. 18 with respect to cl,n, and setting the results to zero. Using the relationship
which can be derived from Eq. 15 and Eq. 17, we can write
Substitution of Eq. 15 and Eq. 17 into Eq. 20 with significant simplification provides
for n=0, . . . , N and l=−L, . . . , L−1, where functions a(n) and b(x) respectively are defined by
After solving Eq. 21, the frequency response H(ejω) of the polynomial interpolator is calculated. As per Eq. 7 and Eq. 12, H(ejω) may be calculated as
In stop bands, the frequency response H(ejω) directly indicates the error function, as the ideal response is zero there.
The weight function W(ω) cannot be controlled over all stop-bands because W(ω) is defined in the range 0≦ω≦απ, while there are stop-bands in kπ−απ≦ω≦kπ+απ, k=2, 4, . . . . Therefore, the errors lying in these regions are mapped onto 0≦ω≦απ. This can be done by taking the maximum error among k=2, 4, . . . . In other words, the error function defined by
is evaluated for 0≦ω≦απ, where H(ejω) is defined by Eq. 24.
Then, the polynomial coefficients may be iteratively optimized as follows. At the first iteration ρ=1, set W1(ω)=1 for 0≦ω≦απ. For each iteration until convergence is reached, solve Eq. 21, calculate the error function as per Eq. 26, and update Wρ(ω) for the next iteration, using Wρ+1(ω)=Wρ(ω)E(ω), 0≦ω≦απ. After each iteration, check for convergence. If convergence has not been reached, update ρ←ρ+1 and perform another iteration. Any suitable test for convergence may be used. For example, convergence may be found when the difference between the maximum and minimum in E(ω) is under a threshold or the change in cl,n is under a threshold.
As disclosed in U.S. Patent Publication No. 2009/0077149, the stop-band attenuation can be improved by shaping the pass-band of the interpolator with a droop curve. The pass-band droop is acceptable when the polynomial interpolator is used with an additional oversampler or downsampler, namely H1(z) as in
To allow the minimax polynomial interpolator to have a droop shape in the pass-band, the ideal response of the polynomial filter that was given by Eq. 11 is modified to
where D(ω) represents the droop function. By substituting Eq. 27 into Eq. 13, the ideal polyphase filter response of Eq. 14 is modified to
After working on Eq. 28 with the same procedures described above for the weighted least squares solution, a modified linear equation regarding the polynomial coefficients is obtained, i.e.,
where a(n) and b(x) respectively are defined by Eq. 22 and Eq. 23, and d(x) is defined by
d(x)=∫0απD(ω)W(ω)cos(ωx)dx. (30)
The minimax solution of the droop filter may be found in a similar fashion to the minimax solution of the filter without the droop curve using Eq. 29 instead of Eq. 21.
D(ω)=1−0.05ω2.
This figurer shows that the pass-band edge was reduced to to 1−0.05(απ)2, or −1.14 dB and the maximum stop-band error was reduced to −65 dB.
Thus far, the oversampling ratio M has been assumed to be a finite value in the filter design process. Polynomial filters so designed can work for oversampling signals by any high M values up to infinity, without loss of stop-band performance. This can visually be understood in
In spite of the above fact, it is still interesting to modify the design method to allow M→∞ in the design process. To do this, Eq. 21 and Eq. 22 are normalized by M and let M→∞ which results in
For the droop version of polynomial interpolator, Eq. 31 applies with the replacement of b(x) with d(x), i.e.,
Also in the optimization process, the frequency response of H(ejω) in Eq. 24 is modified to
At each iteration of the coefficient optimization, one of the sets of linear equations of Eq. 21, Eq. 29, Eq. 31, and Eq. 33 is solved, which are order of 2L(N+1). When L and N increase, directly solving these equations will require increased computation time which could be a problem in some applications. For example, the Gaussian elimination and Cholesky decomposition take O((LN)3) to solve those equations. One solution is to factorize the linear equations.
The equations Eq. 21, Eq. 29, Eq. 31, and Eq. 33 can be rewritten with the following generalized formula:
The vector-matrix expression of Eq. 36 is
and T denotes transpose. Note that here the relationship b−x=bx is used, which is obvious because of Eq. 23.
The matrix G is factorized to
and I is the 2L×2L identity matrix. Therefore, the solution of the above linear equations may be found as follows. First, solve the order-2L linear equations
for φl,n, n=0, 1, . . . , N. Then, solve the order-N+1 linear equations
for cl,n, l=−L, −L+1, . . . , L−1.
Both Eq. 38 and Eq. 39 can be solved by using the Levinson algorithm, as the coefficient matrices have toeplitz structure. As the Levinson algorithm takes O(N2) of computational load for solving order-N equations, the entire computational load of solving Eq. 38 and Eq. 39 will be O(LN(L+N)), which is significant savings as compared with the other solutions such as Gaussian elimination and Cholesky factorization which take O((LN)3).
The polyphase filter coefficients pl(m) are then computed using the polyphase index 1302 and the polynomial coefficients cl,n as per Eq. 7. A method for computing the polynomial coefficients cl,n is described below in relation to
The ASRC 1405 includes functionality to perform a sample rate conversion method as described herein. Further, the ASCR 1405 operates according to different methods for upsampling and downsampling under the control of the system controller 1430. That is, the system controller 1430 determine whether the input sample rate is above or below the output sample rate of the digital audio processor 1402, and issues a control signal to the ASCR 1405 accordingly. The output of ASRC 1405, which is at the sample rate the digital audio processor 1402, is applied to one input of the multiplexer 1406.
The digital audio receiver is also configured to receive analog audio signals. The analog-to-digital converter (ADC) 1404c converts analog stereo signals from analog line-in inputs CH_IN and from tuner 1413 to a digital data stream, and provides this data stream to another input of the multiplexer 1406. Because the sampling frequency of the ADC 1404c can be selected by the system designer, that sampling frequency will typically be selected to match the frequency at which the digital audio processor 1402 operates (e.g., 48 kHz), thus not requiring sample rate conversion. However, if the output of the ADC 1404c were at a different sample rate, these signals would also be applied to the ASRC 1405. The multiplexer 1406 chooses one (or both) of these inputs for application to the digital audio processor 1402, under the control of the system controller 1430.
The audio source selected by the ASRC 1405 and the multiplexer 1406 is under user control; in this regard, system controller 1430 receives direct selection inputs from the front panel switches 1425, or infrared remote control signals via the infrared receiver 1427, both communicating with the system controller 1430 via the interface circuitry 1428. As, system controller 1430 provides audio source selection signals to ASRC 1405 and multiplexer 1406, and channel volume control signals to PWM audio processor 20. The system controller 1430 also provides other control signals throughout the digital audio receiver, including channel selection control to the tuner 1406 in response to user inputs received via the front panel 1425 or the infrared receiver 1427, and operational control signals applied to digital audio processor 1402.
The digital audio processor 1402 is an integrated circuit, or integrated circuit core, for decoding and digitally processing the digital audio signals from the multiplexer 1406. Alternatively, the digital audio processor 1402 may be implemented as part of a larger-scale integrated circuit for decoding and processing digital video and audio signals. In either case, examples of functions performed by digital audio processor 1402 include decoding of the incoming digital data, applying the various digital audio data to corresponding channels supported by the digital audio receiver, applying digital filters, and formatting the digital audio data into a pulse-code-modulated (PCM) format. The PCM signals for each channel are then forwarded to the pulse-width-modulation (PWM) audio processor 1420. An additional interpolation function may be provided between the digital audio processor 1402 and the PWM audio processor 1420 (or included within PWM audio processor 1420) to increase the sample rate (e.g., by a factor of eight) to the desired pulse-width modulated frequency (e.g., 384 kHz).
The PWM audio processor 1420 converts the PCM digital audio signals at its inputs to corresponding pulse-width-modulated (PWM) signals output signals for four channels, in this example. For each of these four channels, the PWM audio processor 1420 produces separate PWM control signals that are applied to a corresponding power amplifier stage 1422a through 1422d, each of which drives a respective one of loudspeakers SPKR_1 through SPKR_4. More or fewer channels may be supported by the digital audio receiver. The PWM audio processor 1420 includes circuitry for controlling the volume of the audio output, performing the functions of parametric speaker equalization or “voicing”, implementation of graphic equalizer presets, treble and bass adjustment, and precision soft volume control on the audio signal being processed for its channel. Other digital functions that can be performed by the PWM audio processor 1420 include loudness compensation to boost bass frequencies when the output for the channel is low, dynamic range compression, background noise floor compensation or noise squelch, center or sub-woofer channel synthesis, programmable dither, peak limiting and clipping, and other digital filter processing.
In
While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein.
Embodiments of the invention may be performed in many different types of digital systems, e.g., digital audio players, personal computers, laptop computers, and table computers with multimedia capabilities, etc. In such digital systems, embodiments of the sample rate conversion systems and methods described herein may be implemented in hardware, software, firmware, or any combination thereof. The methods may be executed in one or more processors, such as a microprocessor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), digital signal processor (DSP), or a system on a chip (SoC) combining one or more such processors with specialized programmable accelerators. Any software instructions may be stored in onboard or external memory and executed by the one or more processors.
It is therefore contemplated that the appended claims will cover any such modifications of the embodiments as fall within the true scope of the invention.
This application claims benefit of U.S. Provisional Patent Application Ser. No. 61/381,508, filed Sep. 10, 2010, which is incorporated by reference herein in its entirety.
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Sigmar Ries, “A Class of Sampling Rate Converters with Interesting Properties”, Preprint 5827, presented at the 114th Convention of the Audio Engineering Society, Mar. 22-25, 2003, Amsterdam, The Netherlands, pp. 1-13. |
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20120066280 A1 | Mar 2012 | US |
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61381508 | Sep 2010 | US |