ASYNCRONOUS RESETTING INTEGRATED CIRCUITS

Abstract

A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.

Description

Claims

1. A method, comprising: electrically connecting a plurality of flip-flops in a predefined series, wherein each flip-flop in the predefined series has a scan input gate, a Q output gate and a Q-bar output gate and wherein one of the Q output gate or the Q-bar output gate is electrically connected to the scan input gate of an adjacent flip-flop in the predefined series; andfeeding a bit string through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops.

2. The method of claim 1, further comprising producing a scan out chain of bits from either the Q output gate or the Q-bar output gate of a final flip-flop in the predefined series, wherein the scan out chain of bits is different from the bits of the bit string.

3. The method of claim 1, wherein electrically connecting the plurality of flip-flops in the predefined series includes electrically connecting in series each of a first series of flip-flops to an adjacent flip-flop in the first series between the Q output gate and the scan input gate.

4. The method of claim 1, wherein electrically connecting the plurality of flip-flops in the predefined series includes electrically connecting in series each of a second series of flip-flops to an adjacent flip-flop in the second series between the Q-bar output gate and the scan input gate.

5. The method of claim 1, wherein each flip-flop of the plurality of flip-flops comprises an edge-triggered device or a level-triggered device.

6. The method of claim 1, wherein the bits for feeding the bit string are all zeros or all ones.

7. A method, comprising: receiving a bit string of identical bits at a scan gate input of a first flip-flop in a predefined series of flip-flops;outputting a first predefined bit from one of either a Q output gate or a Q-bar output gate for each of the identical bits in the bit string from the first flip-flop in the predefined series of flip-flops; andinputting the first predefined bit from the first flip-flop to a scan gate input of a subsequent flip-flop in the predefined series of flip-flops to eliminate receipt of signaling indicative of a reset operation to reset gates in the plurality of flip-flops.

8. The method of claim 7, further comprising feeding the bit string comprising the identical bits through the scan input gate of the first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops in the absence of signaling indicative of performance of a reset operation.

9. The method of claim 7, wherein the bit string of identical bits is all zeros or all ones.

10. The method of claim 7, further comprising outputting a second predefined bit from one of either a Q output gate or a Q-bar output gate for each of the first predefined bit from the first flip-flop; and inputting the second predefined bit from the first subsequent flip-flop to a scan gate input of a second subsequent flip-flop in the predefined series of flip-flops.

11. The method of claim 10, wherein the first predefined bit is identical to the second predefined bit.

12. The method of claim 7, further comprising electrically connecting one of either a Q output gate or a Q-bar output gate of the flip-flops in the series of flip-flops to the scan input gate of an adjacent flip-flop in the series of flip-flops.

13. The method of claim 12, further comprising producing a scan out chain of bits from a final flip-flop in the predefined series, wherein the scan out chain of bits is different than the identical bits of the bit string.

14. An apparatus, comprising: a plurality of flip-flops, wherein each flip-flop in the plurality of flip-flops has a scan input gate, a Q output gate and a Q-bar output gate, wherein one of the Q output gate or the Q-bar output gate of each flip-flop is electrically connected to the scan input gate of an adjacent flip-flop of the plurality of flip-flops; andcircuitry configured to provide a bit string of identical bits that is received at the scan input gate of a first flip-flop of the plurality of flip-flops for the resetting of the apparatus.

15. The apparatus of claim 14, wherein one of either the Q output gate or the Q-bar output gate being electrically connected to the scan input gates of the adjacent flip-flop in the plurality of flip-flops provides a preset physical digital logic path for the apparatus.

16. The apparatus of claim 14, wherein bit string of identical bits are all zeros or all ones.

17. The apparatus of claim 14, wherein a quantity of the identical bits in the bit string is larger than the number of flip-flops in the plurality of flip-flops.

18. The apparatus of claim 14, wherein at least one flip-flop of the plurality of flip-flops does not include a reset input or a set input.

19. The apparatus of claim 14, wherein the apparatus does not include reset circuitry.

20. The apparatus of claim 14, wherein the apparatus includes reset circuitry.

21. The apparatus of claim 14, wherein the first flip-flop of the plurality of flip-flops starts a predefined series of sequential flip-flops, wherein each of the flip-flops in the predefined series is electrically connected to a single adjacent flip-flop in the predefined series through one of the Q output gate or the Q-bar output gate.

22. The apparatus of claim 14, wherein the apparatus is an application-specific integrated circuit (ASIC).