The present disclosure relates generally to the field of processors and in particular to a method testing multi-port memory arrays at operating frequency.
Microprocessors perform computational operations in a wide variety of applications. A processor may serves as a central or main processing unit in a stationary computing system such as a server or desktop computer. High execution speed is a primary consideration for such desktop processors. In addition, processors are increasingly deployed in mobile computers such as laptops and Personal Digital Assistants (PDAs), and in embedded applications such as mobile phones, Global Positioning System (GPS) receivers, portable email clients, and the like. In such mobile applications, in addition to high execution speed, low power consumption and small size are desirable.
Many programs are written as if the computer executing them had a very large (ideally unlimited) amount of fast memory. Commonly modern processors simulate the ideal condition of unlimited fast memory by employing a hierarchy of memory types, each having different speed and cost characteristics. The memory types in the hierarchy vary from very fast and very expensive at the top, to progressively slower but more economical storage types in lower levels. A common processor memory hierarchy may comprise registers (gates) in the processor at the top level; backed by one or more on-chip caches comprised of Static Random Access Memory (SRAM); possibly an off-chip cache (SRAM); main memory Dynamic Random Access Memory (DRAM); disk storage (magnetic media with electromechanical access); and tape or Compact Disc (CD) (magnetic or optical media) at the lowest level. Most portable electronic devices have limited, if any, disk storage, and hence main memory, often limited in size, is the lowest level in the memory hierarchy.
High-speed, on-chip registers comprise the top level of a processor memory hierarchy. Discrete registers and/or latches are used as storage elements in the instruction execution pipeline. Most RISC instruction set architectures include a set of General Purpose Registers (GPRs) for use by the processor to store a wide variety of data, such as instruction op codes, addresses, offsets, operands for and the intermediate and final results of arithmetic and logical operations, and the like.
In some processors, the logical GPRs correspond to physical storage elements. In other processors, performance is improved by dynamically assigning each logical GPR identifier to one of a large set of storage locations, or physical registers (commonly known in the art as register renaming). In either case, the storage elements accessed by logical GPR identifiers may be implemented not as discrete registers, but rather as storage locations within a memory array. The registers or memory array storage elements implementing logical GPRs are multi-ported. That is, they may be written to, and/or their contents read by, several different processor elements, such as various pipeline stages, ALUs, cache memory, or the like.
Testing is an important part of IC manufacture, to identify and weed out defective or substandard components. Testing memory arrays is particularly problematic. Automatic Test Pattern Generation (ATPG) methodology comprises scanning an excitation pattern into one set of scan-chained registers or latches, applying the pattern to exercise random logic, capturing the results in another set of scan-chained registers or latches, and scanning the captured results out for comparison to expected values. Memory arrays cannot be efficiently tested using ATPG techniques due to the intermediate storage of test patterns in the array.
Memory arrays in a processor may be tested by functional testing, wherein code is executed in the processor pipeline to write test patterns to the array (e.g., to logical GPRs), then read the values and compare to expected values. Functional testing is time consuming and inefficient because the processor must be initialized and test code loaded into the cache prior to executing the tests. Additionally, the control and observation point—within the pipeline—is far removed from the memory locations being tested, and it may be difficult to isolate uncovered faults from intervening circuits.
Accordingly, many prior art processors with embedded memory arrays include a Built-In Self-Test (BIST) circuit that exercises the memory array during a test mode. A BIST controller writes data patterns to the memory array, reads the data patterns, and compares the read data to expected data. In functional mode, the BIST controller is inactive and the memory array is controlled by the processor control circuits. Prior art BIST systems include a dedicated test port in the memory array to write and/or read the array during testing. This places a lower boundary on the test duration by restricting memory access bandwidth; fails to test the memory I/O circuits, including the functional read and write ports; and may fail to uncover electrical marginalities that are only exposed when two or more ports access the array simultaneously.
According to one or more embodiments, a multi-port memory array is tested by a BIST controller by simultaneously writing data to the array via two or more write ports, and/or simultaneously reading data from the array via two or more read ports, at the processor operating frequency. Comparing the data read from the array to that written to the array may be performed sequentially or in parallel. Comparator circuits are effectively disabled during normal processor operations. By simultaneously writing and/or reading data via multiple ports, latent electrical marginalities may be exposed, and test time is reduced, as compared to prior art test methodologies.
One embodiment relates to a method of testing a memory array, having a plurality of write ports, in a processor. A first data pattern is writing to a first address in the array via a first write port. A second data pattern is simultaneously written to a second address in the array via a second write port. The first and second data patterns are read from the array. The first and second data patterns read from the array are compared to the first and second data patterns written to the array, respectively.
Another embodiment relates to a method of testing a memory array, having a plurality of read ports, in a processor. A first data pattern is written to a first address in the array. A second data pattern is written to a second address in the array. The first data pattern is read from the array via a first read port. The second data pattern is simultaneously read from the array via a second read port. The first and second data patterns read from the array are compared to the first and second data patterns written to the array, respectively.
Yet another embodiment relates to a method of testing a memory array in a processor. One or more predetermined data patterns are written to the array. The data patterns are simultaneously read from the array via two or more read ports, thereby exposing electrical marginalities in the array and/or the read ports not exposed by reading data via one read port at a time.
Still another embodiment relates to a processor. The processor includes a memory array having at least one write port and a plurality of latching read ports; a first data comparator having read data and compare data inputs, and outputting an indication whether the read data match the compare data pattern; and a first selector selectively directing data from two or more first read ports to the first comparator read data input. The processor additionally includes a BIST controller controlling the write port, first read ports, and first selector, providing write data to the write port and compare data to the first comparator compare data input, and receiving the first comparator output. The BIST controller operative to write one or more predetermined data patterns to the array via the write port; simultaneously read the written data from the array via two or more first read ports; and sequentially control the first selector to direct data from each first read port to the first comparator, provide corresponding compare data to the first comparator, and verify the array by inspecting the first comparator output.
The pipelines 12a, 12b fetch instructions from an Instruction Cache (I-Cache) 22, with memory addressing and permissions managed by an Instruction-side Translation Lookaside Buffer (ITLB) 24. Data is accessed from a Data Cache (D-Cache) 26, with memory addressing and permissions managed by a main Translation Lookaside Buffer (TLB) 28. In various embodiments, the ITLB may comprise a copy of part of the TLB. Alternatively, the ITLB and TLB may be integrated. Similarly, in various embodiments of the processor 10, the I-cache 22 and D-cache 26 may be integrated, or unified. Misses in the I-cache 22 and/or the D-cache 26 cause an access to main (off-chip) memory 32, under the control of a memory interface 30. The processor 10 may include an Input/Output (I/O) interface 34, controlling access to various peripheral devices 36. Those of skill in the art will recognize that numerous variations of the processor 10 are possible. For example, the processor 10 may include a second-level (L2) cache for either or both the I and D caches. In addition, one or more of the functional blocks depicted in the processor 10 may be omitted from a particular embodiment.
The particular memory array 20 depicted in
In test mode, the BIST controller 40 writes a background data pattern to the memory array 20 via write ports 42A, B, and/or C. The BIST controller 40 then writes test data patterns to one or more memory array 20 storage locations via write ports 42 A, B, and/or C. In at least some tests, the BIST controller 40 writes test data patterns via all a three write ports 40 simultaneously, to expose electrical marginalities in the memory array 20 that may not be observable when writing data through only one write port 42 at a time.
The BIST controller 40 then reads the test data patterns from the memory array 20 simultaneously via at least two read ports 44. To maximally stress the memory array 20 and expose any latent electrical marginalities, and additionally to minimize the test time, the BIST controller 40 simultaneously reads data via all available read ports 44 (i.e., all five read ports 44 in the embodiment depicted in
In the embodiment depicted in
Those of skill in the art will readily recognize that the number of comparators 48, 52 may be increased to further reduce test time by performing data comparisons in parallel. The test time may be minimized by providing a comparator 48, 52 for each read port 44 (obviating the need for a selector 46, 50). However, this increases silicon area, and may introduce wiring congestion, for test circuits that are not active during normal processor operation. At the other extreme, a single comparator 48, 50 may be provided, with data from all read ports 44 directed thereto via a single selector 46, 50. This minimizes the test circuitry, but places a lower limit on test duration, as each word in the memory array 20 must be compared sequentially. However, even with one comparator 48, 52, the memory array 20 may be more thoroughly and realistically tested than is possible with prior art test techniques, by simultaneously reading data via two or more (and up to all available) read ports 44.
The test apparatus and methodology disclosed herein additionally allows for more detailed diagnostics then prior art test systems, many of which are limited to a minimal functionality test (i.e., a go/no-go decision). The BIST controller 40 may write minimize test time by simultaneously writing test data patterns to three different storage locations via the three write ports 42, and simultaneously read data from five different storage locations via the five read ports 44. Alternatively, the BIST controller 40 may stress individual storage locations (and associated I/O circuits) by writing data to and/or reading data from a single storage location utilizing all available respective ports.
The test methodology is fully applicable to any memory array having two or more write ports 42 and/or two or more read ports 44.
Referring again to
Accordingly, the comparator circuits 48, 50 are effectively disabled during normal operations by ensuring that a constant data pattern is presented at the comparator 48, 52 data input. One input of each selector 46, 50 is tied to a constant data pattern, such as ground (as depicted in
Numerous latent electrical marginalities that may be exposed by simultaneously writing data patterns via two or more write ports 42, and/or by simultaneously reading data patterns via two or more read ports 44. Prior art test methods are completely unable to uncover these marginalities. When simultaneously writing data patterns via two or more write ports 42, multiple write drivers fire simultaneously. This stresses the power grid, which may expose marginalities. In addition, noise coupling between “quiet” and “switching” bit lines may be exposed.
Simultaneously reading data patterns via two or more read ports 44 may expose power grid marginalities by turning multiple prechargers “on” simultaneously. Similarly, multiple read bit lines are discharged simultaneously, which may also expose power grid marginalities. Power grid marginalities may further be exposed by multiple global and/or local word lines being turned “on” simultaneously. Noise coupling between “quiet” and “switching” bit lines may be exposed by multiple read bit lines being discharged simultaneously. In addition, multiple read data latch outputs switch simultaneously, causing coupling on long unshielded nets. This noise causes a delay pushout, which may expose noise and/or timing marginalities.
Although the present disclosure has been described herein with respect to particular features, aspects and embodiments thereof, it will be apparent that numerous variations, modifications, and other embodiments are possible within the broad scope of the present disclosure, and accordingly, all variations, modifications and embodiments are to be regarded as being within the scope of the disclosure. The present embodiments are therefore to be construed in all aspects as illustrative and not restrictive and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.