Claims
- 1. An ATM-port module for an ATM-node having an Ethernet switch, the ATM-port module comprising:
an ATM-controller; and an Ethernet-switch interface connecting the ATM-controller to the Ethernet switch.
- 2. The ATM-port module of claim 1, wherein the Ethernet-switch interface comprises:
an Ethernet encapsulating-unit for encapsulating ATM cells processed by the ATM-controller into Ethernet packets for transmission to the Ethernet switch, and an Ethernet decapsulating-unit for extracting ATM cells from Ethernet packets received from the Ethernet switch.
- 3. The ATM-port module of claim 1, wherein the ATM controller comprises:
an ATM-to-Ethernet signal path, and an Ethernet-to-ATM signal path.
- 4. The ATM-port module of claim 1, wherein the ATM-controller comprises a memory for storing:
a header look-up-table; and a queue look-up-table.
- 5. The ATM-port module of claim 4, wherein the header look-up-table is configured to store, for each detected ATM-cell header:
a corresponding port-address of a destination port of the ATM node; OAM parameters; and a queue number.
- 6. The ATM-port module of claim 5, wherein the queue number comprises a pointer to a corresponding entry in the queue look-up-table.
- 7. The ATM-port module of claim 5, wherein the queue look-up-table is configured to store, for each queue number:
corresponding queue parameters; and an indication flag indicative of a destination port of a received ATM cell.
- 8. The ATM-port module according to claim 7, wherein the indication flag is indicative of whether the destination port is an ATM port or an Ethernet port.
- 9. The ATM-port module of claim 3, wherein the ATM-to-Ethernet signal path comprises:
an ATM-header detector unit for detecting headers of received ATM cells; an ATM-OAM-processor for performing operation and maintenance functions depending on OAM parameters read from a queue look-up-table of the memory, a buffering-and-scheduling unit for buffering and scheduling the processed ATM-cells and for generating enlarged ATM-cells, each of which includes a port address of the ATM node, the port address being read from the memory.
- 10. The ATM-port module of claim 3, wherein the Ethernet-to-ATM-signal-path of the ATM controller comprises:
a buffering-and-scheduling unit for buffering and scheduling ATM cells received from the Ethernet-switch interface; an ATM-OAM-processor for performing operation and maintenance functions depending on OAM-parameters read from the memory; an ATM-header translator.
- 11. The ATM-port module according to claim 2, further comprising:
a segmentation-and-reassembly unit; and a buffering-and-scheduling unit for providing a processed enlarged-ATM-cell to the Ethernet encapsulating-unit when an indication flag indicates that an ATM port is a destination port of the enlarged ATM-cell; and providing a processed enlarged-ATM-cell to the segmentation-and-reassembly unit when an indication flag indicates that an Ethernet port is the destination port of the enlarged ATM-cell.
- 12. The ATM-port module according to claim 11,
wherein the segmentation-and-reassembly unit is configured to discard an ATM header of an enlarged ATM-cell; and the ATM-port module further comprises an Ethernet-packet generator for receiving an Ethernet packet having a payload that includes at least one ATM cell.
- 13. The ATM-port module according to claim 12, wherein the Ethernet-packet generator is configured to:
read interworking-type data from the memory, and to generate an Ethernet packet on the basis of the interworking-type data.
Priority Claims (1)
Number |
Date |
Country |
Kind |
PCT/EP02/02247 |
Mar 2002 |
WO |
|
RELATED APPLICATIONS
[0001] This application claims the benefit of the Mar. 1, 2002 priority date of PCT application PCT/EP02/02247, the contents of which are herein incorporated by reference.