Patent Grant
10063249
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2015-089557, filed Apr. 24, 2015, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to an audio circuit.
2. Description of the Related Art
An electronic device having a function of playing back an audio signal, examples of which include CD players, audio amplifiers, car stereo systems, portable radios, portable audio players, and the like, includes a sound processor that provides an audio signal with various kinds of signal processing.
An audio system 100 includes a sound source 102, an analog amplifier 104, an A/D converter 106, a DSP 108, a D/A converter 210, a volume circuit 220, a power amplifier 110, and an electroacoustic conversion element 112.
The sound source 102 is configured as a CD player, silicon audio player, cellular phone terminal, or the like, which outputs an analog audio signal. The analog amplifier 104 amplifies the analog audio signal received from the sound source 102 such that its output matches the input range of the A/D converter 106 configured as a downstream stage. The DSP 108 receives a digital audio signal from the A/D converter 106, and performs predetermined digital signal processing on the digital audio signal thus received. Examples of such signal processing performed by the DSP 108 include equalizing, bass boost, treble boost, monaural/stereophonic conversion, digital volume control, and the like.
The D/A converter 210 converts the digital audio signal, which has been subjected to signal processing by the DSP 108, into an analog audio signal. The volume circuit 220 amplifies the output signal of the D/A converter 210 with a gain that corresponds to a volume value. The power amplifier 110 amplifies the output of the volume circuit 220, so as to drive the electroacoustic conversion element 112 configured as a speaker or headphones.
With such an audio system 100, by inserting the volume circuit 220 as a downstream stage of the D/A converter 210, such an arrangement provides improved noise characteristics when the volume is reduced.
In the configuration shown in
The present invention has been made in order to solve such a problem. Accordingly, it is an exemplary purpose of an embodiment of the present invention to provide an audio circuit which is capable of suppressing the occurrence of DC shock noise.
An embodiment of the present invention relates to an audio circuit. The audio circuit comprises: a differential D/A converter that converts digital audio data into an analog differential audio signal; a differential to single-ended conversion circuit that converts the differential audio signal into a single-ended audio signal; a volume circuit that receives the single-ended audio signal, and amplifies the single-ended audio signal with a gain that corresponds to a volume value; a reference voltage source that generates a reference voltage commonly referred by the differential to single-ended conversion circuit and the volume circuit; and a calibration circuit that controls the differential D/A converter so as to shift at least one component of the differential audio signal such that a difference between an output voltage of the differential to single-ended conversion circuit and the reference voltage becomes zero.
In a case in which there is not an offset voltage in both the differential D/A converter and the differential to single-ended conversion circuit, the output voltage of the differential to single-ended conversion circuit matches the reference voltage. Conversely, in a case in which there is an offset in either the differential D/A converter or the differential to single-ended conversion circuit, the output voltage of the differential to single-ended conversion circuit deviates from the reference voltage. Directing attention to this mechanism, the reference voltage and the output of the differential to single-ended conversion circuit are monitored, and a calibration operation is performed such that they match each other, thereby canceling out the effects of the offset voltage. By canceling out the offset voltage, such an arrangement is capable of reducing DC shock noise that can occur when the audio circuit is started up or when the volume is switched.
Also, the calibration circuit may comprise: a first voltage comparator that compares the output voltage of the differential to single-ended conversion circuit with the reference voltage, and that generates a first comparison signal that indicates a comparison result; an offset adjuster that controls the differential D/A converter so as to shift at least one component of the differential audio signal; and a logic circuit that changes an offset amount to be applied from the offset adjuster, while monitoring the first comparison signal.
Also, the calibration circuit may operate after a predetermined time period elapses after the audio circuit is started up.
This allows the calibration to be performed after the voltage applied to the internal circuit becomes the same level as that in the normal operation.
Also, the reference voltage source may comprise: a first resistor and a second resistor arranged in series between a power supply line and a ground line; a capacitor connected to a connection node that connects the first resistor and the second resistor; and a voltage follower that receives a voltage at the connection node, and that outputs the reference voltage.
Also, the calibration circuit may further comprise: a threshold voltage source that generates a predetermined threshold voltage; and a second voltage comparator that compares the reference voltage with the threshold voltage, and asserts a second comparison signal when the reference voltage exceeds the threshold voltage. Also, when the second comparison signal is asserted, the logic circuit may start the calibration operation.
This allows the calibration to be performed after the reference voltage becomes the same level as that in the normal operation.
Also, a common comparator may be employed as both the first voltage comparator and the second voltage comparator. This allows the circuit area to be reduced.
Also, the differential D/A converter may be configured as a current segment D/A converter. Also, the offset adjuster may comprise a correction current segment group connected such that an output thereof is connected to an output of a current segment group of the differential D/A converter so as to form a common output. Also, the logic circuit may control an on/off operation of each of multiple current sources included in the correction current segment group.
Such an arrangement is capable of applying an offset to the output of the differential D/A converter.
Also, the differential D/A converter may be configured as a switched capacitor filter D/A converter.
Also, the audio circuit may be monolithically integrated on a single semiconductor substrate.
Examples of such a “monolithically integrated” arrangement include: an arrangement in which all the circuit components are formed on a semiconductor substrate; and an arrangement in which principal circuit components are monolithically integrated. Also, a part of the circuit components such as resistors and capacitors may be arranged in the form of components external to such a semiconductor substrate in order to adjust the circuit constants.
Another embodiment of the present invention relates to an in-vehicle audio apparatus. The in-vehicle audio apparatus comprises any one of the aforementioned audio circuits.
Yet another embodiment of the present invention relates to an audio component apparatus. The audio component apparatus comprises any one of the aforementioned audio circuits.
Yet another embodiment of the present invention relates to an electronic device. The electronic device comprises any one of the aforementioned audio circuits.
It is to be noted that any arbitrary combination or rearrangement of the above-described structural components and so forth is effective as and encompassed by the present embodiments.
Moreover, this summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.
Embodiments will now be described, by way of example only, with reference to the accompanying drawings which are meant to be exemplary, not limiting, and wherein like elements are numbered alike in several Figures, in which:
The invention will now be described based on preferred embodiments which do not intend to limit the scope of the present invention but exemplify the invention. All of the features and the combinations thereof described in the embodiment are not necessarily essential to the invention.
In the present specification, the state represented by the phrase “the member A is connected to the member B” includes a state in which the member A is indirectly connected to the member B via another member that does not affect the electric connection therebetween, in addition to a state in which the member A is physically and directly connected to the member B.
Similarly, the state represented by the phrase “the member C is provided between the member A and the member B” includes a state in which the member A is indirectly connected to the member C, or the member B is indirectly connected to the member C via another member that does not affect the electric connection therebetween, in addition to a state in which the member A is directly connected to the member C, or the member B is directly connected to the member C.
The audio circuit 200 includes a differential D/A converter (which will simply be referred to as the “D/A converter” hereafter) 210, a differential to single-ended conversion circuit 230, a volume circuit 220, a reference voltage source 240, and a calibration circuit 250.
The D/A converter 210 receives digital audio data DIN from an unshown DSP 108 configured as an upstream stage, and converts the digital audio data DIN into analog differential audio signals VP and VN.
The differential to single-ended conversion circuit 230 converts the differential audio signals VP and VN into a single-ended audio signal VSE. The differential to single-ended conversion circuit 230 includes an operational amplifier 232 and resistors R11 through R14. It should be noted that the configuration of the differential to single-ended conversion circuit 230 is not restricted in particular. Furthermore, a reference voltage VREF is supplied to the differential to single-ended conversion circuit 230. The differential to single-ended conversion circuit 230 performs differential to single-ended conversion based on the reference voltage VREF.
The volume circuit 220 receives the single-ended audio signal VSE, and amplifies the single-ended audio signal VSE with a gain (attenuation ratio) that corresponds to the volume setting value. The output voltage VOUT of the volume circuit 220 is supplied to an unshown power amplifier via a capacitor C2. The volume circuit 220 is configured as a non-inverting variable amplifier including a variable attenuator 222 and a non-inverting amplifier (voltage follower) 224. The variable attenuator 222 includes a resistor ladder 228 and a multiplexer 229. The resistor ladder 228 includes multiple resistors connected in series between the output of the differential to single-ended conversion circuit 230 and a reference voltage line 226 to which the reference voltage VREF is supplied. A tap is drawn from each node that connects adjacent resistors of the multiple resistors. The multiplexer 229 selects one from among the multiple taps according to the volume setting value VOL. The non-inverting amplifier 224 receives an output voltage VATT of the variable attenuator 222, and outputs the voltage VOUT having the same electric potential.
The reference voltage source 240 generates the reference voltage VREF configured as a common reference voltage to be used by both the differential to single-ended conversion circuit 230 and the volume circuit 220. The reference voltage source 240 includes a first resistor R21, a second resistor R22, an operational amplifier 242, and an external capacitor C21. The first resistor R21 and the second resistor R22 are arranged in series between a power supply (VDD) line and a ground (GND) line. The capacitor C21 is connected to a connection node that connects the two resistors R21 and R22. The operational amplifier 242 is configured as a voltage follower, which outputs the voltage across the capacitor C21 as the reference voltage VREF.
In the calibration mode, the calibration circuit 250 controls the D/A converter 210 so as to shift at least one from among the differential audio signals VP and VN such that the difference between the reference voltage VREF and the output voltage VSE of the differential to single-ended conversion circuit 230 approaches zero. In the calibration mode, the input to the D/A converter 210 is fixed to zero. The calibration result, i.e., the shift amount, is stored in memory such as a register or the like. In the normal audio playback mode, the shift amount stored in the memory is fixedly used.
The calibration circuit 250 includes a voltage comparator 252, a logic circuit 254, and an offset adjuster 256.
The voltage comparator (first comparator) 252 compares the reference voltage VREF with the output voltage VSE of the differential to single-ended conversion circuit 230. The offset adjuster 256 controls the D/A converter 210 so as to shift at least one from among the differential audio signals VP and VN. With this circuit configuration, the offset adjuster 256 shifts the differential audio signals VP and VN toward the lower electric potential side.
In the present embodiment, the D/A converter 210 is configured as a current-segment D/A converter including a pair of current segment groups CS31 and CS32 designed according to the digital audio data (input code) DIN. Each current segment group is configured to allow each current segment to be independently turned on and off. Furthermore, the output of each current segment of each current segment group is connected to a common output. The current to be supplied by each current segment may be weighted in a binary manner. Also, the current to be supplied by each current segment may be set to the same value. Also, the current to be supplied by a part of the current segments may be weighted in a binary manner, and the current to be supplied by each of the other current segments may be set to the same value.
A decoder 212 controls the current segment group CS31 with a first polarity and controls the current segment group CS32 with a second polarity, according to a common input code DIN. Resistors R31 and R32 convert the differential currents generated by the pair of current segment groups CS31 and CS32 into the differential voltages VP and VN, respectively.
The offset adjuster 256 includes a pair of correction current segment groups CS41 and CS42. The output of the current segment group CS41 is connected to the output of the current segment group CS31 of the D/A converter 210 so as to form a common output. Furthermore, the output of the current segment group CS42 is connected to the output of the current segment group CS32 of the D/A converter 210 so as to form a common output. The current to be generated by multiple current sources included in each of the correction current segment groups CS41 and CS42 is preferably designed to have a value that is smaller than 1 LSB of the D/A converter 210.
The logic circuit 254 controls an on/off operation for each of the multiple current sources included in the correction current segment groups CS41 and CS42, thereby independently controlling the offset currents IOFSP and IOFSN. The differential voltages VP and VN are shifted according to the offset currents IOFSP and IOFSN. Specifically, when the offset current IOFSP is generated, the differential voltage VP is shifted toward the lower electric potential side by (R31×IOFSP). In this case, the output VSE of the differential to single-ended conversion circuit 230 is shifted toward the lower electric potential side. Conversely, when the offset current IOFSN is generated, the differential voltage VN is shifted toward the lower electric potential side by (R32×IOFSN). In this case, the output VSE of the differential to single-ended conversion circuit 230 is shifted toward the high electric potential side.
The logic circuit 254 monitors a first comparison signal SCMP1 configured as an output of the voltage comparator 252. Furthermore, the logic circuit 254 optimizes the offset amount, which is to be supplied from the offset adjuster 256 to the D/A converter 210, such that the output voltage VSE of the differential to single-ended conversion circuit 230 becomes substantially the same as the reference voltage VREF.
The method for adjusting the offset amount and the algorithm thereof are not restricted in particular. For example, the voltage comparator 252 may be configured as a window comparator. With such an arrangement, a pair of reference voltages VREFH and VREFL may be set in the vicinity of the reference voltage VREF. Also, the offset amount may be optimized such that the voltage VSE is positioned within a range between the pair of reference voltages VREFH and VREFL. With such an arrangement, the logic circuit 254 may scan the offset amount, i.e., the output current IOFS of either one of the current segment group CS41 or CS42, from an initial value (e.g., zero). Also, the logic circuit 254 may stop the offset scanning immediately after the relation VREFH<VSE<VREFL holds true.
Alternatively, the voltage comparator 252 may be configured as a single comparator. With such an arrangement, the offset amount supplied from the offset adjuster 256 may be incremented (or otherwise decremented) from zero in a stepwise manner. Also, such an arrangement may detect a point at which the first comparison signal SCMP1 changes.
The calibration circuit 250 preferably operates after a predetermined period of time TTIMER elapses after the audio circuit 200 starts up. In order to meet such a requirement, the logic circuit 254 includes a digital timer circuit (clock counter) as a built-in component. Alternatively, an analog timer circuit is provided as an external component.
The calibration circuit 250 further includes a threshold voltage source 258 and a selector 260. The threshold voltage source 258 includes resistors R41 and R42, which divide the power supply voltage VDD so as to generate a predetermined threshold voltage VTH. The selector 260 receives the output voltage VSE of the differential to single-ended conversion circuit 230 and the threshold voltage VTH, and selects one from among the output voltage VSE and the threshold voltage VTH thus received, according to an instruction from the logic circuit 254. Before the calibration operation after the audio circuit 200 starts up, the logic circuit 254 sets a control signal S1 to a first level (e.g., low level) so as to instruct the selector 260 to select the threshold voltage VTH. In the calibration operation, the logic circuit 254 sets the control signal S1 to a second level (e.g., high level) so as to instruct the selector 260 to select the voltage VSE.
The threshold voltage VTH is set to be slightly lower than the reference voltage VREF that develops in the steady state. Accordingly, the voltage dividing ratio provided by the resistors R41 and R42 may preferably be designed to be slightly lower than the voltage dividing ratio provided by the resistors R21 and R22 of the reference voltage source 240 shown in
During a period in which the selector 260 selects the threshold voltage VTH, the voltage comparator 252 functions as a second comparator that compares the reference voltage VREF with the threshold voltage VTH. That is to say, in this state, when the reference voltage VREF exceeds the threshold voltage VTH, the voltage comparator 252 asserts a second comparison signal SCMP2. By making a combination of the voltage comparator 252 and the selector 260, such an arrangement allows the voltage comparator 252 to have two different comparator functions for different respective comparison targets.
When the second comparison signal SCMP2 is asserted, the logic circuit 254 instructs the selector 260 to select the voltage VSE, which starts the calibration operation.
The above is the configuration of the audio circuit 200. Next, description will be made regarding the operation of the audio circuit 200.
First, description will be made regarding the operation before the calibration operation.
At the time point t2, the power supply voltage VDD and the threshold voltage VTH reach their respective normal levels. On the other hand, the reference voltage VREF requires a longer time period to rise than that of the threshold voltage VTH due to the effect of the capacitor C21. When the reference voltage VREF reaches the threshold voltage VTH at the time point t3, the second comparison signal SCMP2 is asserted (set to the high level).
At the time point t1, an internal timer of the logic circuit 254 starts time measurement. At the time point t4 after a predetermined time period TTIMER elapses, a timer signal S2 is asserted. When both the second comparison signal SCMP2 and the timer signal S2 are asserted, the logic circuit 254 sets the control signal S1 to the high level, which switches the audio circuit 200 to the calibration operation mode.
The above is the configuration of the audio circuit 200. Next, description will be made regarding the operation thereof.
When the first comparison signal SCMP1 is switched to the high level, the logic circuit 254 holds the offset amount (shift amount) that has been set for the offset adjuster 256 in this stage, and the calibration operation ends.
After the completion of the calibration, such an arrangement enables a normal audio playback operation. In the audio playback operation, the D/A converter 210 is provided with an offset set in the calibration operation.
The above is the operation of the audio circuit 200. The audio circuit 200 has the following advantages.
By providing the D/A converter 210 with a correction offset, such an arrangement is capable of canceling out the effect of an offset voltage present in the D/A converter 210 or the differential to single-ended conversion circuit 230. By canceling out the offset voltage present in the D/A converter 210 or the differential to single-ended conversion circuit 230, such an arrangement is capable of reducing DC shock noise that can occur when the audio circuit 200 is started up or when the volume is switched.
Furthermore, after the predetermined time period TTIMER elapses and the reference voltage VREF exceeds the threshold voltage VTH after the audio circuit is started up, the calibration circuit 250 starts the calibration operation. This ensures that the calibration is performed after the reference voltage VREF is sufficiently stabilized, thereby providing the calibration with improved precision.
Description has been made above regarding the present invention with reference to the embodiment. The above-described embodiment has been described for exemplary purposes only, and is by no means intended to be interpreted restrictively. Rather, it can be readily conceived by those skilled in this art that various modifications may be made by making various combinations of the aforementioned components or processes, which are also encompassed in the technical scope of the present invention. Description will be made below regarding such modifications.
[First Modification]
The configuration of the volume circuit 220 is not restricted to such an arrangement shown in
[Second Modification]
The configuration of the D/A converter 210 is not restricted to such a current segment configuration. For example, the D/A converter 210 may have a switched capacitor filter configuration. Examples of conceivable methods for applying an offset to such a switched capacitor filter D/A converter include: a method in which the clock frequency is changed; a method in which multiple correction capacitor segments are added; and the like.
[Third Modification]
Description has been made in the embodiment regarding an arrangement in which the calibration operation is performed every time the power supply of the audio circuit 200 is turned on. Also, in a case in which the audio circuit 200 includes nonvolatile memory as a built-in component, the calibration operation may be performed with a reduced frequency. Also, the calibration may be performed only once before or after shipment.
[Usage]
Lastly, description will be made regarding the usage of the audio circuit 200.
The audio circuit 200 receives a digital input signal from a sound source 502 such as a CD player or the like. The digital input signal, which is output from the CD player, is directly input to a DSP 508. Furthermore, a stereo analog audio signal output from a tuner is input to TUNER channels. In addition, stereo analog audio signals, which can be output from other kinds of circuits such as a mobile audio player or the like, are input to AUX channels.
An input selector 503 selects the input channel, and an amplifier 504 converts a single-ended analog audio signal input to the selected channel into a differential signal. In a case in which an audio signal input to the selected channel is configured as a differential signal, the differential conversion processing is skipped.
An A/D converter 506R converts an input audio signal of the R channel configured as a differential signal into a digital audio signal. An A/D converter 506L converts an input audio signal of the L channel configured as a differential signal into a digital audio signal.
The DSP 508 includes a digital volume circuit, a 5-band equalizer, a loudness circuit, a crossover filter, and a bass booster circuit. The DSP 508 performs predetermined signal processing on the digital audio signals D1R and D1L.
A D/A converter 610R converts an R-channel digital audio signal D2R into a differential analog audio signal. A D/A converter 610L converts an L-channel digital audio signal D2L into a differential analog audio signal. A D/A converter 610M converts a digital audio signal D2M of the remaining channel into a differential analog audio signal. The D/A converters 610 correspond to a combination of the D/A converter 210 and the differential to single-ended conversion circuit 230 shown in
The application employing the audio circuit 200 shown in
While the preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-089557 | Apr 2015 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 6111529 | Maulik | Aug 2000 | A |
| 20070091207 | Aufranc | Apr 2007 | A1 |
| 20100329482 | Lee | Dec 2010 | A1 |
| 20130243223 | Sakai | Sep 2013 | A1 |
| Number | Date | Country |
|---|---|---|
| 2008278117 | Nov 2008 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20160316294 A1 | Oct 2016 | US |
