This disclosure relates generally to audio encoding and audio transmission methods, and more particularly to audio encoding methods and transmission methods for providing audio signals on the same carrier line as video signals.
Traditionally, analog audio and video signals have been transmitted over separate lines or cables. Additional cables may also be required where there is more than one discrete audio channel provided in a given audiovisual signal feed. For example, stereo audio provides for two discrete channels of audio and thus two audio signal lines are typically required to transmit the complete stereo audio signal. In other audio systems, such as those providing additional front, rear, center, or other channels, a separate line may also be required for each such additional channel in order to properly convey the full audio signal from one location to another.
In some instances, additional channel information may be extracted from standard stereo audio lines through special processing techniques such as the Pro Logic system from Dolby Laboratories of San Francisco, Calif. However, this system and those similar to it typically still require multiple lines or cables to provide the full audio signal and may not actually fully replicate each channel in a multi-channel signal. Additionally, these systems typically apply only to the audio portion of a complete audiovisual signal and are therefore not suitable for providing a single-line, multi-channel audio and video signal.
In other instances, multiple channels of analog audio may be frequency modulated (FM) and transmitted on the same line as a video signal. However, this method typically limits the quality of the audio signal. Additionally, problems can occur from the multiple analog audio and video signals propagating along the same medium such as cross talk between the audio signals and between the audio and video signals.
The present invention disclosed and claimed herein, in one aspect thereof, comprises a method of transmitting audio signals. The method includes receiving a multi-channel analog audio signal and converting the analog audio signal to a digital audio signal. The digital audio signal has a first sample bit length and a first sample rate. A header is provided for each discrete sample of the digital audio signal to produce a sample packet with a second sample bit length. The samples with headers are frequency shift key (FSK) encoded on first and second audio transmission frequencies and transmitted.
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying Drawings in which:
Referring now to the drawings, wherein like reference numbers are used herein to designate like elements throughout the various views, embodiments of the present invention are illustrated and described, and other possible embodiments of the present invention are described. The figures are not necessarily drawn to scale, and in some instances the drawings have been exaggerated and/or simplified in places for illustrative purposes only. One of ordinary skill in the art will appreciate the many possible applications and variations of the present invention based on the following examples of possible embodiments of the present invention.
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The digitized signal from the A/D converter 120 may be produced on output 122. The output 122 may provide a serial stream having both right and left audio signals included therein. In one embodiment, the output 122 is a standard I2S interface. The digitized audio signals are frequency shift key (“FSK”) encoded by FSK encoder 130. The frequency to which the digital audio signals are keyed may be chosen based upon the needs of the user. In one embodiment the 0's (zeros) of the digitized signals may be represented by a carrier of approximately 9 MHz and the 1's (ones) of the digitized signals may be represented by a carrier wave of approximately 12 MHz. Thus, the digital bits of the signals may be transmitted by a carrier signal alternating between 9 MHz (representing a 0 bit) and 12 MHz (representing a 1 bit). As with the A/D converter, the FSK encoder 130 may comprise commercially available components, such as an operational amplifier, an ASIC, an FPGA, software for a general processing system, or a combination thereof.
The FSK encoder 130, or another component of the audio encoder 100, may also function to add a preamble or header to each of the audio samples. In the present embodiment, an 8-bit header is attached to each of the 24-bit audio samples resulting in a 32-bit data packet for each audio sample. The header can be used to identify whether a given sample is a left or right audio-channel sample, to provide clock information, to provide error checking, or for other uses. Possible formats of the attached headers are described in greater detail below. With the attached headers, each of the 32-bit data packets may then be frequency shift keyed by the FSK encoder 130 as described, and transmitted on output 132. A band pass filter 140 may be provided and may be adapted to pass only the 9 MHz and 12 MHz frequency ranges to ensure a high quality digital output signal on output 142. In producing the FSK encoded output, the FSK encoder 130 utilizes a clock signal internal to the audio encoder 100. An output corresponding to this internal clock may be provided to accompany the output audio signal or the clock signal may be recovered on the receiving or decoding end as described below.
A video source 150 may also be provided to the summing junction 160 via signal path 152. The video source 150 may be connected via a standard Bayonet Neill Concelman (BNC) connector or another input suitable to the needs of the user. The video source may provide a video signal operating in a frequency range of up to 6 MHz. The video signal and the FSK audio signal may be combined at summing junction 160. The summing junction 160 may be a differential transmitter or other device capable of combining the audio and video signals. The summing junction 160 may comprise commercially available components, such as an operational amplifier, an ASIC, an FPGA, software for a general processing system, or a combination thereof. The combined signal consisting of the video signal and the audio signal, may be provided on output 162. The summing junction 160 may also provide additional amplification or signal conditioning as needed. In one embodiment, the output 162 may be an unshielded twisted pair (UTP) cable, although other physical carriers may also be suitable depending upon the needs of the user.
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The digitized audio samples, or packets, including the headers are FSK encoded at step 230. The output from the FSK encoding step may be a single bit stream of digital audio samples with the header information indicting to which audio channel the packet belongs. In one embodiment, the 0's of the bit stream correspond to a signal of approximately 9 MHz while the 1's of the stream correspond to signal of approximately 12 MHz. At step 240, a filter may be provided that removes noise from the signal that does not correspond substantially to one of the two carrier frequencies. A high quality signal may then be provided for combination with a video signal at step 250. Additional signal conditioning and/or amplification may also be performed at step 250 or at other steps. The signal may be transmitted at step 260 by placing the signal on a UTP cable for example. As previously stated, a clock signal may be transmitted with the signal, or the clock signal may be recovered from the signal itself as described below.
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An input 305 is provided for the decoder 300 for receiving an input signal such as that provided on the output 162 of the audio encoder 100 described above. As described, the signal may include video and multi-channel audio. A filter 310 removes the video portion of the signal. The filter 310 may be a high-pass filter or a band-pass filter. As described, in one embodiment, the video source provides a video signal operating in a frequency range of up to 6 MHz, while the digitized audio signals are FSK encoded and carried on 9 MHz and 12 MHz frequencies. Thus the filter 310 may be designed as a high pass or band pass filter that blocks the video frequency but passes the audio frequencies. The filtered signal is provided on output 312 and is provided to an FSK decoder 320.
The FSK decoder 320 receives the digital audio signal as a bit stream. The FSK decoder 320 examines each packet to determine on which audio channel the sample should be placed. In one embodiment, the FSK decoder 320 utilizes a state machine 340 to determine to which channel an audio sample belongs based on an examination of the attached header. The FSK decoder 320 may recover or synchronize with the clock signal from the bit stream itself, as described in greater detail below. In the present embodiment the FSK decoder 320 provides the digital audio samples on output 322, which may be an I2C interface. In one embodiment, the output digital audio sample comprise 24 bit samples at 48 KHz, corresponding to the audio sample output from the encoder 100 of
A second filter 340 is provided for removing the FSK audio signal of the input signal from the input 305. In the present embodiment, the audio signals on the input 305 are at 9 MHz and 12 MHz, while the video signal is up to about 6 MHz. Therefore, a low pass filter may be employed. The video output signal is provided on output 342, free of the audio signal. The output 342 may be a BNC connection or another suitable output.
In operation, as described in greater detail below, the audio decoder 300 receives a bit stream as an input. The bit stream may be without an accompanying clock signal. In such case, the audio decoder 300 may make adjustments for variations in the different clock signals being used by the audio encoder 100 and the decoder 300. A state machine 345 may be provided to locate a known bit pattern in the input bit stream. A high speed oscillator or counter 350 may also be provided and attached to or integrated with one or more of the other components of the audio decoder 300. In one embodiment, the state machine 345 and the high speed counter 350 may be implemented as a part of the FSK decoder 320. The frequency of the high speed counter 350 may vary according to the needs of the user but is generally high enough to have multiple counts per clock cycle of the audio signal bit stream. In one embodiment a 73 MHz counter may be employed.
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It will be appreciated by those skilled in the art having the benefit of this disclosure that this invention provides a broadband information appliance. It should be understood that The drawings and detailed description herein are to be regarded in an illustrative rather than a restrictive manner, and are not intended to limit The invention to The particular forms and examples disclosed. On The contrary, The invention includes any further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments apparent to those of ordinary skill in The art, without departing from The spirit and scope of this invention, as defined by The following claims. Thus, it is intended that he following claims be interpreted to embrace all such further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments.