The present invention relates to audio signal processing such as equalisation and spatial enhancement functions, and is particularly but not exclusively concerned with digital signal processing of digital audio signals.
Two common effects for improving the perceived quality of stereo audio are stereo enhancement and frequency-response equalisation.
Spatial or stereo enhancement effects work by cancelling crosstalk components that occur due to acoustic mixing of left and right signals between the loudspeaker and the ear. The result is to give an impression of increased stereo separation between channels.
Two circuits are commonly used for cancelling these crosstalk components.
In general, filter C is designed with a simple low-pass function to mimic the diffraction effect of the listener's head in path B, based on the assumption that path A has little filtering effect. Filter C may also be designed as a bandpass function to prevent cancellation of bass signals which are recorded equally in left and right channels.
A second known circuit is shown in
Although stereo enhancement filters (C or C′) are usually designed with a bandpass or lowpass function, the effect can be crude and produces an unnatural sounding stereo image. This is due to the gross approximation that the transfer function B/A is lowpass. More interesting or subtle effects can be produced by using a more flexible filter function. For example, it is useful to be able to modify these filters to compensate for differences in loudspeaker placement and the shape of the listener's head, so as to more closely match the response of function B/A. In practice this will be enabled by user controlled inputs to control the filter characteristics and/or the extent of the stereo enhancement effect (K).
Another common effect is Frequency Response Equalisation, which is used to modify the frequency characteristics of an audio signal to either compensate for the frequency response of the listening environment, or to adjust the sound to suit the listener's preference. Typically a graphic equaliser function is used provide boost or cut over a number of different audio frequency bands.
When implementing both a spatial enhancement effect and equalisation effects, three filters are required, one (CLR and CER) for each channel in the equaliser, and one in the spatial enhancer (C′). Typically these functional blocks are simply cascaded together, as illustrated by the additional filters CEL and CER shown in dashed outline in
In applications where implementation cost needs to be kept to an absolute minimum, the hardware cost of implementing these filters can be prohibitive. For portable battery-powered equipment (generally driving headphones, but similar features are still desirable), power consumption is also an important consideration. If the filters are implemented on an ALU (Arithmetic Logic Unit) core, the number of multiply cycles are at a premium, and so it is advantageous to minimise the number (or complexity) of the filters in order to avoid increasing the clock frequency of the ALU. Higher clock frequencies demand higher power consumption, and possibly a larger chip area, or at worst having to add an extra ALU to the system.
It is thus desirable to be able to provide both spatial enhancement and frequency response equalisation, but with reduced hardware cost and power consumption.
In general terms in one aspect the present invention provides an audio signal processing circuit arrangement for two audio channels, and which combines spatial enhancement or acoustic mixing (crosstalk) cancelling with equalisation functions. The circuit structure processes the sum and difference signals through separate filters and then recombines them to recover the separate channels (adding and subtracting respectively).
Such an arrangement provides a number of advantages including reduced hardware cost and complexity, which is especially important in low cost consumer electronics. This is achieved in an embodiment with a circuit structure having a reduced filter count compared with known cascaded circuits dedicated to each function. An additional advantage is the reduced power consumption of the arrangement due to the reduction of filter functions which are implemented as multiply and add operations on an arithmetic logic unit (ALU). Minimising the number of computations required in this way allows the clock frequency to be reduced and hence power consumption reduced. This is particularly important in portable devices such as personal MP3 players.
A further or alternative advantage is that the filter headroom requirements are reduced. This compares with simply cascading the spatial enhancement effect and equaliser. If a large L−R difference signal occurs, it becomes difficult to manage filter headroom requirements. This is because it is possible that the user will select a high gain for both blocks, causing premature signal overload at large transient overshoots or at frequencies where both filters have high gain, or even where the response of the first block shows peaks and the second is adjusted to give corresponding attenuation to avoid overload at the system output, still giving signal overload at the intermediate node. Such an overload can only be avoided by increasing the width of the digital word, again with penalties in hardware cost and power consumption. Conversely, the first filter may have a large dip in its response, which is then compensated for by a peaking in the second filter response, resulting in an amplification of the quantisation noise or numerical rounding errors from the first filter, which would require more bits at the LSB end of the digital word, to maintain a desired signal-to-noise ratio. This potential headroom problem is not an issue in the embodiments because there is no cascading of filters and so no need for the “last” filter(s) to be capable of handling an otherwise large input dynamic range.
In an embodiment the filtered sum and difference signals are added to the separate input signals in order to provide stereo enhancement and/or equalisation functions. With appropriate scaling of the filtered difference and sum signals and of the input signals, the mix of these two effects can be controlled by a user.
In particular in one aspect there is provided a signal processing circuit for audio signals according to claim 1.
There is also provided a method of processing audio signals according to claim 12.
Whilst the circuit and method are well suited to digital signal processing such as implementing cross-talk cancellation and equalisation functions in digital audio signals, they are also applicable to analogue implementation and analogue signal processing.
Embodiments will now be described with reference to the attached drawings, by way of example only and without intending to be limiting, in which:
a illustrates a circuit for cancelling acoustic crosstalk;
b illustrates another circuit for cancelling acoustic crosstalk;
Thus this “differential” equaliser EQ architecture processes the sum (L+R) and difference (L−R) signals separately.
If the filters C1 and C2 are identical (equal to CE say as described in relation to
Lo=C1(Li+Ri)/2+C2(Li−Ri)/2=CE(Li+Ri)/2+CE(Li−Ri)/2=CE.Li
Ro=C1(Li+Ri)/2−C2(Li−Ri)/2=CE(Li+Ri)/2−CE(Li−Ri)/2=CE.Ri
This is equivalent to processing the signals through the circuit of
If the filter characteristic C1 is equal to CE, and C2 is equal to the product of CE and (1+2.K.C′), when the outputs are recombined the overall result is the same as processing each channel separately through the circuit of
Again, since both main signal paths are scaled by KA, as KA is decreased to less than 0.5, both outputs scale accordingly, by a factor of KA/0.5, down to zero as KA approaches zero.
The combined crosstalk canceller and equaliser of
A second adder AL adds the processed difference signal from S2 (((1−K1)/2).C2.(Li−Ri)) to the processed sum signal from S1 (((1−K1)/2).C1.(Li+Ri)). A further signal path from the input signal Li to the second adder AL incorporates another scaling unit S3 having a gain of K1. The scaled input signal K1.Li is added to the processed sum and difference signals by the second adder AL to provide a left channel output signal Lo. A second subtractor AR subtracts the processed difference signal from S2 from the processed sum signal from S1. A further signal path from the input signal Ri to the second subtractor AR incorporates another scaling unit S4 having a gain of K1. The scaled input signal K1.Ri is added to the processed sum and difference signals by the second subtractor AR to provide a right channel output signal Ro.
A further scaling unit S5 is coupled between the output from the second filter C2 to both the second adder AL and the second subtractor AR, which in both cases add this scaled output to their other inputs to produce their respective left and right output signals Lo and Ro. The fifth scaling unit has a gain of K.K1, where K is a gain value equivalent to that of the scaling unit in
Thus, these combined functions (spatial enhancement and equalisation) can be performed using just two filter blocks C1 and C2, rather than the three of a typical cascade of these functional blocks. This reduces hardware cost and complexity. It also advantageously reduces power consumption by reducing the number of filter computations required to be performed by the ALU. This is highly desirable in portable devices such as MP3 players where battery life is an important issue.
As discussed above, additional signal paths are present in the circuit of
This architecture combines the variable aspect of the “3D” crosstalk cancelling effect of
In practice C1 can equal C2, enabling sharing of coefficients, and hence saving coefficient memory access and capacity.
As K1 is adjusted, the filter transfers functions C1 and C2 can be adjusted to create the proper 3D or EQ effects as described above with respect to
In practice a listener will generally prefer to avoid these extremes and choose some intermediate value of K1, giving a hybrid between the two effects. For values of K1 close to zero, the architecture behaves as an equaliser with some additional enhancement to the spatial properties of the sound due a degree of crosstalk cancellation. For values of K1 close to 1, the spatial effect is very pronounced, but the frequency response equalisation is more subtle.
Whilst not shown in the drawings, the skilled person will appreciate how to interface control signals for varying K1 and the filter functions C1 and C2 with a user interface in order to let a user control these effects. Also, whilst the embodiments have been described where C1=C2, it is equally possible that different equalisation functions could be applied to the left and right channels.
The transfer functions for the left and right paths (where C=C1=C2) are equivalent to those of
Lo=C(1−K1)(Li+Ri)/2+C.K3(Li−Ri)/2+K1.Li
Ro=C(1−K1)(Li+Ri)/2−C.K3(Li−Ri)/2+K1.Ri
Equivalently,
Lo=(C(1−K1)+K1)Li+C.K.K1(Li−Ri)
Ro=(C(1−K1)+K1)Ri−C.K.K1(Li−Ri)
When K1=0 (zero 3D effect), the overall transfer function reduces to that of the circuit of
When K1=1,
Lo=Li+C.K(Li−Ri)
Ro=Ri−C.K(Li−Ri)
so the architecture implements the stereo enhancement function of
The embodiments provide a number of advantages, for example they allow a more efficient implementation to be used (2 filters are used instead of 3), whilst allowing the user control over both Frequency Response Equalisation and Spatial Enhancement (or acoustic crosstalk cancellation). Additionally, the signal headroom requirements are easier to manage, avoiding the need for wider digital words and the extra hardware costs and power required to process them. This is because the problem of cascading two high gain stages (separate spatial enhancement and equalisation stages) together is avoided.
Whilst the embodiments have been described with respect to digital signal processing, it is equally possible to implement them in other technologies, for example as analogue circuits using op amps with similar advantages in terms of reduced circuit complexity, cost, and power and avoidance of overload or noise peaking under possible filter response selections.
The circuits of the embodiments may be implemented as integrated circuits or chips, and these may be incorporated into various items of audio equipment such as portable MP3 players, computer sound cards, games machines, audio visual equipment such as TV's, stand alone amplifiers or speakers, as well as other digitally based hi-fi sound equipment, digital still and video cameras.
The skilled person will recognise that the above-described apparatus and methods may be embodied as processor control code, for example on a carrier medium such as a disk, CD- or DVD-ROM, programmed memory such as read only memory (Firmware), or on a data carrier such as an optical or electrical signal carrier. For many applications embodiments of the invention will be implemented on a DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array). Thus the code may comprise conventional programme code or microcode or, for example code for setting up or controlling an ASIC or FPGA. The code may also comprise code for dynamically configuring re-configurable apparatus such as re-programmable logic gate arrays. Similarly the code may comprise code for a hardware description language such as Verilog™ or VHDL (Very high speed integrated circuit Hardware Description Language). As the skilled person will appreciate, the code may be distributed between a plurality of coupled components in communication with one another. Where appropriate, the embodiments may also be implemented using code running on a field-(re)programmable analogue array or similar device in order to configure analogue hardware.
The skilled person will also appreciate that the various embodiments and specific features described with respect to them could be freely combined with the other embodiments or their specifically described features in general accordance with the above teaching. The skilled person will also recognise that various alterations and modifications can be made to specific examples described without departing from the scope of the appended claims.
Number | Date | Country | Kind |
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0423097.5 | Oct 2004 | GB | national |