1. Field of the Invention
The invention relates to an audio/video signal processor, and more particularly to an audio/video signal processor with dual chips
2. Description of the Related Art
An audio/video playing device, such as a television or a computer, may display images and play sounds according to digital signals and analog signals received from an analog/digital tuner (or a hybrid tuner), and received from various interfaces such as a D-sub connector, a component input terminal, and a CVBS/S-Video input terminal. Thus, in the playing device, an audio/video signal processor for processing both digital and analog signals received from the analog/digital tuner (or a hybrid tuner), and received from various interfaces such as a D-sub connector, a component input terminal, and a CVBS/S-Video input terminal has to be fabricated by BGA (ball grid array) packaging for a large number of pins, however, which increases cost.
An exemplary embodiment of an audio/video signal processor comprises a first chip, a bus, and a second chip. The first chip receives at least one input signal with display and sound information through at least one I/O interface and converts the input signal to generate a converted signal. The bus is communicated with the first chip. The second chip receives the converted signal through the bus and processes the converted signal to generate a display and sound signal for displaying and playing. The first chip and the second chip are packaged by the same packaging manner with the second chip fabricated by a more advanced process than the first chip. In some embodiments, the packaging manner is quad flat package (QFP), and the second chip is fabricated by a 0.90 nm process, and the first chip is fabricated by a 0.18 um process.
In some embodiments, the second chip comprises a first processing module, a second processing module, a third processing module, and a memory. The first processing module processes the converted signal from the first chip to accordingly generate a processed video signal and a processed audio signal. The second processing module and the third processing module respectively process the processed audio signal and the processed video signal to generate a display and sound signal for displaying and playing. The memory is accessed by the first processing module and the third processing module.
In some embodiments, the first chip comprises a demodulating unit for receiving a digital signal to serve as the input signal and generating the converted signal to the second chip and a converting unit for receiving an analog input signal to serve as the input signal and generating the converted signal to the second chip. Further, the first chip comprises an interface controlling unit and a processing device, wherein the interface controlling unit controls the processing device to receives the converted signal from the demodulating unit through the bus, descramble and decrypt the converted signal from the demodulating unit, and transmits the converted signal which has been descrambled and decrypted signal to the second chip through the controlling unit.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
Audio/video signal processors are provided. In an exemplary embodiment of an audio/video signal processor in
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The chip 11 comprises processing modules 21 and 22 and an audio processing module 23. The processing module 21 comprises a video decoding unit 210a, a de-interlacing unit 210b, a video enhancement unit 210c, and a scaling unit 210d for processing video data of the converted signal from the chip 10. When the chip 11 receives the converted signal from the ADC unit 20b or the SIF-PIF ADC unit 20c, the video decoding unit 210a decodes the received converted signal and generates a video decoded signal. The de-interlacing unit 210b transforms an interlacing scan mode of the video decoded signal to a progressive scan mode, wherein the progressive scan mode is applied for a liquid crystal display (LCD) panel or a plasma display panel (PDP). The video enhancement unit 210c enhances the quality of images represented by the video decoded signals, for example, the video enhancement unit 210c reduces noise and enhances contrast of the images. The scaling unit 210d adjusts size or resolution of the images represented by the video decoded signal to display images on an external display panel according specification of the display panel or use's requirements. After the scan mode transformation, video enhancement, and size or resolution adjustment, the processing module 21 generates a display signal for the display panel. The audio processing module 23 also receives the converted signals from the ADC unit 20b or the SIF/PIF ADC unit 20c and demodulates/decodes audio data of the converted signals to generate audio decoded signals. The audio decoded signals are transmitted to an external speaker module.
When the chip 11 receives the converted signal from DTV modulating unit 20a or the HDMI receiving unit T24, the processing module 22 of the chip 11 processes video and audio data of the converted signal. The processing module 22 accordingly generates a processed video signal and transmits the processed video signal to the de-interlacing unit 210b, the video enhancement unit 210c, and the scaling unit 210d for adjusting quality of images represented by the processed video signal and changes feature values of the images represented by the processed video signal. The de-interlacing unit 210b transforms an interlacing scan mode of the processed video signal to a progressive scan mode. The video enhancement unit 210c enhances the quality of images represented by the processed video signal. The scaling unit 210d adjusts size or resolution of the images represented by the processed video signal to display images on the display panel according specification of the display panel or use's requirements. The processing module 22 generates a display signal for the display panel. The processing module 22 also generates a processed audio signal according to the received converted signals and transmits the processed audio signal to the audio processing module 23. The audio processing module 23 demodulates/decodes the processed audio signal to generate audio decoded signals, which are transmitted to the speaker module. In some embodiments, the processing module 22 comprises an MPEG-2 (Moving Picture Experts Group-2) decoding unit.
According to above disposition of the chips 10 and 11, the units for receiving/outputting signals from/to the I/O interfaces and the units for processing the video data and audio data are divided into the two chips 10 and 11. Thus, each of the chips 10 and 11 has a decreased number of pins. Both of the chips 10 and 11 can be packaged by a quad flat package (QFP) matter which has a lower cost. Moreover, since the processing modules 21 and 22 and the audio processing module 23 are arranged to process digital signal, the chip 11 can be fabricated by a smaller 90 nm process. The chip 10 is fabricated by 0.18 um process.
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When the audio/video signal processor 1 is applied in European television systems, the chip 10 further comprises a common interface (CI) controlling unit 30, as shown in
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In some embodiments, the audio/video signal processor 1 can operate in a fast access mode. When the audio/video signal processor 1 begins operating, the units of the chip 10 may require data previously stored in the memory M20 for initiation. At this time, the audio/video signal processor 1 enters a fast access mode to transmit the data from the memory M20 to the chip 10 in parallel.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.