Auto gain control circuit

Abstract

An auto gain control circuit comprises a first peak detector, a variable gain amplifier, a second peak detector, a multiplexer and a controller. The first peak detector detects peaks of an input signal to generate a first peak signal. The variable gain amplifier amplifies the input signal to generate an output signal according to a control signal. The second peak detector detects peaks of the output signal to generate a second peak signal. The multiplexer selectively outputs the first peak signal or the second peak signal according to a first control signal. The controller generates the control signal according to the second peak signal and the first peak signal or according to the second peak signal and the reference voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 illustrates a conventional auto gain control circuit with zero decibel gain;

FIG. 2 shows an auto gain control circuit according to an embodiment of the invention;

FIG. 3 shows a variable gain amplifier according to an embodiment of the invention; and

FIG. 4 shows a variable gain amplifier according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 shows auto gain control circuit 200 according to an embodiment of the invention. Auto gain control circuit 200 comprises first peak detector 210, variable gain amplifier 220, second peak detector 240, multiplexer 250 and controller 260. First peak detector 210 receives input signal S₂₁ from input terminal Input and detects peaks of input signal S₂₁ to generate first peak signal S₂₃. Variable gain amplifier 220 receives input signal S₂₁ and adjusts its gain to amplify input signal S₂₁ to generate output signal S₂₂ to output terminal Output according to control signal S₂₆.

In an embodiment of the invention, variable gain amplifier 220 may amplify or attenuate input signal S₂₁. For example, the range of the gain of variable gain amplifier 220 is −10 dB˜+10 dB. In another embodiment of the invention, variable gain amplifier 220 further comprises a plurality of attenuators (d₁, d₂ . . . d_n) and a plurality of variable gain amplifiers (A₁, A₂ . . . A_n) coupled in serial, as shown in FIG. 3. Attenuators (d₁, d₂ . . . d_n) may be voltage dividers. Second peak detector 240 is coupled to variable gain amplifier 220 to receive output signal S₂₂ and detects peaks of output signal S₂₂ to generate second peak signal S₂₄. Multiplexer 250 is coupled to first peak detector 210 to receive first peak signal S₂₃ and reference voltage V_ref. Multiplexer 250 selectively outputs first peak signal S₂₃ or reference voltage V_ref according to control signal S₃. Controller 260 is coupled to variable gain amplifier 220, second peak detector 240 and multiplexer 250. Controller 260 generates control signal S₂₆ according to second peak signal S₂₄ and one of first peak signal S₂₃ and reference voltage V_ref from multiplexer 250. Controller 260 further comprises comparator 264 and integrator 262. Comparator 264 compares second peak signal S₂₄ and one of first peak signal S₂₃ and reference voltage V_ref from multiplexer 250 to generate comparative signal S₂₅. Integrator 262 is coupled to comparator 264 and generates control signal S₂₆ according to comparative signal S₂₅.

According to an embodiment of the invention, integrator 262 comprises at least one capacitor. Integrator 262 accumulates charges of comparative signal S₂₅ to generate corresponding control signal S₂₆. For example, if multiplexer 250 selects to output first peak signal S₂₃, after a period, auto gain control circuit 200 will stay locked. The gain of variable gain amplifier 220 will stabilize at 0 dB. Input signal S₂₁ is thus equal to output signal S₂₂. If multiplexer 250 selects to output reference voltage V_ref, auto gain control circuit 200 generates comparative signal S₂₅ by using comparator 264 to compare second peak signal S₂₄ and reference voltage V_ref. When second peak signal S₂₄ exceeds reference voltage V_ref, comparator 264 outputs comparative signal S₂₅ to decrease charges of integrator 262 for decreasing a voltage level of control signal S₂₆. Similarly, when second peak signal S₂₄ is lower than reference voltage V_ref, comparator 264 outputs comparative signal S₂₅ to increase charges of integrator 262 for increasing the voltage level of control signal S₂₆. Auto gain control circuit 200 uses control signal S₂₆ to control variable gain amplifier 220 to adjust output range of output signal S₂₂. Since integrator 262 comprises capacitors, output signal S₂₂ will be gradually adjusted. Output signal S₂₂ will not change sharply, avoiding saturation or abnormality of subsequent stage circuits. In addition, input signal S₂₁ may be an audio signal with frequency range 400˜30 KHz.

FIG. 4 shows variable gain amplifier 400 according to an embodiment of the invention. Variable gain amplifier 400 comprises resistor 410, first transistor Q1, second transistor Q2, third transistor Q3 and fourth transistor Q4. Resistor 410 is coupled between first voltage source Vcc and output terminal Output. First transistor Q1 comprises a drain coupled to resistor 410, a gate coupled to input terminal Input and a source. Second transistor Q2 comprises a drain coupled to the source of first transistor Q1, a gate coupled to the source of first transistor Q1 and a source. Third transistor Q3 comprises a drain coupled to the source of second transistor Q2, a gate receiving control signal S₂₆ and a source coupled to second voltage source Vss. Fourth transistor Q4 comprises a drain coupled to the source of first transistor Q1, a gate receiving control signal S₂₆ and a source coupled to second voltage source Vss. In addition, first transistor Q1, second transistor Q2, third transistor Q3 and fourth transistor Q4 are all NMOS (Negative-Channel Metal Oxide Semiconductor) transistors.

While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims

1. An auto gain control circuit, comprising: a first peak detector receiving an input signal and detecting peaks of the input signal to generate a first peak signal;a variable gain amplifier receiving the input signal and adjusting a gain of the variable gain amplifier to amplify the input signal to generate an output signal according to a control signal;a second peak detector coupled to the variable gain amplifier to receive the output signal and detecting peaks of the output signal to generate a second peak signal;a multiplexer coupled to the first peak detector to receive the first peak signal, receiving a reference voltage and selectively outputting the first peak signal or the reference voltage according to a first control signal; anda controller coupled to the variable gain amplifier, the second peak detector and the multiplexer and generating the control signal according to the second peak signal and one of the first peak signal and the reference voltage from the multiplexer.

2. The auto gain control circuit as claimed in claim 1, wherein the controller further comprises: a comparator coupled to the second peak detector and the multiplexer and generating a comparative signal by comparing the second peak signal and one of the first peak signal and the reference voltage from the multiplexer; andan integrator coupled to the comparator and the variable gain amplifier to generate the control signal according to the comparative signal.

3. The auto gain control circuit as claimed in claim 1, wherein the gain of the variable gain amplifier is between −10 dB and +10 dB.

4. The auto gain control circuit as claimed in claim 1, wherein the variable gain amplifier further comprises an attenuator and a first variable gain amplifier.

5. The auto gain control circuit as claimed in claim 4, wherein the attenuator is coupled to the first variable gain amplifier in serial.

6. The auto gain control circuit as claimed in claim 4, wherein the attenuator is a voltage divider.

7. The auto gain control circuit as claimed in claim 1, wherein the variable gain amplifier comprises a plurality of second variable gain amplifiers.

8. The auto gain control circuit as claimed in claim 1, wherein the input signal is an audio signal.

9. The auto gain control circuit as claimed in claim 1, wherein a frequency range of the input signal is 400˜30 KHz.

10. The auto gain control circuit as claimed in claim 1, the variable gain amplifier comprising: a resistor coupled to a first voltage source;a first transistor having a first terminal coupled to the resistor, a second terminal receiving the input signal and a third terminal;a second transistor having a fourth terminal coupled to the third terminal of the first transistor, a fifth terminal coupled to the third terminal of the first transistor and a sixth terminal;a third transistor having a seventh terminal coupled to the sixth terminal of the second transistor, an eighth terminal receiving the control signal and a ninth terminal coupled a second voltage source; anda fourth transistor having a tenth terminal coupled to the third terminal of the first transistor, an eleventh terminal receiving the control signal and a twelfth terminal coupled to the second voltage source.

11. The auto gain control circuit as claimed in claim 1, wherein the first transistor, the second transistor, the third transistor and the fourth transistor are NMOS transistors.

12. An auto gain control circuit, comprising: a first peak detector receiving an input signal and detecting peaks of the input signal to generate a first peak signal;a variable gain amplifier receiving the input signal and adjusting a gain of the variable gain amplifier to amplify the input signal to generate an output signal according to a control signal, comprising: a resistor coupled to a first voltage source;a first transistor having a first terminal coupled to the resistor, a second terminal receiving the input signal and a third terminal;a second transistor having a fourth terminal coupled to the third terminal of the first transistor, a fifth terminal coupled to the third terminal of the first transistor and a sixth terminal;a third transistor having a seventh terminal coupled to the sixth terminal of the second transistor, an eighth terminal receiving the control signal and a ninth terminal coupled to a second voltage source; anda fourth transistor having a tenth terminal coupled to the third terminal of the first transistor, an eleventh terminal receiving the control signal and a twelfth terminal coupled to the second voltage source;a second peak detector coupled to the variable gain amplifier to receive the output signal and detecting peaks of the output signal to generate a second peak signal;a multiplexer coupled to the first peak detector to receive the first peak signal, receiving a reference voltage and selectively outputting the first peak signal or the reference voltage according to a first control signal;a comparator coupled to the second peak detector and the multiplexer and generating a comparative signal by comparing the second peak signal and one of the first peak signal and the reference voltage from the multiplexer; andan integrator coupled to the comparator and the variable gain amplifier to generate the control signal according to the comparative signal.

13. The auto gain control circuit as claimed in claim 12, wherein the integrator comprises at least one capacitor.

14. The auto gain control circuit as claimed in claim 12, wherein the input signal is an audio signal.

15. The auto gain control circuit as claimed in claim 12, wherein a frequency range of the input signal is 400˜30 KHz.

16. The auto gain control circuit as claimed in claim 12, wherein the variable gain amplifier comprises a plurality of second variable gain amplifiers.

17. The auto gain control circuit as claimed in claim 12, the first transistor, the second transistor, the third transistor and the fourth transistor are NMOS transistors.