BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
Other objects, features and advantages will occur to those skilled in the art from the following description of a preferred embodiment and the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a prior art substrate bandgap reference circuit;
FIG. 2A illustrates PTAT, CTAT, (complementary to absolute temperature) and PTAT plus CTAT (VBG) characteristics of the circuit of FIG. 1;
FIG. 2B illustrates the noise power spectral density;
FIG. 3 is a schematic diagram of an auto-nulling substrate bandgap reference system according to this invention;
FIG. 4 is a schematic diagram of a portion of the auto-nulling substrate bandgap reference system of FIG. 3 instead using multiple diode connected bipolar junction transistors to implement a multiple (or “stacked”) bandgap reference.
FIG. 5 is a schematic diagram of another embodiment of the auto-nulling substrate bandgap reference system of this invention with the strobe circuit of this invention;
FIG. 6 is a schematic diagram of another embodiment of the strobe circuit of this invention; and
FIG. 7 illustrates the waveforms of the compensation voltage, start up signal and strobe signal generated by the strobe circuit and substrate bandgap reference system of this invention.
DETAILED DESCRIPTION OF THE INVENTION
Aside from the preferred embodiment or embodiments disclosed below, this invention is capable of other embodiments and of being practiced or being carried out in various ways. Thus, it is to be understood that the invention is not limited in its application to the details of construction and the arrangements of components set forth in the following description or illustrated in the drawings. If only one embodiment is described herein, the claims hereof are not to be limited to that embodiment. Moreover, the claims hereof are not to be read restrictively unless there is clear and convincing evidence manifesting a certain exclusion, restriction, or disclaimer.
There is shown in FIG. 1 a basic substrate bandgap reference circuit 10 contained on the single MOS chip 12 including an amplifier 14 and a substrate PTAT bandgap core 16 which has a differential output 18, 20 to the differential input 22, 24 of amplifier 14. Amplifier 14 operates with a feedback circuit 15 which responds to the output of amplifier 14 to drive to zero the differential output 18, 20 at inputs 22 and 24. The inherent offset and noise errors associated with such amplifiers is a problem. Bandgap core 16 includes a pair of bandgap reference diodes 26 and 28 which may be diodes but are typically diode connected substrate bipolar junction transistors. Bandgap core 16 also includes three resistors R1 30, R2 32, and R3 34. In this circuit a differential base emitter voltage (ΔVBE) is developed by running different current densities into two bipolar devices 26 and 28. The same ΔVBE can be achieved by using differently sized bipolar devices or a combination of these effects. The resulting differential voltage is used to develop a proportional to absolute temperature (PTAT) current that in turn is used to generate larger PTAT voltages. The circuit is configured so that the base emitter voltage with the substrate bipolar known to be complementary to absolute temperature (CTAT) is added to the generated PTAT voltage so that the resulting reference output voltage shows little variation over temperature. This is standard architecture and well known to those skilled in the art. In MOS process the largest contribution offset and low frequency noise in such a reference circuit results from the MOS devices used in the amplifier that provide the large loop gain necessary in this circuit. In accordance with this invention those noise sources are removed or reduced.
The characteristic PTAT 40 and CTAT 42 voltages, FIG. 2A, combine to form a virtually temperature insensitive voltage VBG. The nulling technique of this invention which removes offset in the amplifier has the same effect on low frequency noise as it has on offset voltages in that it removes or greatly reduces the noise that occurs at frequencies well below the frequency at which the auxiliary amplifier is switched in and out of the main loop. As low frequency (1/f) noise becomes more and more significant and as process geometries are reduced this becomes more and more important. This is shown in FIG. 2B, where the thermal noise 46 and 1/f noise 48 are shown in a plot of log of noise power versus log of the frequency.
The auto-nulled bandgap reference system 50 according to this invention is shown in FIG. 3, where similar parts have been given similar numbers accompanied by a lower case letter. Auto-nulled bandgap reference system 50 is located on a single chip 12a along with a basic substrate bandgap reference circuit 10a, but there is added in this invention a second auxiliary amplifier 52 in addition to the first primary amplifier 14a. Also included are storage devices such as capacitors 54 and 56 and a switching circuit 58 which includes switches 60, and 62, which are closed in a first mode φ1 and two switches 64 and 66 which are closed during a second mode φ2. The switches are operated on a break before make basis so that at no time will switches 60 and 62 be on at the same time as switches 64 and 66. Switches 60, 62, 64, and 66 are operated by nulling control circuit 68 which provides at its output the φ1 signal in the first mode, and φ2 signal in the second mode. Nulling control circuit 68 may be commanded to alternate between the two modes either at a fixed frequency 70 or at a hopping frequency 72 or using a pseudo random or spread spectrum approach 74. The nulling frequency therefore may be moved during operation depending on where noise will cause problems in the application. In some applications it may not be practical or possible to find a safe frequency range for the auto nulling frequency to be set in order to avoid a potential frequency bands of interest. In those cases the auto nulling can be spread spectrum to avoid placing too much unwanted frequency content in a given band.
In operation, in a first mode switches 60 and 62 are closed. Switch 62 shorts together the inputs to auxiliary amplifier 52. With switch 60 also closed a secondary feedback loop 76 is created so that the output of auxiliary amplifier 52 is fed back on the nulling input 78 of auxiliary amplifier 52 to develop a voltage sufficient to cancel any offset voltage at or imbalance between its inputs. This voltage will be stored on storage device or capacitor 56. Switches 60 and 62 are now open preserving that voltage at least for a finite period of time during which auxiliary amplifier 52 operates as a “perfect” amplifier with the offset and low frequency noise at its input reduced to zero, or nearly so. Then in the second mode switches 64 and 66 which have been opened during the first mode are closed. With the closing of switch 66 the inputs to auxiliary amplifier 52 are connected in parallel with the inputs of primary amplifier 14a. And the output of auxiliary 52 is delivered to the nulling input 80 of primary amplifier 14a. Auxiliary amplifier 52 now perfectly senses the offset and low frequency noise errors at the input of primary amplifier 14a and through feedback loop 82 and closed switch 64 develops a voltage at nulling input 80 which compensates for the offset and low noise error at the input of amplifier 14a. Primary amplifier 14a now operates as a virtually perfect amplifier as did auxiliary amplifier 52. Initially, the auxiliary amplifier 52 is nulling itself and the main amplifier 14a controls the loop with its offset set as a function of its inherent offset plus the effect of the voltage stored at its nulling input. Once this phase is complete, the switch connected to the nulling cap input of the auxiliary amplifier 52 is first opened, followed by the switch shorting its inputs together. Next, the switch connecting the inputs of the auxiliary amplifier 52 to the inputs of the main amplifier 14a is shorted followed by connecting the output of the auxiliary amplifier 52 to the nulling input of the main amplifier 14a. When this clock phase is completed, the connection from the output of the auxiliary amplifier 52 to the nulling input of the main amplifier 14a is first disconnected followed by the connection of the auxiliary amplifier 52 inputs to the inputs of the main amplifier 14a. To complete the cycle, the inputs of the auxiliary amplifier 52 are first shorted followed by the connection of the output of the auxiliary amplifier 52 to the auxiliary inputs of the main amplifier 14a. And thus, the cycle continues.
While in FIG. 3 the bandgap references are shown as the single pair of diodes or diode connected transistors 26a and 28a, commonly referred to as a “single bandgap,” this is not a necessary limitation of the invention. For example as shown in FIG. 4, each leg may include two or more such diode devices, e.g. 26a1, 26a2 . . . 26an: 28a1, 28a2 . . . 28an, in order to implement a multiple or (“stacked”) bandgap reference.
In another embodiment, FIG. 5, primary amplifier 14b and auxiliary amplifier 52b each have differential nulling inputs 80b, 80bb, 78b, 78bb, respectively, so there are two storage devices capacitors 54b, 54bb and capacitors 56b and 56bb and the switches are both double pole switches 64b and 60b.
A strobe circuit 98 according to this invention is also shown in FIG. 5. Strobe circuit 98 includes output storage device 104, refresh switch 102, and strobe control circuit 100. Strobe control circuit 100 provides a periodic strobe signal which closes switch 102 to periodically charge output storage device, capacitor 104, and simultaneously enable the primary 14b and auxiliary 52b amplifiers which are otherwise disabled in order to conserve power. This is done at a predetermined rate in accordance with the particular application. Since the charge leakage from output storage capacitor 104 is effected by temperature, a temperature sensor circuit 108 may be used to change the rate at which strobe control circuit refreshes storage capacitor 104 in accordance with the temperature sensed. When strobe control circuit 100 powers up amplifiers 14b and 52b, it also enables nulling control circuit 68 to begin its auto nulling operation. Also shown in FIG. 5 is start up circuit 110 which includes a comparator 112 and a timer 114. Comparator 112 senses the voltage on output terminal 114 and as it rises provides an output signal when it reaches a reference voltage Vx. This operates timer 114 so that after a predetermined period of time when the voltage has stabilized a signal is sent on line 116 to enable strobe control circuit 100.
Strobe control circuit 98c is shown more generally in FIG. 6 as including only strobe control circuit 100c and output storage device capacitor 104c as switch 102c may not always be necessary. The strobe signal on line 122 could simply enable or disable an associated bandgap reference circuit 120 such as auto-nulled bandgap reference system 50, FIG. 3, or 50b, FIG. 5, so that it provides output or no output to capacitor 104c without the supervision of a switch such as switch 102c. If there no switch it may simply have a high impedance output when disabled to allow the output capacitor 104c to float.
The average current is substantially reduced by the strobe circuit operation whereby the bandgap reference is powered up periodically to refresh the voltage on the output capacitor and after a short period of refresh the bandgap reference is then completely powered down to save current. When it is powered down and it presents a high impedance output (or if a switch is opened) the output capacitor is then allowed to float and this process repeats cyclically at a predetermined rate.
In operation, at startup referring to FIG. 7 and 5 the compensation voltage 130, FIG. 7, rises until it reaches the reference voltage Vx of comparator 112, FIG. 5. This triggers an output from comparator 112 at 132 which operates timer 114 for a period of time until it reaches time 134. At that point it provides an enable signal 136 to the strobe circuit which then begins refreshing output capacitor 104 and, alternately, powering up to refresh output capacitor 104 and powering down to conserve power. Strobe signals repeat periodically as shown at 138 in dependence upon how quickly the charge on output capacitor 104 depletes as indicated by the saw tooth shape 140 of the compensation voltage 130. It is during each of these strobe periods 138 that the nulling control circuit provides the auto-nulling operation using switching circuits 58, 58b. Note that if the strobing is used in conjunction with the auto nulling the refresh period should be over several cycles of the auto nulling period to get the benefits from auto nulling.
Although specific features of the invention are shown in some drawings and not in others, this is for convenience only as each feature may be combined with any or all of the other features in accordance with the invention. The words “including”, “comprising”, “having”, and “with” as used herein are to be interpreted broadly and comprehensively and are not limited to any physical interconnection. Moreover, any embodiments disclosed in the subject application are not to be taken as the only possible embodiments.
In addition, any amendment presented during the prosecution of the patent application for this patent is not a disclaimer of any claim element presented in the application as filed: those skilled in the art cannot reasonably be expected to draft a claim that would literally encompass all possible equivalents, many equivalents will be unforeseeable at the time of the amendment and are beyond a fair interpretation of what is to be surrendered (if anything), the rationale underlying the amendment may bear no more than a tangential relation to many equivalents, and/or there are many other reasons the applicant can not be expected to describe certain insubstantial substitutes for any claim element amended.
Other embodiments will occur to those skilled in the art and are within the following claims.
Patent Application
20080079413
