Patent Application
20220206955
This disclosure relates to efficient set rebalancing in a translation lookaside buffer (TLB) that contains a configurable sub-TLB that is configurable to hold different page size sets at different times after boot and a fixed sub-TLB that holds a fixed page size set after boot.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present techniques, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be noted that these statements are to be read in this light, and not as admissions of any kind.
Integrated circuits are found in numerous electronic devices, from handheld devices, computers, gaming systems, robotic devices, automobiles, and more. Some integrated circuits, such as microprocessors, process data retrieved from memory. While the data is stored in a physical memory address representing an actual location in the memory, software running on the integrated circuit may operate using a virtual memory address that is translated to the physical memory address when the memory is accessed. A structure on the integrated circuit known as a translation lookaside buffer (TLB) may reduce the time taken to access a memory location by storing recently used mappings of virtual memory addresses to their corresponding physical memory addresses. Virtual-to-physical translation is done using “pages,” where typical x86 page sizes are 4 kibibyte (4KiB), 2 mebibyte (2MiB), or 1 gibibyte (1GiB). The TLB entry for a page covers a range of addresses, corresponding to the page size. For example, if the TLB stores translation for a 2MiB page then there is a range of 2M virtual addresses which may be translated by the same TLB entry. When software running on the integrated circuit requests access to a particular virtual memory address that is on a page that was recently used and that is stored in the TLB, the TLB may rapidly translate the virtual memory address to its corresponding physical memory address.
In this way, the TLB may operate as a cache of mappings from virtual memory addresses to physical memory addresses. When a mapping is requested that is currently stored in the TLB, this may be referred to as a “cache hit” or “TLB hit.” When the TLB does not currently have the requested mapping, however, this may be referred to as a “cache miss” or “TLB miss.” The requested mapping may first be loaded into the TLB before translation occurs. Some software applications may lose significant running time to TLB misses.
One way to reduce TLB misses involves increasing the size of the TLB. Many software applications may touch many pages of memory with poor reference locality, however, making it infeasible to build a “never miss” TLB. Further, a larger hardware structure may have a higher hit rate but slower access time, leading to a net loss of performance. Other ways to reduce miss rates may involve using TLB entries of different page sizes. Unfortunately, the memory use cases that provide performance advantages with this structure may be difficult to realize. Moreover, solutions such as sharing a single sub-TLB of a particular size often introduces non-trivial conflicts or competition that may introduce additional latency due to TLB misses.
Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings in which:
One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements. The terms “including” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “some embodiments,” “embodiments,” “one embodiment,” or “an embodiment” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. Furthermore, the phrase A “based on” B is intended to mean that A is at least partially based on B. Moreover, the term “or” is intended to be inclusive (e.g., logical OR) and not exclusive (e.g., logical XOR). In other words, the phrase A “or” B is intended to mean A, B, or both A and B. Moreover, this disclosure describes various data structures, such as instructions for an instruction set architecture. These are described as having certain domains (e.g., fields) and corresponding numbers of bits. However, it should be understood that these domains and sizes in bits are meant as examples and are not intended to be exclusive. Indeed, the data structures (e.g., instructions) of this disclosure may take any suitable form.
As noted above, integrated circuits are found in numerous electronic devices, from handheld devices, computers, gaming systems, robotic devices, automobiles, and more. Some integrated circuits, such as microprocessors, process data retrieved from memory. While the data is stored in a physical memory address representing an actual location in the memory, software running on the integrated circuit may operate using a virtual memory address that is translated to the physical memory address when the memory is accessed. A structure on the integrated circuit known as a translation lookaside buffer (TLB) may reduce the time taken to access a memory location by storing recently used mappings of virtual memory addresses to their corresponding physical memory addresses. Virtual-to-physical translation is done using “pages,” where typical x86 page sizes are 4 kibibyte (4KiB), 2 mebibyte (2MiB), or 1 gibibyte (1GiB). The TLB entry for a page covers a range of addresses, corresponding to the page size. For example, if the TLB stores translation for a 2MiB page then there is a range of 2MiB virtual addresses which may be translated by the same TLB entry. When data utilization circuitry (e.g., processing circuitry running software on the integrated circuit) requests access to a particular virtual memory address that is on a page that was recently used and that is stored in the TLB, the TLB may rapidly translate the virtual memory address to its corresponding physical memory address.
In this way, the TLB may operate as a cache of mappings of pages of virtual memory addresses to physical memory addresses. When a virtual-to-physical address mapping is requested that may be found on a particular page that is currently stored in an entry of the TLB, this may be referred to as a “cache hit” or “TLB hit.” When the TLB does not currently have the requested mapping, however, this may be referred to as a “cache miss” or “TLB miss.” The requested mapping may first be loaded into the TLB before translation occurs. Some software applications may lose significant running time to TLB misses, so reducing the number of TLB misses may increase the rate at which the TLB can respond to TLB requests.
Rather than simply increasing the size of the TLB to reduce the odds of a TLB miss which could take up a substantial amount of valuable die area of the integrated circuit—a TLB may have several sub-TLBs that handle specific TLB requests corresponding to specific page sizes of memory. In particular, different software applications may use memory of page tables in a variety of sizes (e.g., 4 kibibyte (4KiB), 2 mebibyte (2MiB), or 1 gibibyte (1GiB)). These will be referred to below as 4K, 2M, and 1G, respectively. These are size ratios of 512×—e.g., 2 MiB is 512× larger than 4 KiB. Under certain conditions, a larger page size may be used in place of the next smaller size. This removes about 500× page mappings and so reduces competition for TLB space. For example, if an application touching 100,000×4 KiB pages can be promoted to use 2 MiB pages, then a TLB needs only about 200 TLB entries and this application will rarely take a TLB miss and will therefore run much faster.
Even so, some software applications may access memory primarily via 4K page size and may not use 1G page sizes at all. Other software applications may access memory primarily via 2M page size and may not use memory of the 4K page size. It therefore may be difficult to predict the memory usage pattern that would allow the TLB to operate most efficiently.
In this disclosure, a TLB may reduce the likelihood of a TLB miss using a configurable sub-TLB that is configurable to hold different page size sets at different times after boot to complement a fixed sub-TLB that holds a fixed page size set after boot. As used herein, a page size set represents a set of page sizes (which could be a single page size (e.g., 4K, 2M, 1G) or two or more page sizes (e.g., 4K+2M, 2M+1G, 4K+1G, 4K+2M+1G)) that can be accommodated by a sub-TLB. As discussed below, the number of pages in a page size set used by a configurable sub-TLB may change during runtime (e.g., a configurable fully associative sub-TLB may be reconfigurable at different times during runtime to hold 1G TLB entries, 1G+2M, 1G+4K, 1G+2M+4K).
A fixed sub-TLB is a sub-TLB that may only hold one page size set after boot. Some fixed sub-TLBs may be fixed at design time, while others may be fixed at boot. In any case, a fixed sub-TLB may not be reconfigured dynamically after boot to hold a different page size set. In one example, a fixed sub-TLB may be a sub-TLB that is defined to hold a fixed page size set of 4K page size; during runtime, this fixed sub-TLB may hold 4K TLB entries but not 2M or 1G TLB entries. In another example, a fixed sub-TLB may be a sub-TLB that is defined to hold a fixed page size set of 4K and 2M page sizes; during runtime, this fixed sub-TLB may hold 4K and 2M TLB entries but not 1G TLB entries. In a further example, a fixed sub-TLB may be a sub-TLB that is defined to hold a page size set of 2M and 1G page sizes; during runtime, this fixed sub-TLB may hold 2M and 1G TLB entries, but not 4K TLB entries. Once the page size set to be used by the fixed sub-TLB is fixed (e.g., at design, at manufacture, at deployment in the field, at boot), the fixed sub-TLB may not hold TLB entries of a different page size than found in the fixed page size set.
By contrast, a configurable sub-TLB is a portion of a TLB that can be dynamically configured after boot to hold TLB entries of more than one page size set. In this way, the configurable sub-TLB may accommodate changing memory usage during operation. Examples of configurable sub-TLBs include a configurable set-associative sub-TLB or a configurable fully associative sub-TLB. A configurable set-associative sub-TLB may support TLB entries corresponding to one specific page size set of memory at any one time, but may be dynamically configured (e.g., configured initially or reconfigured from an initial configuration) after boot to change which page size set is held by the configurable set-associative sub-TLB (e.g., only 4K entries at a first time, only 2M entries at a second time, only 1G entries at a third time). Some configurable set-associative sub-TLBs may be configurable to hold multiple page sizes at any one time and which of those multiple page sizes is configured to be contained in the page size set may be dynamically configured after boot (e.g., 4K and 2M, 4K and 1G, 2M and 1G) as memory usage conditions change during operation. For example, a fully-associative sub-TLB may support 4K/2M/1G pages at one time but then be reconfigured to support only 1G pages; or a 2-size set-associative configurable sub-TLB may be configured at one time to support 4K+1G pages and at another time to support 2M+1G pages. A fully associative sub-TLB may support TLB entries corresponding to multiple specific page sizes of memory (e.g., 4K, 2M, and 1G). A configurable sub-TLB may provide additional flexibility for different use cases having different memory size usage but may involve more overhead than a fixed-set sub-TLB.
The difference between a fixed sub-TLB and a configurable sub-TLB may be further explained by the following example. Consider a sub-TLB that may have 1536× entries that hold any mix of 4K and 2M pages. Such a sub-TLB may be considered a fixed sub-TLB because it can handle a fixed page size set consisting of 4K and 2M page sizes. This is “fixed” even though the sub-TLB may be able to handle a page size set of two page sizes. Note that 1536=1024+512. One “configurable” option would be to build two sub-TLBs, one handling a first page size set with 1024× fixed 4K+2M sizes, and a second handling a second page size set with 512× configurable entries that can be configured at different times to hold any two of the sizes (e.g., 4K+2M, 4K+1G, 2M+1G).
The combination of a fixed sub-TLB and a configurable sub-TLB may allow size assignments to be made dynamically at run-time rather than at build-time. In this way, resources can be directed toward the page sizes with the highest miss rates. For example, if entries of 4K page sizes are most in demand, a configurable set-associative sub-TLB may be configured to hold entries of a page size set that includes a 4K page size (e.g., rather than 2M or 1G) or the configurable fully associative sub-TLB may accommodate more 4K TLB entries and fewer 2M or 1G TLB entries. In another example, a configurable set-associative sub-TLB While this disclosure provides many examples relating to dynamic allocation of entries of specific page sizes involving the configurable fully associative sub-TLB and one or more fixed set-associative sub-TLBs, it should be understood that any other suitable types of fixed or configurable sub-TLBs may be used. For example, configurable set-associative sub-TLBs may be used (e.g., in place of the configurable fully associative sub-TLB or in place of one or more of the fixed set-associative sub-TLBs).
These features may be used in any suitable integrated circuit devices, including microprocessors, application-specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). The following architecture discussed below with respect to
Write mask registers 14 may include m (e.g., 8) write mask registers (k0 through km), each having a number (e.g., 64) of bits. Additionally or alternatively, at least some of the write mask registers 14 may have a different size (e.g., 16 bits). At least some of the vector mask registers 12 (e.g., k0) are prohibited from being used as a write mask. When such vector mask registers are indicated, a hardwired write mask (e.g., 0xFFFF) is selected and, effectively disabling write masking for that instruction.
General-purpose registers 16 may include a number (e.g., 16) of registers having corresponding bit sizes (e.g., 64) that are used along with x86 addressing modes to address memory operands. These registers may be referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15. Parts (e.g., 32 bits of the registers) of at least some of these registers may be used for modes (e.g., 32-bit mode) that is shorter than the complete length of the registers.
Scalar floating-point stack register file (x87 stack) 18 has an MMX packed integer flat register file 20 is aliased. The x87 stack 18 is an eight-element (or other number of elements) stack used to perform scalar floating-point operations on floating point data using the x87 instruction set extension. The floating-point data may have various levels of precision (e.g., 16, 32, 64, 80, or more bits). The MMX packed integer flat register files 20 are used to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between the MMX packed integer flat register files 20 and the XMM registers.
Alternative embodiments may use wider or narrower registers. Additionally, alternative embodiments may use more, less, or different register files and registers.
Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: 1) a general purpose in-order core suitable for general-purpose computing; 2) a high performance general purpose out-of-order core suitable for general-purpose computing; 3) a special purpose core suitable for primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general purpose in-order cores suitable for general-purpose computing and/or one or more general purpose out-of-order cores suitable for general-purpose computing; and 2) a coprocessor including one or more special purpose cores primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: 1) the coprocessor on a separate chip from the CPU; 2) the coprocessor on a separate die in the same package as a CPU; 3) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and 4) a system on a chip that may include on the same die the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Example core architectures are described next, followed by descriptions of example processors and computer architectures.
In
The front-end unit 56 includes a branch prediction unit 62 coupled to an instruction cache unit 64 that is coupled to an instruction translation lookaside buffer (TLB) 66. The TLB 66 is coupled to an instruction fetch unit 68. The instruction fetch unit 68 is coupled to a decode circuitry 70. The decode circuitry 70 (or decoder) may decode instructions and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode circuitry 70 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. The processor core 54 may include a microcode ROM or other medium that stores microcode for macroinstructions (e.g., in decode circuitry 70 or otherwise within the front-end unit 56). The decode circuitry 70 is coupled to a rename/allocator unit 72 in the execution engine unit 58.
The execution engine unit 58 includes a rename/allocator unit 72 coupled to a retirement unit 74 and a set of one or more scheduler unit(s) 76. The scheduler unit(s) 76 represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s) 76 is coupled to physical register file(s) unit(s) 78. Each of the physical register file(s) unit(s) 78 represents one or more physical register files storing one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, statuses (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit(s) 78 includes the vector registers 12, the write mask registers 14, and/or the x87 stack 18. These register units may provide architectural vector registers, vector mask registers, and general-purpose registers. The physical register file(s) unit(s) 78 is overlapped by the retirement unit 74 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.).
The retirement unit 74 and the physical register file(s) unit(s) 78 are coupled to an execution cluster(s) 80. The execution cluster(s) 80 includes a set of one or more execution units 82 and a set of one or more memory access circuitries 84. The execution units 82 may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform multiple different functions. The scheduler unit(s) 76, physical register file(s) unit(s) 78, and execution cluster(s) 80 are shown as being singular or plural because some processor cores 54 create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster. In the case of a separate memory access pipeline, a processor core 54 for the separate memory access pipeline is the only the execution cluster 80 that has the memory access circuitry 84). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest perform in-order execution.
The set of memory access circuitry 84 is coupled to the memory unit 60. The memory unit 60 includes a data TLB unit 86 coupled to a data cache unit 88 coupled to a level 2 (L2) cache unit 90. The memory access circuitry 84 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 86 in the memory unit 60. The instruction cache unit 64 is further coupled to the level 2 (L2) cache unit 90 in the memory unit 60. The L2 cache unit 90 is coupled to one or more other levels of caches and/or to a main memory.
By way of example, the register renaming, out-of-order issue/execution core architecture may implement the pipeline 30 as follows: 1) the instruction fetch unit 68 performs the fetch and length decoding stages 32 and 34 of the pipeline 30; 2) the decode circuitry 70 performs the decode stage 36 of the pipeline 30; 3) the rename/allocator unit 72 performs the allocation stage 38 and renaming stage 40 of the pipeline; 4) the scheduler unit(s) 76 performs the schedule stage 42 of the pipeline 30; 5) the physical register file(s) unit(s) 78 and the memory unit 60 perform the register read/memory read stage 44 of the pipeline 30; the execution cluster 80 performs the execute stage 46 of the pipeline 30; 6) the memory unit 60 and the physical register file(s) unit(s) 78 perform the write back/memory write stage 48 of the pipeline 30; 7) various units may be involved in the exception handling stage 50 of the pipeline; and/or 8) the retirement unit 74 and the physical register file(s) unit(s) 78 perform the commit stage 52 of the pipeline 30.
The processor core 54 may support one or more instructions sets, such as an x86 instruction set (with or without additional extensions for newer versions); a MIPS instruction set of MIPS Technologies of Sunnyvale, Calif.; an ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, Calif.). Additionally or alternatively, the processor core 54 includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), thereby allowing the operations used by multimedia applications to be performed using packed data.
It should be understood that the core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof, such as a time-sliced fetching and decoding and simultaneous multithreading in INTEL® Hyperthreading technology.
While register renaming is described in the context of out-of-order execution, register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes a separate instruction cache unit 64, a separate data cache unit 88, and a shared L2 cache unit 90, some processors may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache, or multiple levels of the internal cache. In some embodiments, the processor may include a combination of an internal cache and an external cache that is external to the processor core 54 and/or the processor. Alternatively, some processors may use a cache that is external to the processor core 54 and/or the processor.
The local subset of the L2 cache 104 is part of a global L2 cache unit 90 that is divided into separate local subsets, one per processor core. Each processor core 54 has a direct access path to its own local subset of the L2 cache 104. Data read by a processor core 54 is stored in its L2 cache 104 subset and can be accessed quickly, in parallel with other processor cores 54 accessing their own local L2 cache subsets. Data written by a processor core 54 is stored in its own L2 cache 104 subset and is flushed from other subsets, if necessary. The interconnection network 100 ensures coherency for shared data. The interconnection network 100 is bi-directional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. Each data-path may have a number (e.g., 1012) of bits in width per direction.
Thus, different implementations of the processor 130 may include: 1) a CPU with the special purpose logic 136 being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores 54A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination thereof); 2) a coprocessor with the cores 54A-N being a relatively large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores 54A-N being a relatively large number of general purpose in-order cores. Thus, the processor 130 may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, or the like. The processor 130 may be implemented on one or more chips. The processor 130 may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.
The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units 140, and external memory (not shown) coupled to the set of integrated memory controller unit(s) 132. The set of shared cache units 140 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While a ring-based interconnect network 100 may interconnect the integrated graphics logic 136 (integrated graphics logic 136 is an example of and is also referred to herein as special purpose logic 136), the set of shared cache units 140, and/or the system agent unit 134/integrated memory controller unit(s) 132 may use any number of known techniques for interconnecting such units. For example, coherency may be maintained between one or more cache units 142A-N and cores 54A-N.
In some embodiments, one or more of the cores 54A-N are capable of multi-threading. The system agent unit 134 includes those components coordinating and operating cores 54A-N. The system agent unit 134 may include, for example, a power control unit (PCU) and a display unit. The PCU may be or may include logic and components used to regulate the power state of the cores 54A-N and the integrated graphics logic 136. The display unit is used to drive one or more externally connected displays.
The cores 54A-N may be homogenous or heterogeneous in terms of architecture instruction set. That is, two or more of the cores 54A-N may be capable of execution of the same instruction set, while others may be capable of executing only a subset of a single instruction set or a different instruction set.
Referring now to
The optional nature of an additional processor 130B is denoted in
The memory 158 may be, for example, dynamic random-access memory (DRAM), phase change memory (PCM), or a combination thereof. For at least one embodiment, the controller hub 152 communicates with the processor(s) 130A, 130B via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection 162.
In one embodiment, the coprocessor 160 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like. In an embodiment, the controller hub 152 may include an integrated graphics accelerator.
There can be a variety of differences between the physical resources of the processors 130A, 130B in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.
In some embodiments, the processor 130A executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor 130A recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor 160. Accordingly, the processor 130A issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to the coprocessor 160. The coprocessor 160 accepts and executes the received coprocessor instructions.
Referring now to
Processors 172 and 174 are shown including integrated memory controller (IMC) units 178 and 180, respectively. The processor 172 also includes point-to-point (P-P) interfaces 182 and 184 as part of its bus controller units. Similarly, the processor 174 includes P-P interfaces 186 and 188. The processors 172, 174 may exchange information via a point-to-point interface 190 using P-P interfaces 184, 188. As shown in
Processors 172, 174 may each exchange information with a chipset 194 via individual P-P interfaces 196, 198 using point-to-point interfaces 182, 200, 186, 202. Chipset 194 may optionally exchange information with the coprocessor 176 via a high-performance interface 204. In an embodiment, the coprocessor 176 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like.
A shared cache (not shown) may be included in either processor 172 or 174 or outside of both processors 172 or 174 that is connected with the processors 172, 174 via respective P-P interconnects such that either or both processors' local cache information may be stored in the shared cache if a respective processor is placed into a low power mode.
The chipset 194 may be coupled to a first bus 206 via an interface 208. In an embodiment, the first bus 206 may be a Peripheral Component Interconnect (PCI) bus or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited.
As shown in
Referring now to
Referring now to
Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the disclosure may be implemented as computer programs and/or program code executing on programmable systems including at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.
Program code, such as data 224 illustrated in
The program code may be implemented in a high-level procedural or object-oriented programming language to communicate with a processing system. The program code may also be implemented in an assembly language or in a machine language. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled language or an interpreted language.
One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium that represents various logic within the processor that, when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores,” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that make the logic or processor.
Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic cards, optical cards, or any other type of media suitable for storing electronic instructions.
Accordingly, embodiments of the embodiment include non-transitory, tangible machine-readable media containing instructions or containing design data, such as designs in Hardware Description Language (HDL) that may define structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.
In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert instructions to one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be implemented on processor, off processor, or part on and part off processor.
Similarly,
As discussed above, an integrated circuit may retrieve memory for a variety of purposes (e.g., instruction data, user data). While the data is stored in a physical memory address representing an actual location in a memory device, software running on the integrated circuit may operate using a virtual memory address that is translated to the physical memory address when the memory is accessed. A structure on the integrated circuit known as a translation lookaside buffer (TLB) (e.g., the instruction TLB 66 or the data TLB 86) may reduce the time taken to access a memory location by storing recently used mappings of virtual memory addresses to their corresponding physical memory addresses. While the disclosure below refers specifically to the TLB 86, it should be appreciated that the architecture and methods relating to the TLB 86 may be used in any suitable TLB, which may include the TLB 66 or other TLBs. When data utilization circuitry (e.g., processing circuitry running software) requests access to a particular virtual memory address that was recently used and that is stored in the TLB, the TLB may rapidly translate the virtual memory address to its corresponding physical memory address.
For example, as shown in
The TLB 86 may reduce the likelihood of a TLB miss using a configurable sub-TLB that is configurable to hold different page size sets at different times after boot to complement a fixed sub-TLB that holds a fixed page size set after boot. As used herein, a page size set represents a set of page sizes (which could be a single page size (e.g., 4K, 2M, 1G) or two or more page sizes (e.g., 4K+2M, 2M+1G, 4K+1G, 4K+2M+1G)) that can be accommodated by a sub-TLB. As discussed below, the number of pages in a page size set used by a configurable sub-TLB may change during runtime (e.g., a configurable fully associative sub-TLB may be reconfigurable at different times during runtime to hold 1G TLB entries, 1G+2M, 1G+4K, 1G+2M+4K).
As mentioned above, a fixed sub-TLB is a sub-TLB that may only hold one page size set after boot. Some fixed sub-TLBs may be fixed at design time, while others may be fixed at boot. In any case, a fixed sub-TLB may not be reconfigured dynamically after boot to hold a different page size set. In one example, a fixed sub-TLB may be a sub-TLB that is defined to hold a fixed page size set of 4K page size; during runtime, this fixed sub-TLB may hold 4K TLB entries but not 2M or 1G TLB entries. In another example, a fixed sub-TLB may be a sub-TLB that is defined to hold a fixed page size set of 4K and 2M page sizes; during runtime, this fixed sub-TLB may hold 4K and 2M TLB entries but not 1G TLB entries. In a further example, a fixed sub-TLB may be a sub-TLB that is defined to hold a page size set of 2M and 1G page sizes; during runtime, this fixed sub-TLB may hold 2M and 1G TLB entries, but not 4K TLB entries. Once the page size set to be used by the fixed sub-TLB is fixed (e.g., at design, at manufacture, at deployment in the field, at boot), the fixed sub-TLB may not hold TLB entries of a different page size than found in the fixed page size set.
By contrast, a configurable sub-TLB is a portion of a TLB that can be dynamically configured after boot to hold TLB entries of more than one page size set. In this way, the configurable sub-TLB may accommodate changing memory usage during operation. Examples of configurable sub-TLBs include a configurable set-associative sub-TLB or a configurable fully associative sub-TLB. A configurable set-associative sub-TLB may support TLB entries corresponding to one specific page size set of memory at any one time, but may be dynamically configured (e.g., configured initially or reconfigured from an initial configuration) after boot to change which page size set is held by the configurable set-associative sub-TLB (e.g., only 4K entries at a first time, only 2M entries at a second time, only 1G entries at a third time). Some configurable set-associative sub-TLBs may be configurable to hold multiple page sizes at any one time and which of those multiple page sizes is configured to be contained in the page size set may be dynamically configured after boot (e.g., 4K and 2M, 4K and 1G, 2M and 1G) as memory usage conditions change during operation. For example, a configurable fully-associative sub-TLB may support 4K/2M/1G pages at one time but then be reconfigured to support only 1G pages; or a 2-size set-associative configurable sub-TLB may be configured at one time to support 4K+1G pages and at another time to support 2M+1G pages. A configurable fully associative sub-TLB may support TLB entries corresponding to multiple specific page sizes of memory (e.g., 4K, 2M, and 1G). A configurable sub-TLB may provide additional flexibility for different use cases having different memory size usage but may involve more overhead than a fixed sub-TLB.
The difference between a fixed sub-TLB and a configurable sub-TLB may be further explained by the following example. Consider a fixed sub-TLB that may have 1536× entries that hold any mix of 4K and 2M pages. Such a sub-TLB may be considered a fixed sub-TLB because it can handle a fixed page size set consisting of 4K and 2M page sizes. This is “fixed” even though the sub-TLB may be able to handle a page size set of two page sizes. Note that 1536=1024+512. One “configurable” option would be to build two sub-TLBs, one handling a first page size set with 1024× fixed 4K+2M sizes, and a second handling a second page size set with 512× configurable entries that can be configured at different times to hold any two of the sizes (e.g., 4K+2M, 4K+1G, 2M+1G).
To reiterate, a sub-TLB may vary in (1) which size(s) it supports—possibly one page size, but possibly several page sizes, and (2) whether the supported set of page sizes is a fixed design-time (or, say, boot-time) choice, or whether it can be reconfigured/adjusted dynamically. The systems and methods of this disclosure may be contrasted with the structure of many TLBs (e.g., certain first-level TLBs (L1DTLBs)) that may use (1) fixed set-associative sub-TLBs that support only one size, and the size is selected at design time (“one size” makes it easier to meet circuit timing) or (2) fully-associative sub-TLBs that are small. These fully associative sub-TLBs may be single-size (as in many cases, which may use a 1G FA sub-TLB) or multi-size (as in many other cases, which support 4K/2M/1G in the FA TLB) but the size selection is fixed at design time, and they do not pair the all-size FA sub-TLB with another sub-TLB, so they do not have the problem/consideration of deciding which sub-TLB to use to fill an entry—the L1DTLB is only an 4K+2M+1G FA structure, so there is no other sub-TLB they can choose.
The systems and methods of this disclosure may also be contrasted with the structure of other TLBs, such as many second-level TLBs (L2TLB) that use fixed set-associative sub-TLBs that support two sizes, and the size is selected at design time. For many processors, there is an L2 sub-TLB that supports any mix of 4K+2M pages. “Two sizes” makes it harder to meet circuit timing (hence not used in L1 TB), but can be more efficient because the all the entries can be used for any mix of the sizes. However, while this is multiple sizes, the sizes are selected at design time.
What is used in this disclosure is a sub-TLB that supports dynamically configurable page sizes. This side-steps some circuit design issues (e.g., building a fixed 2-size L2 sub-TLB may have some down-sides, building a fixed 3-size L2 sub-TLB may have even more down-sides). Using a configurable 2-size TLB lets us pick which 2 page sizes to support (so it is 3 sizes but only 2 at a time) which gives up some flexibility but is simpler/faster circuitry than a fixed 3-size sub-TLB. Consider an example in which a TLB of this disclosure has a fixed-configuration 2-size sub-TLB, a fixed-configuration 3-size sub-TLB, and a configurable 2-size sub-TLB that can be reconfigured among three sizes (but only two at one time). Here, it makes sense to think of this example's configurable sub-TLB as “2-size” because it only does 2 sizes for any one configuration, but also “3-size” because it can be re-configured among 3 page sizes (even though it can only support 2 page sizes in any given configuration). Note that, in some cases, the configurable sub-TLB may be the only sub-TLB that can hold some sizes—for example, the TLB may have a configurable fully associative sub-TLB that is the only place to hold 1G TLB entries. So in the case where there are many 1G TLB entries (or a high miss rate on 1G TLB entries), it is desirable to prevent 4K/2M mappings from evicting 1G mappings. Thus, in cases such as these, some page sizes may be treated as “special” under certain conditions (e.g., they may be marked as “sticky” as discussed further below).
The combination of a fixed sub-TLB and a configurable sub-TLB may allow size assignments to be made dynamically at run-time rather than at build-time. In this way, resources can be directed toward the page sizes with the highest miss rates. For example, if entries of 4K page sizes are most in demand, a configurable set-associative sub-TLB may be configured to hold entries of a page size set that includes a 4K page size (e.g., rather than 2M or 1G) or a configurable fully associative sub-TLB may accommodate more 4K TLB entries and fewer 2M or 1G TLB entries. In another example, a configurable set-associative sub-TLB While this disclosure provides many examples relating to dynamic allocation of entries of specific page sizes involving a configurable fully associative sub-TLB and one or more fixed set-associative sub-TLBs, it should be understood that any other suitable types of fixed or configurable sub-TLBs may be used. For example, configurable set-associative sub-TLBs may be used (e.g., in place of the fully associative sub-TLB or in place of one or more of the fixed set-associative sub-TLBs).
Several non-limiting examples of TLBs are shown in
As a specific example, a TLB may use a fixed set-associative sub-TLB holding 4K and 2M mappings and a fully associative sub-TLB holding 1G mappings. The fully associative sub-TLB may be replaced with a 2-size fixed set-associative sub-TLB where the sizes can be reconfigured to some or all of: 4K-only, 2M-only, 1G-only, 4K+2M, 4K+1G, or 2M+1G. For example, if no 1G pages are in-use, it may be configured as 4K+2M; if 1G is in-use then it may be configured as 4K+1G or 2M+1G, depending on which page size is currently suffering the worst miss rate.
Turning to
Other combinations may also be used. For example,
Before continuing, it may be noted that the number of entries supported by the fixed set-associative sub-TLBs 320, 322, and 324 and the configurable fully associative sub-TLB 326 may vary. For instance, the sub-TLB 320 may hold more entries than the sub-TLB 322, and the sub-TLB 322 may hold more entries than the sub-TLB 324. Because the configurable fully associative sub-TLB 326 may involve more overhead (e.g., may take more die space due to the size of its TLB entries or the control circuitry involved in operating it), in some cases, the configurable fully associative sub-TLB 326 may hold fewer entries than the fixed set-associative sub-TLBs 320, 322, or 324. In examples where the configurable fully associative sub-TLB 326 takes the place of a fixed set-associative sub-TLBs 320, 322, or 324, the configurable fully associative sub-TLB 326 may have a size corresponding to that fixed set-associative sub-TLBs 320, 322, or 324. For example, the configurable fully associative sub-TLB 326 may be larger when taking the place of the fixed set-associative sub-TLB 320 than when taking the place of the set associative TLB 324. Moreover, these examples describe a TLB 86 in which the fixed set-associative sub-TLB 320 holds TLB entries corresponding to 4K memory page sizes, the fixed set-associative sub-TLB 322 holds TLB entries corresponding to 2M memory page sizes, the fixed set-associative sub-TLB 324 holds TLB entries corresponding to 1G memory page sizes, and the configurable fully associative sub-TLB 326 holds TLB entries corresponding to 4K, 2M, and 1G memory page sizes. However, it should be appreciated that any suitable memory page sizes, any suitable number of memory page sizes may be used, and any suitable page size sets may be respectively supported by the different sub-TLBs. For example, there may be additional or different fixed set-associative sub-TLBs beyond the sub-TLBs 320, 322, or 324. Moreover, the fully associative TLB 326 may hold TLB entries for page sizes not held by any other fixed set-associative sub-TLBs. In one example, the configurable fully associative sub-TLB 326 may hold TLB entries for 4KiB, 2MiB, 1GiB, and 512GiB page sizes.
The examples below will describe a TLB 86 that includes the configurable fully associative sub-TLB 326 and the fixed set-associative sub-TLBs 320 and 322 (where the configurable fully associative sub-TLB 326 takes the place of the fixed set-associative sub-TLB 324). However, it should be appreciated that the systems and methods of this disclosure are not limited to this example, but may be used with any suitable arrangement. In the TLB 86 shown in
The new TLB entry will be subsequently stored in the TLB 86. To do so, an existing TLB entry is selected that will be “evicted” or “replaced” to make room for the new TLB entry. In a conventional TLB, the only replacement candidates are from a fixed sub-TLB associated with the indicated page size. To gain efficiencies from the configurable fully associative sub-TLB, new TLB entries may be selected to replace TLB entries from either a corresponding fixed set-associative sub-TLB or the configurable fully associative sub-TLB. One example is shown by a flowchart 360 of
When a fixed set-associative (SA) sub-TLB corresponding to the memory page size of the TLB request is selected, the new TLB entry may replace an existing entry on the fixed set-associative sub-TLB based on the policy of that fixed set-associative sub-TLB (block 370). For example, the new TLB entry may replace an existing TLB entry on a least recently used (LRU) or pseudo least recently used (pLRU) scheme. When the configurable fully associative (FA) sub-TLB is selected, the new TLB entry may replace an existing entry based on the policy of the configurable fully associative sub-TLB (block 372). Several examples of these policies will also be discussed further below.
For example, as shown in
There may be many ways to select whether to store a new TLB entry in a corresponding fixed sub-TLB or in a configurable sub-TLB. These may be used separately or in combination.
By tracking the miss rates of the sub-TLBs, the fully associative TLB may be reserved for TLB entries of page sizes currently experiencing the highest demand (e.g., 4K or 2M).
In some cases, the miss rate of the configurable fully associative sub-TLB may be considered. For example, as shown in
Additionally or alternatively, the TLB may select whether to store a new TLB entry in a fixed set-associative sub-TLB or the configurable fully associative sub-TLB depending on a ratio of the availability of entries between a corresponding fixed set-associative TLB and the configurable fully associative TLB. A flowchart of
Additionally or alternatively, the allocation to the configurable fully associative sub-TLB 326 may be less than 100%. In one example, the allocation of available entries in the configurable fully associative sub-TLB 326 may be divided among the fixed set-associative sub-TLBs 320 and 322 (e.g., 50% allocated to 4K and 50% allocated to 2M). In another example, discussed further below, some TLB entries of the fully associative TLB 326 may be marked as “sticky” for another page size and therefore unavailable. Dividing the assignment of the TLB entries of the configurable fully associative sub-TLB 326 may produce different results. For example, if the TLB entries of the configurable fully associative sub-TLB 326 are divided 50% to the 4K size and 50% to the 2M size, the proportion for assigning a new TLB entry of the 4K size may be 64/(64+4) to the sub-TLB 320 and 4/(64+4) to the configurable fully associative sub-TLB 326.
There may also be many ways to replace TLB entries in a configurable sub-TLB, and these, too may be used separately or in combination. In one example, as shown by a flowchart 460 of
Another example involves designating certain TLB entries or entry locations of the configurable fully associative sub-TLB as “sticky” and reserved for only TLB entries of a particular page size or sizes. Thus, a “sticky” TLB entry may only be replaced by a new TLB entry of the same “sticky” page size or sizes. For example, when the configurable fully associative sub-TLB takes the place of a 2M fixed set-associative sub-TLB and a 1G fixed set-associative sub-TLB, it may be desirable to prevent the 2M and 1G TLB entries from being dominated by 4K entries. In this example, marking 1G and 2M TLB entries as “sticky” may prevent a 4K entry (a “non-sticky” page size) from evicting either a 2M TLB entry or a 1G TLB entry. In another example, when the configurable fully associative sub-TLB takes the place of a 1G fixed set-associative sub-TLB, the 1G page size may be considered “sticky” and the 2M and 4K page sizes may be considered “non-sticky.” In this example, marking 1G TLB entries as “sticky” may prevent 1G TLB entries from being evicted by 2M or 4K TLB entries. Additionally or alternatively, marking a TLB entry or entry location as “sticky” may prevent that TLB entry from being evicted by a new TLB entry regardless of page size.
The sticky bit or bits 470 may be implemented and used in a variety of ways. In one example, the sticky bit or bits 470 may be associated with every TLB entry, but only set under certain conditions (e.g., when a 1G TLB entry is stored in a particular TLB entry location). In another example, there may be just one global sticky bit. Once a particular page size (e.g., 1G) has been used in any TLB entry, the global sticky bit may cause the TLB not to let a TLB entry of a different page size (e.g., 4K or 2M) evict a TLB entry of the particular page size (e.g., 1G). In another example, there may be one sticky bit per page size. For instance, if 4K pages are a high-miss “problem” and 2M pages are not, then the sticky bit may prevent 2M pages from evicting anything but 2M pages, but may allow 4K pages to evict 2M pages.
In some cases, as shown by a flowchart 480 of
Certain TLB entries of the configurable fully associative sub-TLB may be marked as “sticky” based on a count relating to uses of specific entries of the TLB (e.g., a direct count of the uses, a count incremented every so many uses, some other proxy indication relating to the number of specific uses).
In some cases, the “sticky” bit or bits and “counter” may be unified, for example a 3-bit counter that holds values 0 . . . 7 and where 0 . . . 6 indicates non-sticky and count-in-progress, while 7 indicates sticky.
While these examples have described stickiness per entry, the sticky bit or bits may define stickiness throughout the configurable fully associative sub-TLB. For instance, there may be a global “sticky” bit or bits for the configurable fully associative sub-TLB that may define whether any entries of a particular page size may be evicted. For example, setting a global “sticky” bit may cause all 1G TLB entries of the configurable fully associative sub-TLB to be unable to be evicted by 4K or 2M TLB entries. In another example, setting the global “sticky” bit may cause all 2M and 1G TLB entries to be unable to be evicted by 4K TLB entries.
In some cases, whether to mark a TLB entry of the configurable fully associative sub-TLB as “sticky” may be determined based on a count of total uses of the configurable fully associative sub-TLB.
The counter 520 may be implemented in a variety of ways. In one example, the counter 520 may represent one counter to count TLB entries of all sizes except 1G in this example, since there is no other place to put 1G mappings, so it may be desirable to “bias” towards preferring 1G over not-1G. In another example, there may be one counter per page size. In a way, this approximates one counter per entry, but summarizes based on the page size. This improves on one counter in that the TLB can “give up” early for whatever size is not-a-problem and keep trying for whatever size is-a-problem.
As provided by a flowchart 530 of
In some cases, whether to mark a TLB entry of the configurable fully associative sub-TLB as “sticky” may be determined based on a count of total uses of the TLB or a count of some number of clock cycles. For example, as shown in
Although the use of “sticky” bits may prevent entries of certain page sizes (e.g., 1G) from being dominated by entries of other page sizes (e.g., 4K or 2M), over time, the number of sticky entries may dominate. Accordingly, the sticky bits may be reset from time to time. For example, as indicated by a flowchart 560 shown in
In another example shown in a flowchart 570 of
Additionally or alternatively, a “second chance” scheme may be used. The “second chance” scheme may reset sticky bits after a particular “sticky” TLB entry is attempted to be reset some threshold number of times. For example, as shown in a flowchart 590 of
The TLB entries of the configurable fully associative sub-TLB may take any suitable data structure. One example appears in
The TLB entry structure 602 may also include a size state field (sz) 620, which may identify the page size of the TLB entry. For example, this field may be one bit wide when two page sizes are used in the configurable fully associative sub-TLB. When the TLB entry structure 602 accommodates any one of three page sizes (e.g., 4K, 2M, 1G), the field may be two or more bits wide. The size may also be indicated via some other mechanism. As an example, consider a 16-entry FA sub-TLB with an indicator [0 . . . 16] which says everything below the indicator is 1G; and everything at or above the indicator is 2M. In this example, filling a 1G mapping would increment the indictor and put the entry at the “new” location; while filling a 2M mapping would select from entries at or above the indicator.
As noted above, the TLB entry structure 602 may also include a sticky (s) field 622. The sticky field 622 may be a single bit (i.e., “sticky” or “not sticky”) or may take up more than one bit to provide varying degrees of “stickiness” (e.g., which may be used in “second chance” resetting techniques, may define whether the entry location is sticky or just the currently stored TLB entry, or may be incremented upon a TLB hit and decremented upon a TLB miss). The TLB entry structure 602 may also have other fields not shown in
The approach above was tested with a set of workload traces. The testing started with a standard trace library and involved selecting those traces which in cycle-accurate simulation spent 10% or more of wallclock time waiting for TLB misses, using a baseline TLB configuration similar to certain currently available processors. A functional (counting, but not cycle-accurate) simulator was modified to implement one version of the disclosed design. Notably, the 1 GiB sub-TLB was modified to accept all page sizes. The simulator implemented simple pseudo-random selection and a simple “sticky” implementation for 1G pages in the FA. (E.g., no miss rate tracking, no complicated “sticky” aging.) Three versions of the disclosed method were considered: (a) 4 KiB and 1 GiB page mappings in the FA array; (b) 2 MiB and 1 GiB page mappings in the FA array; and (c) all three page sizes in the FA array.
A functional simulator has no notion of time, so the metric MPKI or “misses per thousand instructions” was used to evaluate the approach. MPKI changes do not translate directly to performance changes—for any given workload, the size of the MPKI change may be more or less than the size of the performance change. However, MPKI improvements are typically associated with performance improvements.
For the configuration and workloads described above, we saw
The above is described in terms of a first-level data TLB, but other TLBs can use similar approaches. These may also include TLBs built entirely of fixed set-associative sub-TLBs (no fully-associative sub-TLBs) and TLBs that include one or more configurable set-associative sub-TLBs.
EXAMPLE EMBODIMENT 1. An integrated circuit comprising a translation lookaside buffer (TLB) that comprises:
a first fixed sub-TLB that, during runtime, stores a first plurality of TLB entries corresponding to a first page size set; and
a configurable sub-TLB that, during runtime, is configurable to store a second plurality of TLB entries of a second page size set that includes at least a first page size of the first page size set and includes at least a second page size not of the first page size set.
EXAMPLE EMBODIMENT 2. The integrated circuit of example embodiment 1, wherein the first fixed sub-TLB comprises a fixed set-associative sub-TLB.
EXAMPLE EMBODIMENT 3. The integrated circuit of example embodiment 1, wherein the configurable sub-TLB comprises a configurable set-associative sub-TLB.
EXAMPLE EMBODIMENT 4. The integrated circuit of example embodiment 1, wherein the configurable sub-TLB comprises a configurable fully associative sub-TLB.
EXAMPLE EMBODIMENT 5. The integrated circuit of example embodiment 1, wherein the first page size of the first page size set comprises a 4KiB page size and the second page size of the second page size set comprises a 1 GiB page size.
EXAMPLE EMBODIMENT 6. The integrated circuit of example embodiment 5, wherein the second page size set comprises a third page size, wherein the third page size comprises a 2 MiB page size, and wherein the first page size set does not comprise the 1 GiB page size or the 2. MiB page size.
EXAMPLE EMBODIMENT 7. The integrated circuit of example embodiment 1, wherein the second page size set comprises at least one page size not supported by any other sub-TLBs of the TLB.
EXAMPLE EMBODIMENT 8. The integrated circuit of example embodiment 1, wherein the first fixed sub-TLB holds more TLB entries than the configurable sub-TLB.
EXAMPLE EMBODIMENT 9. The integrated circuit of example embodiment 1, wherein the TLB comprises control circuitry that selects whether to store a new TLB entry corresponding to the first page size set in the first fixed sub-TLB or in the configurable sub-TLB based at least in part on a ratio of available entries in the first fixed sub-TLB and the configurable sub-TLB.
EXAMPLE EMBODIMENT 10. The integrated circuit of example embodiment 1, wherein:
the fixed sub-TLB comprises a first fixed set-associative sub-TLB that, during runtime, is configured to store the first plurality of TLB entries corresponding to the first page size set;
the first page size set includes only a first page size;
the TLB comprises a second fixed set-associative sub-TLB that, during runtime, is configured to store a third plurality of TLB entries corresponding to a third page size set; and
the third page size set includes only a third page size.
EXAMPLE EMBODIMENT 11. The integrated circuit of example embodiment 10, wherein the second page size set includes the third page size.
EXAMPLE EMBODIMENT 12. The integrated circuit of example embodiment 11, wherein the first page size set comprises a page size of 4KiB, the second page size set comprises a page size of 1GiB, and the third page size set comprises a page size of 2MiB.
EXAMPLE EMBODIMENT 13. The integrated circuit of example embodiment 11, wherein the TLB comprises control circuitry that monitor a first miss rate of the first set-associative TLB and a second miss rate of the second set-associative TLB, and wherein the control circuitry is configured to select whether to store a new TLB entry corresponding to the first page size in the first fixed set-associative sub-TLB or in the configurable sub-TLB based at least in part on whether the first miss rate is higher than the second miss rate.
EXAMPLE EMBODIMENT 14. The integrated circuit of example embodiment 13, wherein the TLB comprises control circuitry that monitors a third miss rate of the configurable sub-TLB, and wherein the control circuitry is configured to select whether to store the new TLB entry corresponding to the first page size set in the first fixed set-associative sub-TLB or in the configurable sub-TLB based at least in part on whether the third miss rate is higher than the first miss rate and the second miss rate.
EXAMPLE EMBODIMENT 15. The integrated circuit of example embodiment 1, wherein the integrated circuit comprises a processor and wherein the TLB operates as an instruction TLB for the processor.
EXAMPLE EMBODIMENT 16. The integrated circuit of example embodiment 1, wherein the integrated circuit comprises memory access circuitry and the TLB operates as a data TLB for the memory access circuitry.
EXAMPLE EMBODIMENT 17. A method comprising:
receiving, at a translation lookaside buffer (TLB), a TLB request that results in a TLB miss;
retrieving, from a page table, a new TLB entry corresponding to the TLB request; and
selecting between:
replacing a first old TLB entry from a first fixed sub-TLB of the TLB with the new TLB entry; and
replacing a second old TLB entry from a configurable sub-TLB of the TLB with the new TLB entry.
EXAMPLE EMBODIMENT 18. The method of example embodiment 17, wherein the selecting is based at least in part on a ratio of available entries in the first fixed sub-TLB and configurable sub-TLB.
EXAMPLE EMBODIMENT 19. The method of example embodiment 18, wherein entries in the configurable sub-TLB are not considered available if marked as “sticky” and therefore reserved for a different page size than the new TLB entry.
EXAMPLE EMBODIMENT 20. A method comprising:
receiving, at a translation lookaside buffer (TLB) that includes a first fixed sub-TLB corresponding to a first page size set and a configurable sub-TLB corresponding to the first page size set and a second page size set, a TLB request corresponding to the second page size set that results in a TLB miss;
EXAMPLE EMBODIMENT 21. The method of example embodiment 20, wherein the new TLB entry is identified as “sticky” in response to being stored in the configurable sub-TLB and corresponding to the second page size set.
EXAMPLE EMBODIMENT 22. The method of example embodiment 20, comprising, before identifying the new TLB entry in the configurable sub-TLB as “sticky,” receiving, at the TLB, a TLB request corresponding to the new TLB entry that results in a TLB hit, wherein the new TLB entry is identified as “sticky” in response to the TLB hit for the new TLB entry.
EXAMPLE EMBODIMENT 23. The method of example embodiment 20, comprising:
maintaining a count relating to a number of times that an entry location of the configurable sub-TLB corresponding to the new TLB entry is used to store a TLB entry of the second page size set, wherein the new TLB entry is identified as “sticky” in response to the count exceeding a threshold number.
EXAMPLE EMBODIMENT 24. The method of example embodiment 20, comprising:
maintaining a count relating to a number of times that the configurable sub-TLB is used to store a TLB entry of the second page size set, wherein the new TLB entry is identified as “sticky” in response to the count exceeding a threshold number.
EXAMPLE EMBODIMENT 25. The method of example embodiment 20, comprising maintaining a first count relating to TLB requests received by the TLB or maintaining a second count relating to a number of clock cycles, wherein the new TLB entry is identified as “sticky” in response to the first count exceeding a first threshold or the second count exceeding a second threshold.
EXAMPLE EMBODIMENT 26. The method of example embodiment 20, comprising:
detecting a context switch; and
in response to detecting the context switch, stopping identifying the new TLB entry as “sticky.”
EXAMPLE EMBODIMENT 27. The method of example embodiment 20, comprising:
performing an explicit invalidation of the new TLB entry; and
in response performing the invalidation of the new TLB entry, stopping identifying the new TLB entry as “sticky.”
EXAMPLE EMBODIMENT 28. The method of example embodiment 20, comprising:
starting a timer or maintaining a count relating to clock cycles; and
in response the timer expiring or the count exceeding a threshold, stopping identifying the new TLB entry as “sticky.”
EXAMPLE EMBODIMENT 29. The method of example embodiment 20, comprising:
selecting the new TLB entry for eviction;
instead of evicting the new TLB entry, stopping identifying the new TLB entry as “sticky.”
EXAMPLE EMBODIMENT 30. An integrated circuit device comprising a translation lookaside buffer (TLB) that comprises a configurable sub-TLB that stores a first entry comprising:
a virtual memory address field;
a physical memory address field corresponding to the virtual memory address field; and
a sticky field indicating whether the first entry is permitted to be evicted by a second entry based at least in part on a page size of the second entry in relation to the first entry.
EXAMPLE EMBODIMENT 31. The integrated circuit device of example embodiment 30, wherein the sticky field comprises a single bit.
EXAMPLE EMBODIMENT 32. The integrated circuit device of example embodiment 31, wherein the sticky field comprises multiple bits.
EXAMPLE EMBODIMENT 33. The integrated circuit device of example embodiment 32, wherein the sticky field indicates a degree to which the first entry is permitted to be evicted by a second entry associated with a different page size than the page size indicated by the page size field.
EXAMPLE EMBODIMENT 34. The integrated circuit device of example embodiment 30, wherein the first entry comprises a counter field configured to store a count related to a number of times that the first entry is used to store a virtual memory address or a physical memory address corresponding to a particular page size.
EXAMPLE EMBODIMENT 35. The integrated circuit device of example embodiment 30, wherein the sticky field comprises a plurality of bits that store a count, wherein a value of the count indicates either “sticky” or “not sticky”.
EXAMPLE EMBODIMENT 36. The integrated circuit device of example embodiment 30, wherein the first entry comprises a page size field that indicates a page size associated with the virtual memory address field and the physical memory address field.
While the embodiments set forth in the present disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the disclosure is not intended to be limited to the particular forms disclosed. The disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the following appended claims.
The techniques presented and claimed herein are referenced and applied to material objects and concrete examples of a practical nature that demonstrably improve the present technical field and, as such, are not abstract, intangible or purely theoretical. Further, if any claims appended to the end of this specification contain one or more elements designated as “means for [perform]ing [a function] . . . ” or “step for [perform]ing [a function] . . . ”, it is intended that such elements are to be interpreted under 35 U.S.C. 112(f). However, for any claims containing elements designated in any other manner, it is intended that such elements are not to be interpreted under 35 U.S.C. 112(f).
This invention was made with Government support under Agreement No. H98230A-13-D-0124 awarded by the Department of Defense. The Government has certain rights in this invention.
