Automatic flight control system with operatively monitored digital computer

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to automatic flight control systems and particularly to a dual channel fail operative computer controlled configuration.
2. Description of the Prior Art
Conventional fail passive automatic flight control systems normally require dual redundant channels with cross channel comparison monitors to shut the system down in the event of a failure in either channel. Conventional fail operative systems normally require a minimum of triply redundant channels with cross channel comparison monitors to detect a failure in one of the channels and to shut down the failed channel. It is a desideratum in the flight control art to retain either the fail passive or fail operative characteristic but to reduce the number of channels required therefor.
Flight control systems are known that utilize a digital computer in each of the channels of the system to process the input sensor data and provide surface control signals to the surface servo mechanisms in accordance therewith. In order to render each such channel fail passive and hence provide a dual channel fail operative system, such prior art automatic flight control systems have incorporated external test signal sources and test programs stored in memory for operating on the test signal to provide a predetermined output in accordance with the result of the test program. The predetermined output is then compared to a reference signal to detect failure. Such test programs utilize all of the instructions of the computer instruction repertoire and are repeated during each iteration of the operative program for the system. In sophisticated computers with large instruction repertoires, considerable time is utilized by the computer to execute the test program during which time the computer is executing operations that are not directly related to the primary function of controlling the aircraft. In addition to the time required to perform the test program, valuable memory space is occupied thereby and additional hardware such as a test signal source, a reference signal source and an associated comparator are required.
In such prior art systems, the operative programs normally comprise thousands or tens of thousands of instruction words where the execution of the program is under control of a program counter. A prior art test program can verify that the computer repertoire is functioning properly but cannot determine whether each instruction of the main flight program is free of malfunctions or whether the program counter can properly sequence through the operative program as well as the test program. Thus, a faulty stage of the program counter that is not utilized during the test program but is utilized during the operative program may not be detected by such a procedure, or a faulty memory bit in any one of the stored instructions of the operative program will not be detected, thereby precipitating a potentially dangerous system failure when the operative program is executed.
SUMMARY OF THE INVENTION
The above disadvantages of the prior art are obviated by segmenting the operative program into a plurality of tasks, each task program segment having a task completion indicium associated therewith. The program further includes a task completion test segment that determines whether or not all of the task completion indicia have been set after an iteration of the program. In steering through the operative program all of the instructions of the operative instruction repertoire of the computer are exercised by utilizing the instructions in the determination of the addresses that determine the proper program flow. Thus, a failure of a computer instruction causes the program to follow an abnormal path, therefore not setting all of the task completion indicia. When a failure occurs and the computer has at least a partial capability to continue operating, the task completion test program segment upon detecting an unset task completion indicium steers the program into a failure logic computation routine which, inter alia, stops the execution of the program. The program also includes a segment that generates a dynamically varying validity pattern in accordance with the continuous iterations of the program. The flight control system hardware includes a validity pattern detector that detects a static state or an incorrect dynamic state of the validity pattern indicating that the computer is no longer executing the program.
Thus it is appreciated that failures including catastrophic failures of the computer itself are detectable by this unique combination of software and hardware.
The flight control system of the present invention includes additional features such as dual data and program memory banks and some redundant computation execution to provide for a totally self-monitored automatic flight control system channel thereby providing single channel fail passive operation and dual channel fail operative capabilities.

BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic block diagram of one channel of a dual channel automatic flight control system;
FIG. 2 is a schematic block diagram showing in greater detail the digital computer of FIG. 1;
FIG. 3 is a flow chart of the master executive program stored in the program memory of the digital computer of FIG. 2;
FIG. 4 is a flow chart illustrating in greater detail a portion of FIG. 3;
FIG. 5 is a flow chart illustrating in greater detail another portion of FIG. 3; and
FIG. 6 is a partial schematic block diagram and flow chart illustrating a particular validity pattern generation routine.

DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIG. 1, a block schematic diagram of one channel, designated as channel 1, of a dual channel automatic flight control system is illustrated. The channel 1 illustrated in FIG. 1 is itself organized into two channels designated as channels A and B in a manner and for reasons to be later described. The second channel of the system, designated as channel 2, is identical to that illustrated in FIG. 1.
Channel 1 of the automatic flight control system includes identical sensor sets 10 and 11, the sensor set 10 being utilized for the channel A computations, and the sensor set 11 being used for the channel B computations in a manner to be described. Each sensor set 10 and 11 includes the conventional attitude, rate and acceleration sensors as well as other devices such as control wheel force sensors that are conventionally utilized in modern jet transports. These sensors may include such devices as directional and vertical gyroscopes, rate gyroscopes and accelerometers. Each of the sensor sets 10 and 11 may additionally include conventional radio guidance equipment such as VOR and ILS receivers and the like. The sensor sets 10 and 11 may also include inputs from the aircraft control surface position transducers as well as engine sensors and inputs from such devices as radio altimeters and the like. The sensor sets 10 and 11 each include the required complement of sensors that provide analog signals for use in controlling the aircraft. It will be appreciated that included within the sensor set blocks 10 and 11 are conventional analog signal processing circuits for preparing the sensor signals for entry into the system. Such processing circuits include demodulators for synchro data and the like.
The channel 1 of the automatic flight control system also includes a complement of digital sensors 12. The sensors 12 may include a conventional digital air data computer for providing such parameters as barometric altitude, total air temperature, and the like. The digital sensors 12 may also include other equipment such as a digital DME receiver.
The outputs of the analog sensor sets 10 and 11 are applied to a conventional multiplexer 13 via electrical conductor cables 14 and 15 respectively. The output of the multiplexer 13 is applied to a conventional analog-to-digital converter 16 whose output is in turn applied to another multiplexer 17.
The outputs of the digital sensors 12 are applied via an electrical conductor cable 20 to a digital data receiver 21 that includes buffers for entering the digital data into the system. The digital data receiver buffers 21 also receive digital data from channel 2 of the automatic flight control system via electrical conductor cable 22. The output of the digital data receiver buffers 21 are applied as an input to the multiplexer 17 via a cable 23.
The multiplexer 13 is of a conventional type that is designed to receive a plurality of analog inputs and to provide at its output a selected analog input. The multiplexer 17 is of conventional design of the type that accepts a plurality of digital inputs providing a selected digital input at its output.
The output of the multiplexer 17 is applied as an input to a digital computer 24. The digital computer 24 is of conventional architecture and is of the general purpose, medium scale design, a variety of which are commercially procurable and specifically constructed for real-time airborne analysis and control. Preferably, a series 1819 type computer commercially procurable from the Sperry Flight Systems Division of the Sperry Rand Corporation, may be utilized in implementing the system.
A data output 25 of the computer 24 is connected as an input to a conventional multiplexer 26 which selectively applies the digital signal on the computer output 25 to one of its digital outputs 27 and 30. The digital computer 24 provides control signals via an electrical conductor cable 31 to control the multiplexers 13, 17 and 26. An electrical conductor 31' from the cable 31 controls the multiplexer 13 to selectively provide one of its inputs to the analog-to-digital converter 16. Similarly, an electrical conductor 31" from the cable 31 controls the multiplexer 17 to selectively apply one of its inputs to the digital computer 24. Additionally, an electrical conductor 31'" from the cable 31 controls the multiplexer 26 to selectively apply the digital signals on the computer output 25 to one of the multiplexer outputs 27 or 30. Further details with regard to the internal arrangement of the digital computer 24 and its stored program will be discussed hereinbelow with regard to the ensuing figures.
The output 30 from the multiplexer 26 is connected to a plurality of digital-to-analog converters 32. The output 30 of the multiplexer 26 is an electrical conductor cable providing a pluraity of selectively controlled outputs from the multiplexer 26 to the respective digital-to-analog converters 32, selectively receiving data from the digital computer output 25 in accordance with control signals applied on the electrical conductor 31'".
The digital-to-analog converters 32 provide analog signals to the aircraft surface actuator control electronics 33 which, in turn, provide control signals to the surface control actuators 34. The control actuators 34 position the aerodynamic control surfaces of the aircraft, schematically represented at 35. The analog signals from the converters 32 to the actuator control electronics 33 are provided via electrical cable 36. It will be appreciated that the blocks 33, 34 and 35 are schematically representative of the conventional complete three-axis control apparatus for the aircraft control surfaces commonly utilized in modern jet transports. Such apparatus may be of the well known electromechanical or electrohydraulic variety. The control actuators 34 are schematically representative of the total aircraft surface actuator system which may, in modern jet transports, be of the redundant variety and thus receives an input at 37 from channel 2 (not shown) of the automatic flight control system. Such redundant actuator controls and electronics may, for example, be of the type described in Applicant's assignee's U.S. Pat. No. 3,504,248 issued Mar. 31, 1970.
The outputs from the digital-to-analog converters 32 on the cable 36 are also applied to conventional flight director instrumentation 40. The flight director instrumentation 40 provides visual commands to the pilot via attitude director instruments in a well known manner.
The outputs of the digital-to-analog converters 32 are also applied via an electrical conductor cable 41 as respective inputs to the multiplexer 13. This connection provides "end-around" feedback in a well known manner permitting the computer 24 to compare each D/A output from the block 32 against the associated signal from the computer output 25 thereby verifying the operability of each of the D/A elements in the block 32. The "end-around" feedback technique is well known in the automatic flight control system art and will be further discussed hereinbelow.
In accordance with the invention and in a manner to be later described in detail, the digital computer 24 stores a program that operates upon the signals from the sensors 10, 11 and 12 and provides output commands via the converters 32 to position the control surfaces 35 and to actuate the flight director 40. A real-time clock (not shown) within the computer 24, controls continuous repetitions of the stored program so as to effectively provide continuous control of the aircraft. When the system is functioning properly, the program stored in the computer 24 generates a validity pattern that varies dynamically in accordance with the continuous executions of the program. In a manner to be further described, the validity pattern is generated and provided at the computer output 25 and selected via the multiplexer 26 for application to one of the digital-to-analog converters 32. The output of this selected converter is applied via a lead 42 to a validity pattern detector 43. The validity pattern detector 43 is conventionally configured in a manner to be described to detect departures of the validity pattern from the computer 24 from that provided during normal operation of the system. When the computer 24 fails to provide the normal validity pattern indicative of proper system operation, the validity pattern detector 43 provides a failure signal via a lead 44 to engage/shutdown interlocks 45 of the system, the interlocks 45 being conventional and well known components of an automatic flight control system. When the validity pattern detector 43 provides a failure signal on the electrical conductor 44, which signal is indicative of a failure in channel 1 of the system, the interlocks 45 shut down channel 1 and continue operative control of the aircraft via channel 2.
The validity pattern signal on the conductor 42 is also applied as an input to the multiplexer 13 for the purpose of "end-around" checking of the associated D/A converter in the manner described above.
The outputs 27 from the multiplexer 26 are applied as inputs to a conventional digital data transmitter 46 which provides digital signals via an electrical conductor cable 47 to the displays of the system as well as to the other sub-systems of the aircraft. The signals on the cable 47 are also applied as inputs to the multiplexer 17 for "end-around" monitoring of the type described above. The digital data transmitter 46 also provides digital signals on an electrical conductor cable 50 to channel 2 (not shown) of the automatic flight control system, so that in conjunction with the signals received from channel 2 on the cable 22, the two autonomous channels 1 and 2 of the system may communicate with one another for such purposes as signal equalization and the like. It will be appreciated that although this interchannel communication is utilized, each channel is an autonomous fully self-monitored configuration capable of detecting internal channel failures and accordingly shutting down the channel.
Referring now to FIG. 2 in which like reference numerals indicate like components with respect to FIG. 1, the digital computer 24 is illustrated depicting the basic internal construction thereof. The digital computer 24 includes an input/output (I/O) control unit 51 that accepts the digital input signals from the multiplexer 17 of FIG. 1 and provides digital output signals on the output 25 to the multiplexer 26 of FIG. 1. The I/O control unit 51 also provides the multiplexer controlling signals on the cable 31. The computer 24 includes program storage 52, data storage 53 and an arithmetic unit 54 as well as a control unit 55, all interconnected for two-way communication therebetween via a bus 56. It will be appreciated that the internal configuration of the computer 24 is of a conventional nature and will therefore be only briefly described to facilitate an understanding of the invention.
The program memory 52 has stored therein the operative program for performing all of the functions required by channel 1 of the automatic flight control system illustrated in FIG. 1. The program is generally arranged in segments or routines as schematically illustrated by the blocks 60 through 80. The detailed structure and operation of the program stored in the program memory 52 will be described herein below with respect to subsequent figures.
The data memory or storage 53 is utilized for storing the constants used by the program as well as containing predetermined locations for the storage of the various types of data provided by the sensors 10, 11 and 12 of FIG. 1.
The control unit 55 includes a program counter 85 and a plurality of registers, one of which being designated at 86. The arithmetic unit 54 includes the circuits for performing the arithmetic and logical operations for the computer 24 and includes an accumulator (not shown) which may comprise a double length accumulator for performing double precision arithmetic operations as is well known in the computer art. The double length accumulator is designated as comprising upper accumulator (A.U.) and a lower accumulator (A.L.). In a manner well understood in the art, the program counter 85 sequentially fetches the instructions of the program from the program memory 52 and controls the computer 24 to perform the instructions, fetching data from the data memory 53 when required. The combination of the control unit 55 and the arithmetic unit 54 is often referred to as the central processor unit which is designated by reference numeral 55' of the digital computer 24. The arithmetic unit 54 is utilized under control of the control unit 55 to perform the conventional arithmetic and logical operations as required by the program. The I/O control unit 51 accepts data from the multiplexer 17 of FIG. 1 and provides data to the multiplexer 26 of FIG. 1 and additionally provides the timing control signals for the multiplexers 13, 17 and 26 under control of the control unit 55 as commanded by the sequence of program instructions stored in the program memory 52.
Although instruction repertoires generally vary from computer to computer, the computer 24 includes instructions for entering data from addressed locations in the data storage 53 into the accumulator of the arithmetic unit 54. Additionally, the computer 24 generally has a class of instructions for storing data in addressed locations in the data memory 53 from the accumulator in the arithmetic unit 54 as well as storing zero and constants. The computer 24 also includes a class of arithmetic instructions for performing arithmetic operations on data stored in addressed locations in the data memory 53 with respect to data stored in the accumulator of the arithmetic unit 54. Additionally, the computer 24 includes a class of address transfer instructions for causing the program counter 85 to transfer control to an addressed location in the program memory 52. These instructions generally are designed as "jump" instructions and are particularly used in transferring from a main program to a sub-routine stored elsewhere in memory. These "jump" instructions are of an unconditional nature; that is, when a particular "jump" instruction is encountered in the program, control always transfers to the new address.
In addition to the above described instructions, the computer 24 also has a class of conditional transfer instructions which cause the control to transfer to a specified address if certain conditions are met. For example, the conditional transfer instructions test the contents of the accumulator with regard to the upper and lower portions thereof to determine if the contents are equal to zero, not equal to zero, positive or negative and either jumps to the specified address or proceeds to the next sequential instruction in accordance with the result of the test. Conditional transfer instructions are also included for comparing the contents of an addressed location in the data memory 53 with the contents of the accumulator and performing the conditional jump upon equality, inequality, less than or equal to, or greater than with regard to the two quantities. The computer 24 additionally has the usual complement of logical instructions as well as shift instructions with regard to the accumulator. Additionally, the instruction repertoire of the computer 24 includes the usual complement of input/output instructions as well as interrupt instructions including an instruction to wait for an interrupt, i.e., to place the processor into a hold condition until the interrupt occurs. The computer 24 also includes a real time clock (not shown) which is used to generate real time interrupts for program timing.
Thus it will be appreciated that the computer 24 includes an instruction repertoire that provides it with the capability of inputting data from the automatic flight control system sensors, operating upon the data in accordance with the required control laws and outputting signals appropriate for positioning the control surfaces of the aircraft. It will furthermore be appreciated that to an extent the instruction repertoire is configured in accordance with the manner in which the automatic flight control system is utilized and the aircraft in which it is installed. To a greater extent the specific program stored in the program memory 52 will be determined by these conditions and the dynamic characteristics of the particular aircraft. It is specifically appreciated, however, that the operative program may be reiterated under control of the real time clock by utilizing the "wait for interrupt" instruction in combination with the real time clock. In a practical jet transport control environment the operative program may be repeated every fifty milliseconds to effectively provide continuous control of the aircraft.
As previously described, the program flow is directed through the variety of tasks to be performed as generally indicated by the blocks 60 through 76 stored in the program memory 52. As the program is executed, program jumps are performed to the various sub-routines 77 through 80 during which transfers the instructions of the computer repertoire may be utilized, for the purpose of exercising and hence testing them, in establishing the addresses at which the sub-routines are located. Therefore, if a failure should occur with regard to those portions of the computer 24 associated with the execution of the instruction, control will transfer to an abnormal location and the program flow will continue along an abnormal path. For example, a jump instruction may be utilized in conjunction with an arithmetic instruction that manipulates the desired address so that in effect the program "gets lost" if the arithmetic instruction utilized should fail. This concept will be further clarified with regard to the discussion of the ensuing figures.
Before discussing the ensuing figures, however, the following provisions within the data storage memory 53 should be appreciated. As previously discussed, the operative program is structured as a plurality of tasks to be performed. Accordingly, one or more words in the storage 53 are reserved as task list words, each bit thereof representing a particular one of the tasks. Correspondingly, another group of words is reserved in the memory 53 to provide task completion indicia wherein each bit of the task completion words represents completion or non-completion of the associated task. The bit positions of the task list words correspond to the bit positions of the associated bit completion words for convenience.
Referring now to FIG. 3 with continued reference to FIGS. 1 and 2, the master executive flow chart for the programs stored in the program memory 52 of FIG. 2 is illustrated. Block 90 of the master executive flow chart is selected as the start thereof in accordance with the occurrence of the real time clock interrupt. The real time clock causes an interrupt to occur at the end of a predetermined interval of time typically 50 milliseconds for modern jet transport aircraft. The interrupt occurs during normal operation of the system independently of what point in the program, i.e., position on the master executive flow chart it occurs. When the real time clock interrupt occurs, the control unit 55 of the computer 24 transfers control to a predetermined location in the program memory 52 which is schematically illustrated at 60.
The next block 91 on the master executive flow chart indicates performance of task s.sub.1 which initiates the analog-to-digital inputs. The program segment corresponding to the flow chart block 91 is schematically represented at 65 in the program memory 52. Conveniently the real time interrupt entrance 60 in the program memory 52 may be selected as the location of the first instruction for the task s.sub.1 program segment 65. Alternatively the real time interrupt entrance location may contain a jump instruction which would transfer control to the first location of the task s.sub.1 program segment 65. In so transferring the address may be manipulated by utilizing, for example, arithmetic or logical instructions from the instruction repertoire so that in the event of failure of the so utilized instructions, control will transfer to an erroneous location and hence the program flow would follow an abnormal path.
The task s.sub.1 program segment 65 as indicated by the flow chart block 91 initiates the acquisition of data from the sensors 10, 11 and 12 of FIG. 1. In the program segment 65, instructions are utilized to cause the computer 24 to provide signals on the cable 31 that control the multiplexers 13 and 17 to transfer the data from the appropriate sensor inputs to the multiplexers into the computer 24. This data is transmitted through the I/O control unit 51 along the cable 56 into the data storage 53. Since preferably the computer 24 may be configured as a direct memory access machine, the signals on the cable 31 merely initiate the transferring of the data which will thereafter occur on a "cycle steal" basis as the program continues through the flow chart. This is a conventional and well understood technique in the digital computer art. The A/D inputs are initiated at the block 91 and the timing of the system is such that the transferring of the data will be complete at the point in the computations where it will be utilized and the data will be as recent as possible.
After initiating the A/D inputs in accordance with the block 91 of the master executive flow chart, the program counter 85 (FIG. 2) will sequence control to the next following instructions which will provide a routine for setting the task s.sub.1 completion bit to a binary ONE as indicated in block 92 of the flow chart. The task completion bits are designated with capital letters and sub numerals corresponding to the associated task designations. It will be appreciated that the actual program steps utilized in performing, for example, the functions of the block 92 may readily be prepared as a routine matter by normally skilled digital computer programmers and will, of course, depend on the specific instruction repertoire and programming language of the machine utilized. It will further be appreciated that the present description is provided with regard to a particular iteration of the master executive program. During the previous iteration the task list bits were established in a manner to be later described and the task completion bits were all set to binary ZERO. It will be appreciated from the foregoing that if in transferring between the blocks 90 and 91 of the master executive flow chart, instructions of the repertoire had been utilized in establishing the transfer addressing and a failure had occurred in the so utilized instructions that the program would have followed an abnormal path and would not have arrived at the block 92 in order to set the task completion bit S.sub.1. If during the previous iteration of the program, other task completion bits had not been set, this would then be detected in the next portion of the program to be described.
In the preferred embodiment of the invention, the tasks to be performed are sub-divided into three categories. One category includes all of the tasks that are done on a single channel basis, i.e., related to the entire channel 1 or the entire channel 2. Another category includes all of those tasks done on a dual channel basis related to the channel A portion of channel 1, for example, and the other category includes all of the dual channel tasks related to channel B.
The blocks 93 through 98 of the master executive flow chart of FIG. 3 indicate the manner in which the program determines that all of the assigned tasks were completed on the previous iteration through the program. When the program segment indicated by block 92 of the master executive flow chart is completed, the program counter 85 of FIG. 2 causes control to be transferred to the program segment related to the block 93 of the flow chart. In the block 93 the single channel tasks are tested for completion by taking the EXCLUSIVE OR logical function between the corresponding bits of the task list words and those of the task completion bit words. For example, the single bit task s.sub.1 as performed in accordance with the block 91 in the flow chart is logically combined by means of the EXCLUSIVE OR instruction with the task completion bit S.sub.1 to provide a binary ONE if the bits are the same and a binary ZERO if the bits are different. In this manner all of the single channel tasks s.sub.1 . . . s.sub.m are tested for completion and a new word M.sub.S is formed. If all of the bits of the M.sub.S word are binary ONE, then all of the single channel tasks were performed during the previous iteration of the program. If, however, there is a single ZERO in the word, then at least one task was not performed during the previous iteration. The manner in which the non-completion of all of the single channel tasks is detected and the nature of the single channel tasks will be further described with regard to FIGS. 3, 4 and 5.
After establishing the M.sub.S word, the control unit 55 transfers to the next sequential instruction under control of the program counter 85 to enter the program segment corresponding to the block 94 on the master executive flow chart. In this program segment the M.sub.A word is computed wherein the channel A task list is logically compared to the channel A task completion bits in the manner described above with regard to the block 93. After completing the establishment of the M.sub.A word, control transfers to the program segment associated with the block 95 to establish the M.sub.B word in the manner described above with respect to the blocks 93 and 94 for the channel B tasks.
Upon completion of the block 95 instructions, control is transferred to the block 96 in which a routine to be later described in greater detail with respect to FIG. 4 is performed to determine if all of the bits in the M.sub.A word have been set to binary ONE. If, in fact, the M.sub.A word has been properly set, indicating completion of all of the channel A tasks, then control is transferred to the block 97 via the program branch labeled YES, in which block the M.sub.B word is tested in a manner similar to the tests performed in the block 96. If again the M.sub.B word is properly set, indicating completion of the channel B tasks, then control is transferred to the block 98 via the program branch labeled YES. Similarly within the block 98 comparable tests are performed on the M.sub.S word as were performed with regard to the previous blocks 96 and 97 and if again the M.sub.S word is properly set, indicating completion of all of the single channel tasks, then the program continues along the associated branch labeled YES.
If, however, a task is not completed, program control will transfer from the appropriate one of the test blocks 96-98 along the appropriate NO program branch into a failure logic routine 102 which leads to a computer step instruction as indicated in block 103. The programming stored in the program memory 52 of the computer 24 (FIG. 2) for the blocks 93 through 98 is schematically indicated as the program segment 61. The failure logic computations as indicated by the flow chart blocks 102 and 103, are illustrated schematically as stored in the program memory 52 at the segment 62. The specific programming for the failure logic computations will depend on the specific machine utilized and the software is readily derivable by normally skilled computer programmers to attempt to have the computer come to an orderly halt with regard to the automatic flight control system that it is controlling. Routines are utilized within the failure logic computation block 102 to transfer control to the properly operating channel and to provide instrument panel display indications informing the pilot that one of the two automatic flight control system channels 1 and 2 has failed and that it has been shut down. Such failure indication procedures and apparatus are well known in the flight control art and will not be further described herein for brevity.
If after completing the tests of the flow chart blocks 96, 97 and 98, program control arrives at the branch labeled YES from the block 98, this signifies that the system operated properly during the preceding iteration of the program and control is transferred to a block 104. In this block all of the task lists, task completion words and task completion test words are reset in preparation for the next iteration of the program after which the program control sequentially enters the task s.sub.2 program block 66 stored in the program memory 52 to perform the instructions stored therein in accordance with flow chart block 105.
When the program control arrives at the block 105 all of the A/D inputs initiated at the block 91 will have been completed and stored in a predetermined buffer portion of the data memory 53 (FIG. 2). The programming instructions associated with the block 105 of the flow chart and stored at 66 in the program memory 52 will sequentially extract the data words from the buffer portion of the data memory 53 and enter these words into predetermined locations in memory after being identified as to what the data signifies. For example, the computer 24 controls the multiplexers 13 and 17 of FIG. 1 to enter the data into the buffer storage in an orderly manner so that when the block 105 instructions are executed, the data may be transferred to the appropriate memory locations. For example, the first word may be reserved for pitch rate, the second word for pitch attitude, etc., which quantities will all have assigned locations in the data storage 53 so that they may be later extracted to perform computations thereon. The block 105 also includes instructions for scaling the data so as to have the proper scaling for the computations, i.e., bits per degrees, etc.
It will be appreciated that the block 105 is in itself a sub-executive routine in that control frequently branches to one or more of the numerous sub-routines 77 through 80 (FIG. 2) so as to perform the required computations. After executing a sub-routine, control returns to the point in the program from which the branch took place to subsequently continue the program under control of the program counter 85. During such branching points in the program the numerous instructions of the computer instruction repertoire are utilized in establishing the branching addresses such that should an instruction fail, the program will not transfer to the proper address but will follow an abnormal path and thus not complete the assigned tasks. When the assigned tasks are not completed, the associated task completion bits are not set and the program enters the failure logic block 102 as described above to bring the computer to an orderly halt providing the computer has the residual capability to so perform. An example of such programming to cause the program flow to "get lost" and hence indicate failure will be later described.
If the processing required by the block 105 is properly performed, the program counter 85 (FIG. 2) causes control to sequentially enter block 106 of the master executive flow chart wherein the associated task completion bit S.sub.2 is set in a manner similar to that described above with regard to the block 92 of the flow chart.
After performing the instructions associated with the block 106, control sequentially enters the program segment 67 in the program memory 52 (FIG. 2) to perform the task s.sub.3 input monitoring computation functions indicated by block 107 of the flow chart. The task s.sub.3 program segment 67 contains instructions for comparing the outputs of independent identical sensors of, for example, the sensor sets A and B indicated as blocks 10 and 11 in FIG. 1, to determine that they compare to within a predetermined tolerance. These sensor comparison computations are well known functions normally performed in conventional fail-safe/fail-operational automatic flight control systems.
As previously discussed with regard to the block 105, numerous branches are taken to the sub-routines 77-80 (FIG. 2) to perform standard calculations such as signal filtering and the like. When branching to a sub-routine from a particular point of the program segment represented by the block 107, a return address is stored in a conventional manner at the end of the sub-routine to which control is transferred so that control may return to the proper point in the program. When instructions of the computer repertoire are exercised in the branching and fail, the return address is never encountered and the program follows an abnormal flow thereby never arriving at the task completion point where the associated task completion bit is set. If, however, the program properly completes the program segment 67 (FIG. 2) associated with the task s.sub.3, then the program counter 85 (FIG. 2) sequentially causes control to enter block 108 of the master executive flow chart wherein the associated task completion bit S.sub.3 is set in the manner previously described with regard to the block 106.
During proper operation of the system, the program control will sequentially flow through blocks 111, 112, 113 and 114 to perform the tasks s.sub.4 and s.sub.5 setting the task completion bits S.sub.4 and S.sub.5 upon proper completion of these tasks. It will be appreciated that respective portions of the program memory 52 (FIG. 2) will contain the instructions for performing the functions required by these blocks 111-114.
In block 111, all of the processing required for generation of serial digital data for data reception or transmission from one digital device to another and for cross channel communication with the computer of channel 2 of the system is performed. It will be appreciated that the I/O control block 51 (FIG. 2) via the cable 31 will control the multiplexers 17 and 26 so as to receive data from the digital data receiver 21 (FIG. 1) and transmit data through the digital data transmitter 46 (FIG. 1). Additionally, the program instructions associated with the block 111 of the master executive flow chart will direct the data in and out of the data memory 53 utilizing the arithmetic unit 54, all under control of the control unit 55 to perform the necessary data transformations for the required data reception and transmission. It will be appreciated that the specific processing will depend on the detailed specific instrumentation of a particular automatic flight control system for a particular aircraft. Preparation of software for such program segments is a routine matter for normally skilled programmers and will not be further described herein for brevity.
The program segment associated with the block 113 provides data end-around and monitoring computations of a type that are well known in the automatic flight control system art. As previously described with regard to FIG. 1, each of the digital-to-analog converter outputs on the cable 36 is applied to the multiplexer 13 so that the conversion interfaces 16 and 32 as well as the input/output functions performed by the computer 24 may be tested for proper operation. Additionally, as previously described with regard to FIG. 1, an end-around connection is made from the digital data transmitter 46 to the input of the multiplexer 17 to check the operational integrity thereof in a well known manner. The computations and comparisons required within the computer 24 to provide these functions are specifically related to the particular sensors and interfaces utilized and are of a routine nature so that the specific detailed software for implementing the block 113 may be readily provided by a normally skilled computer programmer.
If the tasks s.sub.4 and s.sub.5 of the respective blocks 111 and 113 are properly performed, then the associated task completion bits S.sub.4 and S.sub.5 of the respective blocks 112 and 114 will be set in a manner similar to that described above with regard to the block 106.
As was previously discussed, the automatic flight control system computations are performed twice utilizing separate memory banks to store the separate, although identical, software for the computations and with separate memory banks utilized for the storage of the data associated therewith. These independent data banks and computations as well as independent and identical sensor sets have been designated as channel A and channel B of channel 1 of the dual redundant automatic flight control system. The dual sensor sets were indicated at 10 and 11 of FIG. 1 and the dual program memory banks are indicated schematically by the blocks 69-72 and the blocks 73-76 respectively. The duality of computation and of memory banks provides a complete verification of memory operability which will detect the failure of even a single bit of memory. The dual memory banks may be skewed with respect to each other, i.e., the address locations of identical programming being offset from one another by a constant number of locations, thereby avoiding common failure modes in the read/write circuitry of the computer which might have caused a symmetrical or identical read or write error in both channels A and B.
Referring again to FIG. 3, blocks 115 and 116 designate all of the channel A and channel B automatic flight control system computational tasks respectively, the channel A tasks being denoted as tasks a.sub.1, a.sub.2, . . . a.sub.n and the channel B tasks being designated as tasks b.sub.1, b.sub.2, . . . b.sub.n. It is appreciated that these identical channel A and channel B computations are performed sequentially as indicated by the sequential flow from the block 115 to the block 116. The channel A computations which are identical to the channel B computations will be described in greater detail herein below with regard to FIG. 5.
After performance of the channel A and channel B computation tasks, the control unit 55 (FIG. 2) transfers control to the task s.sub.6 block 117 of the master executive flow chart of FIG. 3. In this block a program segment stored in the program memory 52 (FIG. 2) compares the results of the channel A and channel B computations to vertify that they are identical. If identity within a predetermined tolerance is established, program control enters block 120 where the S.sub.6 task completion bit is set in the manner described above. If a discrepancy should be detected between the output computations from the blocks 115 and 116, the block 120 may be by-passed by a simple programming routine so that the task completion bit S.sub.6 will remain unset or control may be transferred to the failure logic computations of block 102.
After completion of the block 120 computations, control transfers to the block 121 to perform task s.sub.7 wherein the computer 24 controls the multiplexer 26 to provide the digital output data from the results of the channel A and channel B computations to the digital-to-analog converters 32 which in turn provide the required analog signals to the system as discussed above with regard to FIG. 1. The program segment stored in the program memory 52 (FIG. 2) associated with the flow chart block 121 performs scaling and data packing computations and, in addition, provides the system discrete outputs. The output transmission of the data is initiated by the computations in the block 121 which data transmission continues simultaneously with further processing by the computer 24 in a manner well known in the art. After successfully performing the functions required by the block 121, control transfers to block 122 wherein the associated task completion bit S.sub.7 is set in the manner previously described.
After completion of the computations of the block 122, the program transfers control to the task s.sub.8 block 123 wherein servo modeling and monitoring computations are performed to assure that the aircraft surface servos are performing in the proper manner to within a specified tolerance. Since the specific mathematical models utilized to simulate the servo operation depend on the specific servo mechanisms of the aircraft and such modeling and monitoring is well known in the automatic flight control system art, further details thereof will not be provided herein for brevity. It is appreciated, however, that in performing the associated program segment stored in the program memory 52 (FIG. 2), transfers and returns to and from the sub-routines 77-80 will be required during which transfers the instructions of the computer repertoire may be exercised in the manner described above. If the task s.sub.8 is properly performed, program control transfers to block 124 in accordance with which the associated task completion bit S.sub.8 is set in the manner described above.
After completion of the computations associated with the block 124, the master executive program transfers control to a block 125 in which the remainder of the single channel tasks s.sub.9, s.sub.10, . . . s.sub.m are performed. As previoulsy described, the programming segments associated with these single channel tasks s.sub.1 through s.sub.m are stored within the program memory 52 (FIG. 2) as schematically represented at 65 through 68. The block 125 represents remaining tasks to be performed by the executive program such as scanning the input discretes for information content and processing same for mode selection, mode progression, failure indication and the like. The signals for the aircraft displays are generated and stored in preparation for the repetition of the block 111 wherein the digital data output is provided during the next reiteration of the master executive program.
After all of the single channel tasks are performed and the associated task completion bits set in accordance with the block 125, program control transfers to a block 126 wherein all of the constants utilized for the various single channel computations are formed into a check sum and compared to a reference sum to detect memory failures. After the test in block 126 is performed, control is transferred to a block 127 to wait for the next occurring real time interrupt. Control transfers to the location in the program memory 52 schematically represented at 64 which contains the appropriate WAIT FOR INTERRUPT instruction. The computer 24 processor then stops and waits for the next occurrence of the real time clock interrupt at which time control is transferred to the program memory location 60 in accordance with the start block 90 of the master executive flow chart. In this manner, continuous reiteration of the executive program occurs resulting in effectively continuous control of the aircraft.
It will be appreciated from the foregoing that the tasks are performed sequentially in the order illustrated in FIG. 3. The program segments 60 through 80 schematically illustrated in the program memory 52 of FIG. 2, corresponding to the blocks of FIG. 3, are arranged in the drawing for convenience of illustration and it is appreciated that the order in which the program segments appear in the drawing is not necessarily the order in which the program segments are stored in the physical memory.
The master executive flow chart illustrated in FIG. 3 is designed to provide orderly control of a particular type of modern jet transport. It will be appreciated that other executive program arrangements may be utilized to practice the invention as herein described. The foregoing description was explained in terms of performing each of the blocks of FIG. 3 during each iteration of the program. In a practical system it is not necessary to perform all of the blocks during each iteration. For example, some of the tasks may need only be performed every other iteration or every third iteration. Thus additional programming would conveniently be included between the blocks 92 and 93 for so controlling the executive program flow. This additional programming would set the bits in the task list words corresponding to those tasks that are to be performed during the current iteration. It will be appreciated that the logic performed in the blocks 93-95 will still yield the proper result for the M.sub.S, M.sub.A and M.sub.B words since the unset task list bits will correspond to unset task completion bits thereby yielding the required binary ONE.
Referring now to FIG. 4 in which like reference numerals refer to like blocks with regard to FIG. 3, further details of the blocks 96, 97 and 98 are illustrated. As discussed above, these blocks of the master executive flow chart are utilized to verify that the computer 24 has accomplished all of those tasks assigned to it by the software. The manner in which the task completion test is performed verifies that all of the conditional transfer or program branching instructions of the computer are operating properly. As indicated by the legends, the logical complementing instruction is also utilized and the upper and lower accumulator functional integrity is also tested in accordance with the legends "AU" and "AL" representing the upper and lower accumulator portions (not shown) of the arithmetic unit 54 (FIG. 2). As explained above, the conditional transfer instructions cause program branching in accordance with the contents of the upper and lower accumulator being equal to or not equal to zero as well as being positive or negative. Additionally, the conditional transfer instructions operate on the contents of an addressed word being equal to, not equal to, less than or equal to, or greater than the lower accumulator. Each of the conditional transfer instructions is exercised for both the branch and don't branch conditions such that when the flow chart of FIG. 4 is completed, all of the conditional transfer instructions are verified as operating properly and all of the assigned tasks are verified as having been accomplished. This repertoire exercise is required because devices such as flip-flops within the computer 24 are set as a result of a compare instruction and the state of the flip-flop determines the direction of the branch. If a flip-flop associated with the logical transfer instructions or the associated logic should fail, the failure may result in an incorrect branch command to the program. That is, if the task completion verification words M.sub.A, M.sub.B and M.sub.S are compared to the criteria as indicated by the legends in the blocks of FIG. 4 and a failure were to result, the branch instructions should direct the program to the failure routine address. However, if a computer hardware failure associated with the compare state had occurred, a branch in a wrong direction might occur indicating an incorrect valid state. For this reason all of the branching instructions are exercised in both directions in order to reach a final task completion validation point in the program at the block 104. It will be appreciated that the flow chart of FIG. 4 would be varied in accordance with the specific conditional transfer instruction repertoire of the particular computer utilized. It will further be appreciated that the various words M.sub.A, M.sub.B and M.sub.S, as well as their complements must be transferred to the upper and lower accumulators as indicated by the legends by suitable data enter instructions from the computer repertoire.
The flow chart of FIG. 4 is comprised of blocks 130 through 154 in addition to the blocks 102, 103 and 104 which are identical to the similarly numbered blocks from FIG. 3. It will be appreciated that the block 96 of FIG. 3 is comprised of the blocks 130 through 141 of FIG. 4; that the block 97 of FIG. 3 is comprised of the blocks 142 through 152 of FIG. 4 and that the block 98 of FIG. 3 is comprised of the blocks 153 and 154 of FIG. 4. The block 130 is entered from the block 95 of FIG. 3 and after complementing the M.sub.A word and transferring the complement to the upper accumulator, the program utilizes the conditional transfer instruction to jump if the contents of the upper accumulator is equal to zero. Since under normal operation all of the bits of the M.sub.A word (as well as of the M.sub.B and M.sub.S words) should be equal to ONE, the complement thereof should be equal to zero and control should jump to the next block 131. If, however, a failure should occur and the complement of M.sub.A is not equal to zero, then the jump will not occur and the subsequent instructions will transfer control to the failure logic computations 102. In a similar manner as illustrated, all of the conditional transfer instructions of the computer 24 are tested for proper operation.
It will be appreciated that in the specific preferred embodiment of the automatic flight control system, when the computer performs the programming associated with FIG. 4 all of the tasks are established and must be accomplished each computation cycle. Thus each task list word is a fixed constant of all ONES designating the tasks to be completed.
Specific attention is directed toward blocks 147 and 154 in which zero is added to the M word. Since the specific computer utilized in the preferred embodiment of the invention is a one's complement machine, the all ONES condition of the M word is equivalent to -0 and the addition of +0 to -0 results in +0. The particular logical instructions of the machine only recognize +0. Hence the requirement for the blocks 147 and 154 of FIG. 4.
As previously described, blocks 115 and 116 of FIG. 3 depict the channel A and channel B computations of the system. Referring now to FIG. 5, a detailed flow chart of the channel A computations is illustrated, the channel B computations being identical thereto. The channel A executive computations comprise that portion of the software system that actually performs the automatic flight control system computations. Control is transferred from the block 114 of FIG. 3 to a task a.sub.1 block 160 where the associated program segment is illustrated as schematically stored at 69 in the program memory 52 (FIG. 2). This program segment transfers the data that was placed in predetermined locations during performance of the block 105 of FIG. 3 as explained above, to the computation portion of the software system wherein the data is conditioned such as by utilizing filtering routines and is equalized with regard to the comparable computations from the channel 2 portion of the automatic flight control system. As described above, numerous transfers to and from the sub-routine 77-80 to provide the conditioning and equalization functions may be performed utilizing the instructions of the computer repertoire to manipulate the transfer addresses thereby assuring that if these so utilized instructions fail to operate properly the program will enter an abnormal path and not set the associated task completion bit. During normal operation after the functions required in the block 160 are performed, control transfers to a block 161 in which a task completion bit A.sub.1 is set corresponding to the completion of the task a.sub.1. The task completion bit setting procedure is similar to that described above with regard to FIG. 3.
After performing the instructions associated with the block 161, the control unit 55 (FIG. 2) transfer control to a task a.sub.2 block 162 with the associated program segment schematically illustrated as stored at 70 in the program memory 52 (FIG. 2). The state estimate computations combine the data as processed above utilizing known filtering techniques in order to obtain the best state estimate to be utilized in the ensuing control law and other flight control and guidance computations. The state estimate filtering is well known in the automatic flight control system art, an example of which being conventional complementary filtering. After the state estimate computations are performed, control is transferred to a block 163 in which the associated task completion bit A.sub.2 is set.
With the data processed and the best estimates thereof computed, the software system is then ready to perform the computations for controlling and guiding the aircraft. As is well known in the automatic flight control system art, armed modes and engaged modes are utilized in the various flight regimes of the aircraft. Thus for each of the roll, pitch and yaw axes as well as the throttle modes and the like, armed and engaged computations are selectively performed in accordance with the existing conditions of the aircraft and the modes engaged by the automatic flight control system mode selector, these modes include the appropriate control law computations for effecting the desired aircraft control.
After the computations required by the block 163 of FIG. 5 are performed, control is transferred to an armed roll mode status block 164. In this block a variable i is set to a number from l to k in accordance with the roll armed computations to be performed. The variable i is set in accordance with the automatic flight control system mode selector in conjunction with the extant condition of the aircraft. The program selects one of the many paths to the appropriate armed roll mode computations in accordance with the task selection code assigned to the variable i. Program control transfers from block 164 to a block 165 from which the appropriate roll arm computation sub-routine is entered. The roll arm computation sub-routines are indicated at 166, 167 and 170 on the channel A computations executive flow chart. At the completion of each of the roll arm computation sub-routines, a variable j is set to equal the value of the variable i which controlled entry into the particular roll arm computation sub-routine. These blocks are indicated at 171, 172 and 173 on the channel A computations executive flow chart.
Irrespective of the path taken through the roll arm computations, control returns to a block 174 in which the input variable i and the output variable j are compared for validity. The comparison is performed by dividing i by j which additionally tests the divide instruction of the computer instruction repertoire. If the test of the block 174 fails the next block 175 is by-passed and control transfers to a block 176. If, however, under normal operating conditions of the system, the test is successful, control passes to the block 175 wherein the task completion bit A.sub.3 is set in accordance with the successful completion of the task a.sub.3 which related to the roll armed computations. A similar procedure is performed with regard to the block 176 in which the roll engaged mode status variable i is set to a number from 1 through L in order that upon entering block 177 control may be transferred through the appropriate roll engaged computation sub-routine which sub-routines are indicated at 180, 181 and 182. In a manner similar to that described above with regard to the blocks 171-173, blocks 183, 184 and 185 set an output variable j as indicated by the legend in accordance with the roll engaged computation sub-routine performed. Irrespective of the path chosen through the roll engaged computations, control arrives at a block 186 wherein the logic determines that the correct task was performed by checking that the task completion code j equals the task selection code i. In the block 186 this test is performed so as to check the operability of the multiply instruction of the instruction repertoire of the computer. In a manner similar to that described above with regard to the blocks 174 and 175, failure of the test in the block 186 causes the task completion block 187 to be by-passed whereas proper operation causes the task completion bit A.sub.4 to be set.
After control passes through the blocks 186 and 187, a block 190 is entered which represents a similar flow chart programming arrangement for the remaining modes of the system such as the pitch modes, the throttle modes, the yaw modes and the like.
Control passes from the block 190 to the block 191 in which all of the inner loop computations and the like for the automatic flight control system are performed. The inner loop computations relate to the basic attitude stabilization of the aircraft as opposed to the guidance or command computations performed as described above. The inner loop computations transfer to and from sub-routines for the basic roll, pitch and yaw stabilization equations for the aircraft to control and hold existing attitudes in accordance with angular displacement and rate signals filtered and combined in accordance with the appropriate equations to provide the control signals to the control surfaces of the aircraft. Each of the tasks represented within the block 191 has an associated task completion bit which is set in the manner described above.
After the computations required by the block 191 are performed, the program counter 85 of the control unit 55 (FIG. 2) transfers control to a block 192 in which a multi-level validity pattern signal is generated. It is essential that the pattern be dynamically varying and is generated by changing the state of the output signal on a lead 193 for each iteration of the executive program. Thus should the computer stop functioning either by entering the failure logic computations block 102 of FIG. 3, or if the computer should fail catastrophically by being unable to execute instructions, the signal on the lead 193 would remain in a static state. This static condition may be detected by the validity pattern detector 43 as described above with regard to FIG. 1. It will be appreciated that the dynamically varying validity pattern may be varied in amplitude, in pulse width or both, in order to provide the failure detection function described above. Conveniently, however, the preferred embodiment of the invention is described in terms of varying the amplitude of the pattern.
A specific example of the generation of the validity pattern signal is illustrated in FIG. 6. Referring now to FIG. 6, a computer word designated as D is utilized to provide a square wave of amplitude "A" and width "T" having a period equal to 2T where T is the iteration time of the program. Control is transferred from the block 191 of FIG. 5 into a block 200 which examines the state of the D variable. If D is equal to 1 during a particular iteration, D is set to 0 in a block 201. If, however, during an iteration, D is equal to 0, then D is set to the opposite state 1 in a block 202. The final state of the D variable during the iteration is transmitted to the output in a block 203 to the lead 193 which transmits the D variable to the hardware portion of the system as illustrated in FIG. 1. It is thus appreciated that as the program is reiterated, the amplitude of the D variable is changed from 0 to 1 and when this varying binary state is converted by the associated digital-to-analog converter in the block 32 (FIG. 1), whose output is applied to the lead 42 (FIG. 1), then a squarewave of amplitude A and duration T is generated. As previously stated, if the computer should stop continuously executing the executive program, the signal on the lead 193 would remain in a static state indicative of the failure. The validity pattern signal is applied to a square wave monitor 204 which in this particular example is representative of the validity pattern detector 43 of FIG. 1. The square wave monitor is of conventional design constructed from amplitude discriminator circuits, one-shot multivibrator timers and simple logic networks to detect that the square wave signal is no longer being provided and a static signal indicative of failure is instead being provided by the computer 24 (FIG. 1).
It will be appreciated that in a failure mode of the computer 24, the validity pattern signal may not necessarily fail in a static state but may fail by being other than a precisely defined dynamically varying signal. The computer 24 may fail such that the validity pattern will exhibit an incorrect dynamic state such as one resembling noise.
In accordance with fail-safe and fail-operative techniques, two such monitors 204 are utilized so that a valid signal will be provided only when each of the monitors is generating a valid signal output.
It will be appreciated that in the operation of the system of FIG. 1 in accordance with the master executive program, that the block 125 of FIG. 3 has access to the results of the armed and engaged computations of FIG. 5 and in combination with the mode selector of the automatic flight control system performs the mode progression and regression functions for the system. When the automatic flight control system is in a disengaged mode one of the possible paths for the armed and engaged computations of FIG. 5 is one in which no operations are performed. For example, with regard to the block 176 of FIG. 5, when the automatic flight control system is disengaged, i is set equal to 1 indicating no roll mode. Similarly, when the automatic flight control system is engaged, i may be set equal to 2 for the localizer capture mode and i may be set equal to 3 for the heading hold mode, etc.
From the foregoing description of the preferred embodiment of the invention, it will be appreciated that the automatic flight control system of FIG. 1 is controlled by the real time clock within the computer 24 to continuously execute the master executive program of FIG. 3 thereby continuously transmitting the sensor signals from the blocks 10, 11 and 12 to the input, operating upon the signals in accordance with the computations executive flow chart of FIG. 5 and providing the signals to the surface control actuators of the aircraft via the digital-to-analog converters of the system. The program is arranged in tasks to be performed with associated task completion indicia that are set upon successful completion of the tasks. The instructions of the computer instruction repertoire that are utilized in the programming for the aircraft are interspersed throughout the program to control the branching addressing so as to detect a failure in the instruction repertoire by causing the program flow to follow an abnormal path thereby not setting all of the task completion indicia. Additionally, the program includes a dynamic validity pattern generator program segment which provides a normal output signal only when the computer is continuously executing the master executive program. When the computer stops executing the program either due to entry into the failure logic computations 102 or because of catastrophic failure of the computer 24, an external hardware monitor 43 (204 on FIG. 6) detects the abnormal validity pattern signal shutting down the failed channel.
Examples were given above of the unique programming technique for causing the program to follow an abnormal path, i.e., to "get lost". Further examples of such failure detecting operative programming will now be described specially with regard to the above referenced 1819 computer, it being appreciated that similar techniques may be readily applied to automatic flight control systems utilizing other computer designs. The examples are given with regard to the control law computations performed in accordance with the blocks 115 and 116 of FIG. 3 as shown in greater detail in FIG. 5.
As generally described above, the computer 24 utilizes dual memory banks designated as bank 1 and bank 2 wherein the locations in each bank have octal address designations. For example, address 2-0662 designates locations 0662 in memory bank 2. In the specific computer, the program counter 85 of FIG. 2 is designated by the mnemonic P and the index registers of the computer 24 are generally designated mnemonically as B. Generally an instruction word of the computer 24 has an instruction portion (Op code) and an operand portion. The instruction portion and operand portion may be designated octally to provide the actual binary designation stored in memory as well as mnemonically as is conventional in assembly language programming. The operand portion of the instruction word is designated mnemonically as Y which generally indicates an address in memory, the contents of that address location being designated as (Y). Parentheses utilized in this nature will indicate the contents of the associated element. For example, (P) indicates the contents of the program counter 85.
In the examples to be given, the following functions will be performed. Within the channel A or channel B computations, blocks 115 and 116 respectively of the master executive program of FIG. 3, a control law will be utilized which computes a pitch increment .DELTA. .theta. which is a function of bank angle .phi., weight W, flap deflection .delta..sub.F and .intg.(V/V)dt. A sub-routine such as schematically represented at 77-80 in FIG. 2 called THETLC (Theta lift command) provides this computation. After the THETLC is called and utilized command returns to the address stored when the sub-routine was entered.
The index register B is set with a number that corresponds to an "armed" mode designation. Any roll mode that has been armed and is awaiting satisfaction of additional criteria to activate engagement is given a unique number that is called ROLAIB stored at memory location 2-4327.
As is conventional in computers of the type described, flag locations are included. RAPSIB is a first pass flag which when set calls for special initialization during the first pass of the sub-routine that checks for the satisfaction of the "armed" criteria. After completion of the initialization task, the flag is reset so that in subsequent passes into the sub-routine to check the "armed" criteria, the initialization will not be performed.
AROLIB is the first address of the table of addresses of the sub-routines which check the criteria that enable transition of an armed roll mode to an engaged mode. The index number stored in index register B converts AROLIB to a table of addresses, the index register B having been previously set by the recognition of which specific roll mode was armed, reference being had to the block 164 of FIG. 5. A specific address for each armed mode thereby defines a different sub-routine for checking the engage criteria.
Generally, five instructions are exemplified in the specific operations performed which in the operation of these instructions, other instructions of the repertoire are also utilized. For example, the return jump instruction (RJP) with the octal designation 76 transfers (P)+1 to Y and transfers Y+1 to P. The indirect jump (IJP) with the octal designation 55 transfers (Y) to P. The enter B with (Y) instruction (ENTB) with the octal designation 32 transfers (Y) to the index register B. The enter AL with (Y) instruction (ENTAL) with the octal designation 12 transfers (Y) to the lower accumulator AL. The indirect return jump instruction modified by the index register B (IRJPB) designated octally as 31 transfers (P)+1 to (Y) and (Y)+1 to P where (B) is added to the operand.
It will be appreciated that in these specific examples given, the computer 24 utilizes 18 bit instruction and data words and 12 bit index register words. Associated with the above-described functions, the following table indicates the specific instructions stored at the specific locations in the program memory 52 (FIG. 2) with the resulting response of the computer 24.
__________________________________________________________________________LOCATION INSTR INSTR' OPERAND COMPUTER RESPONSE FUNCTION OF__________________________________________________________________________ INSTRUCTIONI 2-0662 76 4057 RJP'THETLC . THETLC is subroutine in Computes a pitch increment .DELTA. .crclbar. which location 2-4057 is a function of bank angle .phi., weight W, flap deflection .delta..sub.F and .intg. (.gradient./V)dt . GO TO LOCATION 2-4057 . STORE (P + 1) = 0663 in 4057 . SET P TO Y + 1 = 4057 + 1 = 4060 . EXECUTION OF THETLC STARTS AT 4060 2 4060 ... ... THETLC subroutine 2 40XY 55 4057 IJP'THETLC . Set P register to con- Ends THETLC subroutine and commands tents stored in loca- return to address stored when sub- tion 2-4057...that is, routine was entered. 2-0663II 2 0663 32 4327 ENTB'ROLAIB . Set B (index) register The index register is set with a to value stored in loc- number that corresponds to an "armed" ation 2-4327 (ROLAIB) mode designation. Any roll mode that has been armed and is awaiting sat- isfaction of additional criteria to activate engagement is given a unique number that is called ROLAIB (loca- tion 2-4327).III 2 0664 12 4335 ENTAL'RAPSIB . Enter Lower Accumulator RAPSIB is a first pass flag...when with contents of location set, it asks for special initiali- 2-4335 (RAPSIB) zation during the first pass of the subroutine that checks for satis- faction of the "armed" criteria. After completion of the initialization task, the flag is reset so that in subsequent passes into the subroutine to check "armed" criteria, the initialization will not be performed.IV 2 0665 31 5175 IRJPB'AROLIB . Go to location 5175 + B AROLIB is the first address of the AROLIB+ B) table of address of the subroutines . This location contains which check the criteria that enable an address... transition of an armed roll mode to call that address M an engaged mode. The index number . Store the next location stored in index register B converts of the P register (P + 1) AROLIB to a table of addresses. B was which is 2-0666 in previously set by the recognition of address M. "M" is an which specific roll mode was armed. A address whose contents specific address for each armed mode is "M-NAME" thereby defines a different subroutine . Set P to M + 1 for checking engage criteria. . Execution of the "M-NAME" subroutine starts at location M + 1__________________________________________________________________________
With regard to failures that may occur referring to Section I of the Table, it is assumed that the instruction in location 2-0662 does not execute at all, i.e., the computer instruction decoding apparatus (not shown) considers the instruction as one calling for no operation. This results in the subroutine THETLC not being called which results in a task not being accomplished, thereby resulting in the failure to set a task completion bit.
Another failure may occur if the instruction in memory location 2-0662 which should be 76 4057 is erroneously equal to 76 4017 because a single bit at the memory location cannot be set to a 1. The 18 bit number 76 4057 (octal) is in binary form:
1 1 1 1 1 0 1 0 0 0 0 0 1 0 1 1 1 1 = 764057
1 1 1 1 1 0 1 0 0 0 0 0 0 0 1 1 1 1 = 764017,
where the underlined bit represents the erroneously operating bit. The computer 24 will then attempt to execute instructions in the following manner. The program counter 85 will go to location 2-0662 whereat it finds the return jump (RJP) instruction (76) but to an erroneous address 4017, rather than to the correct address 4057. The desired subroutine THETLC is stored in the program memory 52 (FIG. 2) starting at location 4057. The computer executes the return jump instruction (76) by storing the contents of the program counter 85 incremented by 1 [(P+1) = 2-0662 + 1 = 2-0663] in the erroneous address 4017. The program counter 85 is then set to Y + 1 = 4017 + 1 = 4020 (conventional computer octal arithmetic). Thus the computer begins executing at location 4020 but this is not the THETLC subroutine but another subroutine.
The program has now "gotten lost" and the normal flow of the program has been destroyed. There are two alternative paths for the program to take. The erroneous subroutine entered may exit upstream or downstream of the normal program flow. If it exits upstream of the call location 2-0662, the program sequence forms a loop and will be repeatedly executed until the timing cycle expires in accordance with the real time interrupt described above. If it exits downstream, a large portion of the program will be skipped. In either event, there will be a number of tasks which were not accomplished and the associated task completion bits would not have been set.
In another manner of failure with reference to section II of the above table, assume failure in the index register B, e.g., the inability to reset a bit in the B register. Thus, the index register B is set with the quantity ROLAIB which is the contents of location 4327. Assuming that ROLAIB (or the contents of location 4327) is zero but that one of the bits of the B index register is "stuck" in the binary ONE state. Thus instead of a 12 bit index register number equal to
______________________________________000 000 000 000______________________________________
the index register instead provides
______________________________________100 000 000 000 = 4000 octal______________________________________
Referring to Section IV on the above table, the value set in the B register is utilized to find the address of a subroutine. In this portion IV of the Table the program is steered to location 5175 +B (actually 2-5175 indicating location 5175 in memory bank 2). If (B) were properly zero, control would have gone to location 2-5175 to find the address M. However, because of the erroneous value in B, control goes to 2-5175 + 4000 = 31175 (octal). At this erroneous location 31175 the program erroneously attempts to read the address M. The instruction stores the next count of the P counter 85 (P.div.1) at this erroneous address M (contents of 31175). The program then sets the P counter 85 to M + 1. Hence, execution starts at the erroneous M + 1 address.
A failure of this type may transfer program execution to any location of memory within the addressing capability of the P counter 85. In an actual mechanization of the above described preferred embodiment of the invention the effect of the specific failure described was traced through the program which actually steered program control to location 31175. Specifically that erroneous location was actually used to store a control variable. Thus the address M was the value of that variable. Since in the specific situation encountered that variable was usually near zero and assuming that at the time of the failure M was equal to zero, the location 00000 would have the contents 20666 and the location 0001 would have the contents 300505 with execution starting at location 00001 transferring the program to a failure routine. This occurs since in the particular computer utilized, the low memory addresses contain indirect return jumps to system failure routines which, in turn, stop the machine. Thus the routine in 0505 was of this type and hence the machine would have entered a failure routine indicating a fault and then would have stopped. In the particular embodiment described non-used memory locations contain zeros which are utilized as fault codes which indirectly cause the same result (i.e., a fault interrupt causes transfer to a system failure routine). If the executive program would have transferred to an active area of the program memory, then the failure mode operations would occur as described above in the example given above with regard to a memory bit failure.
With regard to the failure response of the computer 24 to an index register failure as described above, the program would "get lost" if an arithmetic instruction should fail. For example, the failure described above with regard to the index register failure could have occurred if the ADD instruction were not operating properly. The indirect return jump B modified instruction (IRJPB) indicated in section IV of the above table, executes by using the arithmetic unit 54 ADD apparatus and associated routine to add the contents of the B index register 86 (FIG. 2) to the address called by the indirect return jump instruction. Thus in section IV of the above table the computer 24 should add 2-5175 + B. If the addition is not accomplished properly the program is steered in an erroneous address in the manner described above when the contents of the index register B were incorrect. The program will, therefore, be steered to one of three regions. The program may enter a region at a lower location than its exit location so that the program will form a loop and "hang-up" which fault will eventually be identified by the next occurring real time interrupt and the check of the task completion bits as described above. Alternatively the program may enter a region at a higher location than its exit location and it therefore skips task completion bit setting program segments so that the task completion test will detect the failure. The program may also enter a region where it is transferred into fault routines that stop the computer and indicate a failure as described above.
From the foregoing it is appreciated that a totally monitored automatic flight control system is achieved using a single digital computer and appropriate interfacing sensors and electronics in each of the two channels of the system. Because of the novel hardware and software monitoring techniques described above 100% failure detection capability is assured followed by a safe shutdown of the failed channel. Two such channels operating simultaneously provide a fail operative capability and with only one such channel operating the automatic flight control system provides "fail-passive" performance. Because of the hardware and software techniques described above it is assured that no failure or equipment anomoly will go undetected, including any malfunction in the ability of the computer to execute instructions. The fault detection capability provided by the above described system operates down to a single erroneous bit in a stored program of thousands of words. The above described structuring of the program is such that digital computer instruction repertoire failures of any type result in incorrect branching of the program flow. Failure of the program flow to progress in the specified manner is determined by both the computer program which detects the absence of a proper sequence of task completion indicia and by an external hardware monitor which detects an error in a dynamic signal pattern which pattern will only be correct if the computer performs its specified task properly. In addition to these monitoring techniques, computer redundancy in the stored program is utilized to detect failures in individual bits of the data storage portion of the computer memory. Thus the continuously refreshed value of a sensed control parameter is stored in two memory locations and the control law computations utilizing that sensor output are calculated twice with the results compared to confirm integrity of the data flow and storage. There are, however, no comparison monitors required between the computers of the two channels as are utilized in conventional fail-passive systems since only one computer is required to achieve the desired monitoring capability of detecting any equipment failure.
The above described system detects and shuts down the failed channel in the event of a computer failure. Two basic types of failure of the computer are possible, i.e., the machine may lose part or it may lose all of its intelligence. If the computer loses all of its intelligence it will not be capable of generating the validity pattern signal and thus this condition is detected externally and the system shut down. If the computer suffers only a partial loss of intelligence, this loss may be detected internally by the computer itself. Thus, by the above-described rigid structure of the software system, the computer retains the capability to detect a partial loss of intelligence. There are generally two causes for a partial loss of computer intelligence. The central processor unit may fail causing a particular instruction or class of instructions to function improperly. A memory or memory addressing failure may cause a particular memory location or class of memory locations to contain improper data or instructions. As described above, and in summary, the following techniques are utilized to detect a partial loss of intelligence.
1. Critical computations are performed in a dual manner providing an essentially perfect memory checking system. This technique is primarily utilized to detect all associated particular memory failures or other computation anomolies.
2. Task list checking is utilized to insure that the program is flowing as prescribed, i.e., verifying that the main program flow is being followed as specified.
3. The novel programming technique described hereinabove is utilized which must yield the correct results in order for the program flow to continue correctly. By utilizing this technique it can be verified that every instruction used by the program executes properly in a generic sense. This programming technique forces the detection of anomolous conditions by reason of utilization of the technique described above in sub-paragraph 2.
This programming technique has been characterized as forcing the program to "get lost". When this happens the computer may attempt to execute program where no memory exists and hence the computer will fail to function properly. Generally the getting lost technique is that the program branches when it shouldn't and doesn't branch when it should or branches to a non-specified address. This technique may be further characterized as forcing the program to take the proper flow only when all instructions are functioning properly. By utilizing this novel programming technique in combination with the task list checking procedure discussed in sub-paragraph 2 above the program checks for the proper execution of the computer instruction repertoire and various computer hardware elements such as the arithmetic instructions, the enter instructions, the store instructions, the conditional and unconditional transfer instructions, the logical instructions, the shift instructions, the register transfer instructions and the software accessible registers.
4. A check sum is performed on all constants utilized by the computations that are performed on a single channel basis. This technique has an extremely high probability of detecting memory failures associated with the single channel constants.
5. The program is organized in the computer memory in dual memory banks as described above so as to render memory addressing failures readily detectable. This technique utilized in conjunction with the above described techniques insure that all generic memory addressing failures are detected.
The above described novel programming technique of exercising the computer instruction repertoire by using the instructions to manipulate branching addresses such that if an instruction should fail the program flow follows an abnormal path and cannot complete the specified program, is the opposite programming philosophy to that utilized in the prior art in what are known as fault tolerant computers wherein the programming is designed such that if a failure should occur, branching into alternate paths will take place to complete the program. In the present invention the program is structured so that if such failure should take place the program will "get lost" and hence the failure will be detectable so that appropriate shut down procedures may be effected.
In summary it is believed that for the first time a fail operative, dual channel automatic flight control system utilizing a single digital computer in each channel has been achieved for practical utilization in modern aircraft. Although this concept has been generally considered in the prior art and systems described that attempt to achieve this desideratum, it is believed that by the above described novel combination of techniques, this desideratum has actually been achieved in a practical flight environment.
The program coding for executing the above described program utilizing the above referenced 1819 computer is provided in the appendix hereto. The program is written in 1819 SCAMP assembly language suitable for execution by the computer.
While the invention has been described in its preferred embodiments, it is to be understood that the words which have been used are words of description rather than limitation and that changes may be made within the purview of the appended claims without departing from the true scope and spirit of the invention in its broader aspects.

Claims

1. An automatic flight control system for aircraft having aerodynamic control surfaces and associated servo means coupled therewith for positioning said control surfaces and having sensor means for providing sensor signals in accordance with flight conditions experienced by said aircraft, comprising
digital computer means having computer input means responsive to said sensor signals, program memory means, a repertoire of instructions operative in said flight control system and computer output means,
computer input coupling means for coupling said sensor means to said computer input means,
said computer means having a program stored in said program memory means comprising a plurality of first program segments structured for sequential execution by said computer means for controlling said computer means to operate on said sensor signals by sequentially performing a plurality of tasks respectively, to provide surface command signals to said computer output means,
said program further including a plurality of second program segments associated with said first program segments, respectively, for switching task completion indicia in said computer means to a set state in accordance with completion of said tasks, respectively,
said program further including a third program segment for testing said indicia for said set state thereby testing said indicia for completion of said tasks,
said program utilizing all of said instructions of said repertoire within at least one of said first, second and third program segments in a manner to cause at least one of said indicia to remain unset upon failure of an instruction to function properly,
said program further including a failure program segment that is entered from said third program segment when one of said indicia remains unset, said failure program segment including instructions for stopping the execution of said program,
means for controlling repeated executions of said program,
said program further including a fourth program segment for generating a precisely defined dynamically varying validity pattern by controlling a validity pattern signal at said computer output means to exhibit one level during an execution of said program and a different level during a subsequent execution thereof,
validity pattern detector means coupled to said computer output means to receive said validity pattern signal for detecting said validity pattern signal being in a state different from said precisely defined state during a time interval in which said repeated executions of said program would normally provide said precisely defined dynamically varying validity pattern signal and for providing a failure signal in accordance therewith, and
computer output coupling means said computer output means to said surface servo means for providing said surface command signals thereto.
2. The system of claim 1 in which said program segments are arranged as an executive program with program sub-routines and linking instructions controlling transferring between said executive program and said sub-routines, where the associated transfer addresses are derived utilizing said instructions of said repertoire to cause said program to follow an abnormal path upon failure of any one of the so utilized instructions thereby causing at least one of said indicia to remain unset.
3. The system of claim 1 in which said repertoire includes an instruction to wait for an interrupt and said means for controlling repeated executions of said program comprises
a real time clock means, and
a program segment in said program responsive to said real time clock means for controlling said computer to wait for a real time interrupt.
4. The system of claim 1 in which said program memory means comprises dual program memory banks, said plurality of first program segments being stored in one of said program memory banks and a plurality of program segments identical to said first program segments being stored in the other of said program memory banks,
thereby providing computational redundancy to test the proper operation of said program memory means.
5. The system of claim 4 in which said computer means further includes dual data memory banks for storing identical sets of said sensor signals for operation thereon by said first program segments and said identical program segments, respectively,
thereby providing data storage redundancy to test the proper operation of said data memory banks.
6. The system of claim 5 in which said task completion indicia comprise the bits respectively of a word stored in said data memory.
7. The system of claim 4 in which said computer means includes read/write circuitry means associated with said program memory means and in which said first program segments and said identical program segments are stored in said dual program memory banks, respectively, in a skewed manner with respect to the address locations of each other,
thereby testing the proper operation of said read/write circuitry means.
8. The system of claim 1 in which said computer means includes a computer I/O control unit including said computer input means and said computer output means for providing control signals to said computer input and output coupling means.
9. The system of claim 8 in which said computer input coupling means comprises
input multiplexer means coupled to receive said sensor signals from said sensor means and coupled to receive said control signals from said I/O control unit and having a multiplexer output for selectively applying said sensor signals to said multiplexer output in accordance with said control signals, and
analog to digital converter means coupled to said multiplexer output for converting said selectively applied sensor signals to digital form for application to said computer input means.
10. The system of claim 9 in which said computer output coupling means comprises
output multiplexer means coupled to said computer output means and coupled to receive said control signals from said I/O control unit and having a plurality of multiplexer outputs for selectively coupling said computer output means to said plurality of multiplexer outputs in accordance with said control signals, and
a plurality of digital to analog converter means coupled to said plurality of multiplexer outputs respectively for converting said surface command signals from said computer output means from digital form to analog form for application to said surface servo means.
11. The system of claim 10 further including means coupling said digital to analog converter means to said input multiplexer means for transmitting said surface command signals in analog form thereto for end-around testing of proper operation of said digital to analog converter means.
12. The system of claim 1 in which said different state of said validity pattern signal comprises remaining in a static state.
13. The system of claim 1 in which said different state of said validity pattern signal comprises responding in an incorrect dynamic state.
14. A dual channel fail operative automatic flight control system for aircraft having aerodynamic control surfaces and associated servo means coupled therewith for positioning said control surfaces, each channel comprising
sensor means for providing sensor signals in accordance with flight conditions experienced by said aircraft,
a digital computer having computer input means responsive to said sensor signals, program memory means, a repertoire of instructions operative in said flight control system and computer output means,
computer input coupling means for coupling said sensor means to said computer input means,
said computer having a program stored in said program memory means comprising a plurality of first program segments structured for sequential execution by said computer for controlling said computer to operate on said sensor signals by sequentially performing a plurality of tasks, respectively, to provide surface command signals to said computer output means,
said program further including a plurality of second program segments associated with said first program segments, respectively, for switching task completion indicia in said computer to a set state in accordance with completion of said tasks, respectively,
said program further including a third program segment for testing and indicia for said set state thereby testing said indicia for completion of said tasks,
said program utilizing all of said instructions of said repertoire within at least one of said first, second and third program segments in a manner to cause at least one of said indicia to remain unset upon failure of an instruction to function properly,
said program further including a failure program segment that is entered from said third program segment when one of said indicia remains unset, said failure program segment including instructions for stopping the execution of said program,
means for controlling repeated executions of said program,
said program further including a fourth program segment for generating a precisely defined dynamically varying validity pattern by controlling a validity pattern signal at said computer output means to exhibit one level during an execution of said program and a different level during a subsequent execution thereof,
a validity pattern detector coupled to said computer output means to receive said validity pattern signal for detecting said validity pattern signal being in a state different from said precisely defined state during a time interval in which said repeated executions of said program would normally provide said precisely defined dynamically varying validity pattern signal and for providing a failure signal in accordance therewith, and
computer output coupling means coupling said computer output means to said surface servo means for providing said surface command signals thereto.
15. The system of claim 14 in which said program segments are arranged as an executive program with program sub-routines and linking instructions controlling transferring between said executive program and said sub-routines, where the associated transfer addresses are derived utilizing said instructions of said repertoire to cause said program to follow an abnormal path upon failure of any one of the so utilized instructions thereby causing at least one of said indicia to remain unset.
16. The system of claim 14 in which said repertoire includes an instruction to wait for an interrupt and said means for controlling repeated executions of said program comprises
a real time clock means, and
a program segment in said program responsive to said real time clock means for controlling said computer to wait for a real time interrupt.
17. The system of claim 14 in which said program memory means comprises dual program memory banks, said plurality of first program segments being stored in one of said program memory banks and a plurality of program segments identical to said first program segments being stored in the other of said program memory banks,
thereby providing computational redundancy to test the proper operation of said program memory means.
18. The system of claim 17 in which said computer further includes dual data memory banks for storing identical sets of said sensor signals for operation thereon by said first program segments and said identical program segments, respectively,
thereby providing data storage redundancy to test the proper operation of said data memory banks.
19. The system of claim 18 in which said computer includes read/write circuitry means associated with said program memory means and in which said first program segments and said identical program segments are stored in said dual program memory banks, respectively, in a skewed manner with respect to the address locations of each other,
thereby testing the proper operation of said read/write circuitry means.
20. The system of claim 19 in which said computer includes a computer I/O control unit including said computer input means and said computer output means for providing control signals to said computer input and output coupling means.
21. The system of claim 20 in which said computer input coupling means comprises
input multiplexer means coupled to receive said sensor signals from said sensor means and coupled to receive said control signals from said I/O control unit and having a multiplexer output for selectively applying said sensor signals to said multiplexer output in accordance with said control signals, and
analog to digital converter means coupled to said multiplexer output for converting said selectively applied sensor signals to digital form for application to said computer input means.
22. The system of claim 21 in which said computer output coupling means comprises
output multiplexer means coupled to said computer output means and coupled to receive said control signals from said I/O control unit and having a plurality of multiplexer outputs for selectively coupling said computer output means to said plurality of multiplexer outputs in accordance with said control signals, and
a plurality of digital to analog converter means coupled to said plurality of multiplexer outputs respectively for converting said surface command signals from said computer output means from digital form to analog form for application to said surface servo means.
23. The system of claim 22 further including means coupling said digital to analog converter means to said input multiplexer means for transmitting said surface command signals in analog form thereto for end-around testing of proper operation of said digital to analog converter means.
24. The system of claim 14 in which said different state of said validity pattern signal comprises responding in an incorrect dynamic state.
25. The system of claim 14 in which said different state of said validity pattern signal comprises remaining in a static state.

CROSS REFERENCE TO RELATED APPLICATION

This is a continuation-in-part of application Ser. No. 485,862, filed July 5, 1974, now abandoned, in the names of Stephen S. Osder and David C. Mossman entitled "Automatic Flight Control System With Operatively Monitored Digital Computer" and assigned to the present assignee.

US Referenced Citations (5)

Number	Name	Date
3379951	Franchi et al.	Apr 1968
3444528	Lovell et al.	May 1969
3551776	Tawfik et al.	Dec 1970
3688099	Buscher	Aug 1972
3781627	Binnig et al.	Dec 1973

Continuation in Parts (1)

	Number	Date	Country
Parent	485862	Jul 1974

Automatic flight control system with operatively monitored digital computer

Information

Patent Number

Date Filed

Date Issued

Inventors

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Agents

CPC

US Classifications

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US

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Abstract

Description

Claims

CROSS REFERENCE TO RELATED APPLICATION

US Referenced Citations (5)

Continuation in Parts (1)