AUTOMATIC HIGH VOLTAGE GATE DRIVER IC (HVIC) FOR PDP

Abstract

A PDP sustain driver circuit including at least one high voltage gate driver IC (HVIC) having a logic functional block. The PDP sustain driver circuit includes a signal buffer for receiving two input signals and providing the two signals to the logic functional block; and at least four switches including a charging switch, a discharging switch, a sustain switch and a grounding recovery switch, the HVIC providing a unique control signal from the logic functional block to the four switches to control said four switches.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a conventional PDP sustain driver

FIG. 2 is a schematic diagram of the conventional PDP sustain driver of FIG. 1 having four inputs connected to switch gates;

FIG. 3 a is a schematic diagram of a PDP sustain driver that uses an HVIC having internal logic functions and system information and that only requires two input signals;

FIG. 3 b is a block diagram of the HVIC used in the PDP sustain driver of FIG. 3a;

FIG. 4 is a circuit diagram of an exemplary embodiment of the HVIC of the present invention;

FIG. 5 is a circuit diagram of the logic functional block of FIG. 3b; and

FIGS. 6 a-6d are graphs corresponding to possible operating modes of the PDP sustain driver of the present invention allowed by the logic functional block of FIG. 5.

Claims

1. A PDP sustain driver circuit including at least one high voltage gate driver IC (HVIC) comprising a logic functional block, the circuit comprising: a signal buffer for receiving two input signals and providing the two signals to the logic functional block; andat least four switches including a charging switch, a discharging switch, a sustain switch and a grounding recovery switch, the HVIC providing a unique control signal from the logic functional block to the four switches to control said four switches.

2. The circuit of claim 1, wherein the PDP sustain driver is a bridge driver with soft switching for a capacitive load.

3. The circuit of claim 1, wherein the charging and discharging switches are coupled as a first half-bridge and the sustain and grounding recovery switches are connected as a second half-bridge.

4. The circuit of claim 1, wherein the HVIC senses voltage on at least one of the sustain and grounding recovery switches and a sensed result is provided to the logic functional block as a delay setting for the at least one of the sustain and grounding recovery switches.

5. The circuit of claim 4, wherein user set information is provided to the logic functional block as a delay setting of the at least one of the sustain and grounding recovery switches instead of the sensed result.

6. The circuit of claim 5, wherein two settings of the user set information are provided.

7. The circuit of claim 4, wherein the sensed result is used to optimize gating of the sustain driver.

8. The circuit of claim 1, wherein the HVIC further comprises a gate driver for processing output signals of the logic functional block and providing at least two unique control signals for controlling the switches.

9. The circuit of claim 8, wherein the unique control signals enable at least two operating modes.

10. The circuit of claim 1, wherein the logic functional block is integrated with HVIC.

11. The circuit of claim 1, comprising at least one HVIC.

12. The circuit of claim 11, wherein the HVICs share the two input signals.

13. The circuit of claim 1, wherein the logic functional block further comprises first and second flip-flops, the first flip-flop providing charge ERR and discharge ERF control signals and the second flip-flop providing sustain SUS and grounding recovery GRND control signals.

14. The circuit of claim 13, wherein the first flip-flop receives a reset signal from a first inverter that inverts an ERR/ERF primary input signal; and a set signal from a first AND circuit that ands the ERR/ERF primary input signal, an inverse of an ERR/ERF secondary input signal from a second inverter, and an inverse output of the second flip-flop.

15. The circuit of claim 14, wherein the second flip-flop receives a reset signal from the ERR/ERF secondary input signal; anda set signal from a first OR circuit that operates on signals received from second and third AND circuits, the third AND circuit operating on the ERR/ERF primary input signal and the inverse of the ERR/ERF secondary input signal from the second inverter, the second AND circuit operating on the ERR/ERF primary input signal, the inverse of the ERR/ERF secondary input signal from the second inverter, and an inverse of an internal gating signal from a delayed on-shot vibrator circuit from a third inverter.