Claims
- 1. A compiler system for allowing a user to specify the total number of words and bits per word in a memory structure and to choose among alternative structures for the specified memory structure according to a selected criterion, comprising:
- means for selectively varying the partitioning of memory address lines in a memory structure among column address lines and row address lines;
- means for selectively varying a memory structure in terms of the number of rows and columns according to the selected partitioning of memory address lines among column address lines and row address lines; and
- means for optimizing the memory structure during compilation thereof by automatically selecting an optimal structure based upon at least one higher-level user-selectable criterion which defines a user-specified constraint of the compiled memory structure, wherein the at least one higher-level user-selectable criterion includes at least one of a selected area, a total number of gate sites occupied by the memory structure, an aspect ratio, and a minimum access time of the overall compiled memory.
- 2. A system according to claim 1 wherein elements in the memory structure are random access memory elements.
- 3. A system according to claim 1 wherein the compiler system is a gate array block compiler.
- 4. A process for implementing a block compiler system such that the system allows a user to specify the total number of words in a memory structure and to choose among alternative structures for the specified memory structure according to a selected criterion, comprising:
- selecting the total number of words in a memory structure of an application-specific integrated circuit;
- selectively varying the partitioning of memory address lines of the memory structure, in terms of column address lines and row address lines; and
- optimizing the memory structure by selecting an optimal structure based on at least one higher-level user-selected criterion during compilation of the memory structure which defines a user-specified constraint of the compiled memory structure, wherein the at least one higher-level user-selectable criterion includes at least one of a selected area, a total number of gate sites occupied by the memory, an aspect ratio, and a minimum access time of the overall compiled memory structure.
- 5. A process according to claim 4 wherein the elements in the memory structure are random access memory elements.
- 6. A process according to claim 4 wherein the compiler system is a gate array block compiler system.
- 7. A process according to claim 4 further including a step of selecting a number of bits per word for the memory structure of an application-specific integrated circuit.
Parent Case Info
This application is a continuation of application Ser. No. 07/626,078, filed Dec. 10, 1990, and now abandoned, which is a continuation-in-part of U.S. application Ser. No. 7/566,684, filed Aug. 10, 1990 and now abandoned.
US Referenced Citations (8)
Continuations (1)
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626078 |
Dec 1990 |
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Continuation in Parts (1)
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566684 |
Aug 1990 |
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