Claims
- 1. An automatic tuning device of a FM receiver comprising:
- an auto-scanning circuit for outputting a squelch signal,
- a scanning-stop circuit for outputting a tuning-stop signal,
- an integrating circuit, a demodulation circuit, means for coupling the demodulation circuit to the integrating circuit, the integrating circuit extracting a DC component from a demodulation signal outputted from the demodulation circuit, within a constant range around a tuning frequency,
- a window comparator and means for coupling the integrating circuit to the window comparator, the window comparator detecting whether or not the DC component is within the range to output the demodulated signal,
- a timing circuit and means for coupling the window comparator to the timing circuit, the timing circuit being switched on by the demodulated signal outputted from the window comparator being continued for a given time, and
- an AND circuit, means for coupling the scanning-stop circuit to the AND circuit, means for coupling the timing circuit to the AND circuit, and means for coupling the auto-scanning circuit to the AND circuit, the AND circuit outputting to the scanning-stop circuit an output signal which brings into action the scanning-stop circuit only when the timing circuit is switched on and the squelch signal is outputted.
- 2. The automatic tuning device of a FM receiver claimed in claim 1, wherein the window comparator is constituted by using two comparators, and to each one input terminal of each comparator is given a positive reference voltage, and the values of the reference voltages are made different from each other.
- 3. The automatic tuning device of a FM receiver claimed in claim 1, wherein the window comparator is constituted by using two comparators, and to one input terminal of one of the two comparators is given a positive reference voltage, and to one input terminal of the other of the comparators is given a negative reference voltage.
- 4. The automatic tuning device of a FM receiver claimed in claim 1, wherein the timing circuit is provided with a transistor for switching which outputs an output signal toward the AND circuit and a delay circuit for on-off controlling the transistor for switching, a demodulated signal being inputted to the delay circuit.
Priority Claims (1)
Number |
Date |
Country |
Kind |
55-72175 |
May 1980 |
JPX |
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Parent Case Info
This is a continuation in part of Ser. No. 266,386 filed, May 22, 1981, now abandoned.
US Referenced Citations (4)
Number |
Name |
Date |
Kind |
3560858 |
Sakai et al. |
Feb 1971 |
|
3947774 |
Glennon et al. |
Mar 1976 |
|
4245348 |
Imazeki |
Jan 1981 |
|
4387469 |
Miyazaki et al. |
Jun 1983 |
|
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
266386 |
May 1981 |
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