The present invention relates to systems and methods for automatically tuning a proportional-integral-derivative (PID) controller for DC-DC buck switching power converter.
Fueled by the development of low-cost microcontrollers with high clock speeds, the autotuning of digitally-controlled DC-DC switched-mode converters has attracted the attention of researchers in the last two decades. Even though analog controllers are still faster and cost less, the digital controller offers some unmatched advantages such as the immunity to controller parameter variation, the ease of retuning the controller, and the ability to implement highly sophisticated control algorithms
Autotuning in the present context refers to the automatic online tuning of a digital controller at pre-set intervals or in response to a user command or a triggering event. Because components in converters have a tolerance and so their exact values are unknown, and because they are prone to ageing, the ability of a controller to retune itself based on actual system parameters rather than a nominal mathematical model can largely improve the stability and dynamic performance of a converter. Autotuning generally includes a test stage in which the system dynamics are excited, and a tuning stage in which the controller is retuned using measurements from the test. Some autotuning methods use an intermediate stage of system identification.
The relay feedback test (RFT) is classically known in the field of control. It involves placing a relay in series with the plant or process, and operating the system in closed-loop, which leads to limit-cycle oscillations occurring at the phase cross-over)(−180°) frequency of the plant. The amplitude and time period of the oscillations are measured and used for tuning a PID controller, for example, using the Ziegler and Nichols (Z-N) PID tuning rules. While this usually yields satisfactory performance, stability is not guaranteed, nor are gain or phase margin be specified. A form of RFT-based autotuning of a DC-DC buck converter has been previously implemented. However, different from the conventional RFT, an integrator is placed in series with the RFT relay. This forces oscillations at a frequency corresponding to a −90° phase shift, thereby identifying the LC resonant frequency of the converter. The first PID zero is placed at the resonant frequency, while the other zero is iteratively tuned until the desired phase margin is met. The PID gain is finally tuned (iteratively) to achieve the desired bandwidth. A disadvantage of this method is that since oscillation amplitude is large at the resonant frequency, the test is performed at a voltage below the nominal, during the startup ramp. This means autotuning must be performed during regular operation. Also, the tuning process is somewhat complex and long as it consists of several stages, some with iterations. In other prior implementations, an improvement to the same RFT-based work has been developed in which only time-period measurements are used in order to avoid errors related to amplitude measurement. In other prior art, limited-cycle oscillations are induced in a DC-DC buck converter by temporarily reducing the resolution of the digital PWM rather than using a relay, which allows for continued regulation of the system even during the test stage, although with poorer tracking.
Several other autotuning methods using tests besides RFT have also been implemented, for example, methods that use the injection of a pseudo-random binary sequence (PRBS) in the test stage. But almost all known methods, whether based on the RFT, PRBS injection, or others, have some level of complexity, mainly because the full burden of test and tuning is to be done online. One way to simplify the test and tuning stages, and thus make them more suitable for practical implementation, is to utilize general knowledge of the system's behavior to do part of the tuning preparation offline. The modified relay feedback test (MRFT) autotuning method is one such method. It is built on a coordinated test and tuning concept that guarantees a specified gain margin or phase margin. Further, the MRFT autotuning method can also be extended to include optimized non-parametric tuning, which in addition to the guaranteed gain or phase margin, provides near-optimal transient performance for a wide range of designs of a given system. The MRFT autotuning method consists of a single-step test and a single-step tuning stage, which are described below.
TEST STAGE: A general block diagram of the test stage of the MRFT autotuning method is shown in
h is the “MRFT magnitude”, which is the amount of the control effort provided by the MRFT block to the process, or in other words the command provided to the actuator. The test stage of MRFT autotuning method is performed when the subject system is in steady-state.
TUNING STAGE: A PID controller of the format
is used in the MRFT autotuning method. The tuning stage is to simply calculate the updated PID parameters using the following equations, where c1, c2, c3 are predetermined constants:
Kc=c1Ku, Ti=c2Tu, Td=c3Tu Eq. (3)
According to one or more aspects of the present disclosure, a method of automatically tuning a digitally-implemented proportional-integral-derivative (PID) controller for the purpose of controlling a DC-DC buck switching power converter includes the steps of
where s is the Laplace variable, Kc is the proportional gain, Ti is the integral time, and Td is the derivative time, to drive the system to a steady state;
and
In one or more embodiments of the method according to any one of the previous paragraphs, the threshold parameter of the MRFT block is given by β=−0.2±5%.
In one or more embodiments of the method according to any one of the previous paragraphs, c1=0.69±5%, c2=1.14±5%, and c3=0.19 ±5%.
According to one or more aspects of the present disclosure a non-transitory computer readable storage medium has data stored therein representing software executable by a computer. The software includes instructions to switch a controller circuit of a DC-DC buck switching power converter from a proportional-integral-derivative (PID) controller to an MRFT block; determine an error signal (e[k]) by measuring an output voltage (Vo[k]) of the DC-DC buck switching power converter and comparing it to a desired reference output voltage (Vo-ref); input the error signal (e[k]) to the MRFT block; depending on the value of e[k], the MRFT block will output either D+h or D−h, where D is the nominal duty cycle described earlier and h is the MRFT magnitude; repeat the preceding instructions until a predetermined number of oscillation cycles (Ncycles)have developed; measure a frequency (Ω0) and amplitude (a0) of the oscillations as an average over the Ncycle oscillations, but disregarding an initial number of cycles (Ndiscard); update the PID controller parameters based on Ω0 and a0 using the equations
and finally switch the controller circuit of the DC-DC buck switching power converter from the MRFT block back to the (updated) PID controller.
In one or more embodiments of the non-transitory computer readable storage medium according to any one of the previous paragraphs, the software further includes instructions to continuously track the error signal (e[k]) and record every occurring maximum (emax) and minimum (emin).
In one or more embodiments of the non-transitory computer readable storage medium according to any one of the previous paragraphs, the software further includes instructions to measure the frequency (Ω0) and amplitude (a0) of the oscillations as an average based on a number of recorded cycles (NMRFT)—which equals a total number of cycles (Ncycles) minus the initial number of cycles (Ndiscard)—and an elapsed time period (TMRFT) of the number of recorded cycles (NMRFT); Ω0 and a0 are then calculated using
In one or more embodiments of the non-transitory computer readable storage medium according to any one of the previous paragraphs, the software further includes instructions to update the PID controller parameters based on the amplitude (a0) where
In one or more embodiments of the non-transitory computer readable storage medium according to any one of the previous paragraphs, the software further includes instructions to calculate a proportional gain (Kc), Ti an integral time (Ti), and a derivative time (Td) for the PID controller, where:
In one or more embodiments of the non-transitory computer readable storage medium according to any one of the previous paragraphs, the non-transitory computer readable storage medium has data stored therein representing a value of C1 as 0.69±5%, a value of c2 as 1.14±5%, and a value of c3 is 0.19±5%.
In one or more embodiments of the non-transitory computer readable storage medium according to any one of the previous paragraphs, the non-transitory computer readable storage medium has data stored therein representing a value of β as −0.2±5%.
The present invention will now be described, by way of example with reference to the accompanying drawings, in which:
A method of autotuning a PID controller 102 of a DC-DC switching buck converter 100 using the modified relay feedback test (MRFT) is provided. The method is comprised of two components, which are:
In the context of the DC-DC converter, a direct implementation of the original MRFT autotuning method would be to disable the DPWM and let the MRFT directly control the converter switches, so that when the MRFT block output is +h, the main switch is turned ON, and when the relay is −h, the main switch is turned OFF. But since the MRFT frequency is typically much lower than the DPWM frequency, switching at the MRFT frequency will result in an increased ripple in both the inductor current and the output voltage. The present invention adopts a more appropriate approach of double-modulation, where the DPWM is still maintained during the test stage, and the MRFT modulation is superposed on top of it. This is done by setting the MRFT block output, u(t), to either D+h or D−h instead of +h or −h, where D is the nominal duty-cycle, i.e., the modulation index that is normally provided by the PID controller to the DPWM to produce an output voltage equal to the set point (Vo-ref). In such approach, the MRFT oscillations appear superposed on top of the nominal output voltage. In terms of gate pulses, the MRFT manifests as a series of slightly wider PWM pulses corresponding to the D+h duty-cycle and lasting for Tu/2, followed by a series of slightly narrower PWM pulses corresponding to the D−h duty-cycle and also lasting for Tu/2, where Tu is the time period of the MRFT oscillations. The advantage of the adopted approach is that the converter maintains the switching frequency it was designed for even during the test stage, thus maintaining an acceptable level of ripple. This minimizes the impact of the MRFT auto-tuning on the converter, making it possible to take place even during normal operation (in most applications).
The algorithm of the MRFT block in such approach is expressed as below:
The MRFT tuning method can be initiated upon user prompt or programmed by the user in accordance with a certain schedule or event. The MRFT tuning method only lasts for a short duration (typically less than 1 millisecond). The inputs required by the MRFT tuning method routine are:
Next, the MRFT tuning method data that needs to be recorded for post-processing is as follows:
MRFT autotuning method; and
The MRFT tuning method is then executed per the algorithm in the flowchart shown in
The above procedure represents the test stage, which is first of two steps of the MRFT tuning method. The second and final step is the tuning stage, which is to update the PID controller parameters using the test results. A PID controller of the following form is used, where Kc is the proportional gain, Ti the integral time, and Td the derivative time.
Tuning rules of the following form are used, where coefficients c1, c2, and c3, are positive constants.
According to the MRFT autotuning method, selecting c1, c2, and c3, and the threshold parameter β of the MRFT in coordination with each other as per the following constraints would provide a user-specified phase margin, ϕm, for any arbitrary system.
Further to this, using a two-stage optimization technique, the set (β, c1, c2, c3) is chosen so that it provides near-optimal transient performance for a wide range of DC-DC buck converters. Details of the optimization procedure used to obtain the optimized tuning rules is provided later. The optimized set (β*, c1*, c2*, c3*), is given below.
β*=−0.2±5%, c1*=0.69±5%, c2*=1.14±5%, c3*=0.19±5% Eq. (6)
Referring to the example application shown in
A digital microcontroller, e.g., Texas Instruments TMS320F28335, is used for sampling and control. The microcontroller includes non-transitory memory containing software instructions to perform the steps of the method described herein. The microcontroller also includes transitory memory containing data generated by the method described herein.
The switching frequency (fs=1/Ts) of the digital pulse width modulator (DPWM) 108 is set to 200 kHz. The sampling rate is also set to 200 kHz and is synchronized with the PWM. The resistive load (Ro) 110 can be electronically switched between two values to provide load transients for controller testing. The resistor Rs 112 is used to sense the inductor current (IL) through the inductor L 114 for protection purposes. The output filter capacitance consists of a parallel combination of two larger aluminum polymer low equivalent series resistance (ESR) capacitors (together forming capacitance C1) 115 and three smaller ceramic capacitors (together forming capacitance C2) 116. RL, RC1, and RC2 are the parasitic resistances of L, C1, and C2, respectively. Nominal input supply voltage (Vs) is 9 V while the set-point output voltage (Vo-ref) is 2 V.
For the first test setup, L=4.8 μH and C1=440 μF are used (where C1 is formed using two parallel 220 μF capacitors for lower ESR). The MRFT tuning method is performed using the optimized β in Eq. (6). The experimentally measured oscillations in vo are shown in
Immediately following the first stage of the MRFT method, the new PID controller coefficients are calculated. Ku is obtained from Eq. (2) using the measured amplitude a0, and it is used along with the frequency Ω0=2π/Tu to calculate the PID controller coefficients using Eq. (4) and (c1, c2, c3) from Eq. (6). Tu for this example application (using a DC-DC buck converter with L=4.8 μH and C1=440 μF) was 138 μs, while the Ku based on the measured a0 was 11.4 V−1.
This same test stage of the MRFT autotuning method was repeated using the same example converter referred above but with different values of L and C1. For each design, two tests are conducted to test the MRFT auto-tuned controller's performance In the first test, a step in Vo-ref from 2 V to 2.2 V is applied, while in the second test a step in the output current (Io) from 0.27 A to 1.27 A is applied.
For comparison, another PID controller that is tuned optimally for each of the specific converter designs is used. This optimized controller is obtained using the following procedure. Experimentally measured frequency response data of the buck converter system is obtained with the aid of a software frequency response analyzer (SFRA) tool, such as that produced by Texas Instruments Incorporated, and a high order transfer function (TF) is fitted to the measured frequency response data. Using this fitted model, a controller that gives the lowest integral of time-weighted absolute error (ITAE) (in simulation) for a step in Vo-ref for this TF is obtained through optimization using a processes of finding a minimum of an unconstrained multivariable function using derivative-free method, e.g., the fminsearch function in MATLAB® available from MathWorks, Inc. Note that this optimized controller differs from the MRFT block in that it 1) is optimized only for a given converter design and cannot be re-tuned to any other converter, and 2) does not guarantee a specific gain or phase margin.
Table 1 above lists the PID controller parameters for the MRFT blocks and the optimized controllers of each of the four tested designs.
In the remainder of this section, the optimization framework used to arrive at the optimal set of (β, c1, c2, c3) is described. The model below describes a general buck converter. The term e−τs represents the total delay due to sampling/control and the PWM operation, given by τ=1.5Ts.
Let T1=√{square root over (LCo)} and
Gbuck is said to have three following situational parameters, namely T1, T2, and τ. The situational parameters may be reduced to two through use of the scaled Laplace variable s′=T1s, which results in the TF below having only
as situational parameters.
In order to obtain a realistic range of TFs covering practical buck converter designs, basic component-sizing equations are utilized. The following equation may be used to determine the inductive value L in a DC-DC buck converter:
where Vo and Io are the nominal output voltage and nominal output current, respectively. KL is a coefficient related to the inductor current ripple and is typically set between 0.2 and 0.3 for a buck converter. KL=0.3 is chosen to provide the minimum L, since L will be scaled up later. The nominal duty-cycle (D) is taken as 0.5. Noting that the ratio of Vo to Io is equal to the load resistance (Ro), minimum inductance (Lmin) is given by
The design criteria for Co, in the case of a low ESR, is given below where Kc is the desired maximum percent ripple in the capacitor voltage.
Choosing KC as 1%, the following expression is obtained for the minimum inductance, Co-min:
Defining scaling factors aL for L and aC for Co, the situational parameters and thus the expression for Gbuck may be rewritten as follows:
Comparing the characteristic polynomial in the denominator to the standard second order system format of (s2+2ζωn+ωn2), the damping factor ζ is found to be
while the natural frequency ωn is 1. By considering all combinations of aL and aC from 1 to 10, a whole range of converters are represented. An illustration of this in grid format is provided in Table 2.
Finally, to justify the approximation of neglecting the zero that appears in the transfer function when the output capacitor has a non-negligible ESR, the ESR effect is represented to some extent by increasing the damping (ζ). This is done by making sure aL≥aC, which results in ζ being ≥⅓. A total of 55 TFs (shown as shaded boxes in the figure below) are obtained after applying the criterion aL≥aC. The TFs are numbered serially from 1 to 55, with the TF number appearing in the respective box in Table 2.
The optimization framework consists of two stages. In the first stage, the optimized value (β, c1, c2, c3) for every TF of the grid in Table 2 is obtained through optimization of the transient response in simulation, using the derived model Gbuck. The transient performance is evaluated using the “integral of time weighted absolute error” (ITAE), calculated using the following equation, where X is the vector [β, c1, c2, c3]. tinit is the time instant at which the transient occurs, and ts is the settling time.
A combination of computer-based simulation programs, such as MATLAB® and SIMULINK®, also available from MathWorks, Inc., may be used for this purpose. A processes of finding a minimum of an unconstrained multivariable function using derivative-free method, e.g., the fminsearch function in MATLAB® which is based on the Nelder-Mead simplex direct search algorithm, is used for the optimization. Each iteration of the optimization consists of the following 3 steps.
After every iteration (of steps 1-3), the set (β, c1, c2, c3) is updated by the fminsearch function to result in a lower ITAE—while still ensuring that the updated (β, c1, c2, c3) still satisfy the constraints in Eq. (5). The iterations (of steps 1-3) are repeated until the improvement in ITAE is below the specified tolerance. Let the 55 TFs in the grid of
The second stage of the optimization applies the principle of “least performance degradation” to obtain a globally optimized set of (β, c1, c2, c3). This is done as follows:
is then found.
is recorded. This is repeated until all worst-case ITAEs,
are recorded.
The globally optimized set, (β*, c1*, c2*, c3*), is the set with the lowest
In other words, it is the set that results in the least performance degradation when applied to all converters in the considered range. This completes the second stage of the optimization. Constraints used in the optimization process include restricting ϕm in Eq. (5) to [20°, 60°], c2 to [0.1, 100] to limit the integral action, and restricting c1 and c3 to being positive. A final constraint was to set the minimum β to −0.2, since large negative values of β may be difficult to apply in practice due to the oscillations associated with having a smaller amplitude thus making their accurate measurement a challenging task. Performing the optimization process above for the system represented by Gbuck and for the range of parameters defined by the grid of Table 2, the globally optimized set was found to be (β3, c13, c23, c33), which resulted in ϕm=35°. The numerical values of the parameters in this set were:
β*=−0.2, c1*=0.69, c2*=1.14, c3*=0.19
In other words, using (β*, c1*, c2*, c3*)=(β3, c13, c23, c33) to tune a controller for every other Gbuck-n model in the considered range resulted in the least performance degradation from the locally optimized performance, ITAE33. This worst-case degradation,
only 13% more than the locally optimized case ITAE33. It is noted that the (β*, c1*, c2*, c3*) provided earlier in the manuscript included a ±5% tolerance for each parameter in the set. This is because as long as the four parameters satisfy the constraints in Eq. (5), the specified phase margin is guaranteed, and further if they are in the vicinity of the original values of (β3, c13, c23, c33) , then very similar dynamic performance is obtained.
While the invention has been described with reference to an exemplary embodiment(s), it will be understood by those skilled in the art that various changes may be made, and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention is not limited to the disclosed embodiment(s), but that the invention will include all embodiments falling within the scope of the appended claims.
This application is a National Stage Application of International Patent Application No. PCT/IB2021/055825 filed Jun. 29, 2021, which claims priority under Article 8 of the Patent Cooperation Treaty to U.S. Provisional Patent Application 63/045,469 filed in the Unites States Patent and Trademark Office on Jun. 29, 2020, the entire disclosure of each of which is hereby incorporated by reference.
Filing Document | Filing Date | Country | Kind |
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PCT/IB2021/055825 | 6/29/2021 | WO |
Number | Date | Country | |
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63045469 | Jun 2020 | US |