The present disclosure is generally directed toward amplifier circuits and, in particular, toward offset control in amplifier circuits.
Input offsets of amplifiers in circuits such as Analog-to-Digital (ADC) and Digital-to-Analog (DAC), voltage amplifiers, sample-and-holds, etc., often limit the minimum resolutions of these circuits. It is, therefore, critical to cancel out these amplifiers' offset, when circuit accuracy is impacted by the magnitude of these input offsets (e.g., usual amplifier input offsets are in the order of 1˜10 mV). At the same time, 1/f noise which is dominant at low frequencies will be concurrently reduced with input offset cancellation. This further improves circuit accuracy.
Two general categories of offset cancellation are already in use: (1) Chopper Stabilization and (2) Autozeroing. In chopper stabilization, a low pass filter is usually required at the output of these amplifiers to reduce the magnitude of the output swing caused by chopping.
In single-ended output sample and hold DAC configuration, the DAC output is often not offset-free in both sample and hold modes, as illustrated in
Additional errors due to charge injection upon switch turn off of the holding capacitor Ch adds to the pedestal in the output voltage Vout. In this structure of
The present disclosure is described in conjunction with the appended figures, which are not necessarily drawn to scale:
The ensuing description provides embodiments only, and is not intended to limit the scope, applicability, or configuration of the claims. Rather, the ensuing description will provide those skilled in the art with an enabling description for implementing the described embodiments. It being understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the appended claims.
Various aspects of the present disclosure will be described herein with reference to drawings that are schematic illustrations of idealized configurations. As such, variations from the shapes of the illustrations as a result, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the various aspects of the present disclosure presented throughout this document should not be construed as limited to the particular circuit elements illustrated and described herein but are to include deviations in circuits and functionally-equivalent circuit components.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this disclosure.
As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise,” “comprises,” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The term “and/or” includes any and all combinations of one or more of the associated listed items.
It is with respect to the above-described shortcomings of DAC circuits that embodiments of the present disclosure were contemplated. In some embodiments, an offset cancellation method and system are disclosed. While embodiments of the present disclosure will be described in connection with a particular configuration of an amplifier circuit, it should be appreciated that the claims are not so limited. Indeed, embodiments of the present disclosure can be utilized to improve the capabilities of any circuit having offset issues such as amplifier circuits. More specific examples of the types of amplifier circuits that may benefit from the disclosed two-phase offset method and system include, without limitation, ADC circuits, DAC circuits, voltage amplifiers, sample-and-hold circuits, and combinations thereof.
Referring now to
The main amplifier circuit 208 passes the input signal 212 through its circuit components and produces an output signal 216. The output signal 216 may correspond to an amplified version of the input signal 212, a digital version of the input signal 212, an analog version of the input signal 212, or the like.
The output signal 216 is also sampled by the two-phase output sampler 220, which samples the output signal 216 over two different clock phases φ1 and φ2. The two-phase output sampler 220 is further configured to obtain or determine a difference in the output signal 216 for the two clock phases. This delta or difference is then integrated over time by the integrator 224. The output of the integrator 224 is provided to the offset correction circuit 228 in a feedback loop to the main amplifier circuit 208, thereby allowing the integration of the delta to correct the main amplifier circuits 208 offset. By removing or reducing the amplifier offset in the main amplifier circuit 208, the pedestal in the output voltage Vout (one example of the output signal 216) will be correspondingly reduced. In some embodiments, the clock phases φ1 and φ2 are synchronized with the main amplifier circuit's 208 sample and hold modes, respectively. In this way, error amplifier offset storage occurs during the circuit's 208 sample mode, when the output voltage Vout of the amplifier circuit 208 has been offset-nulled; and when the circuit 208 goes into the hold mode of operation, which is when the amplifier offset is present at the output voltage Vout, the error amplifier goes into operation to cancel out the circuit's 208 amplifier offset, thereby removing the pedestal in the output voltage Vout.
With reference now to
During a first clock phase φ1 the first switches S1 (in both modules 408, 412) may be in an ON or closed position whereas the second switches S2 (in both modules 408, 412) may be in an OFF or open position. The OTA mode during this first clock phase φ1 can be considered a unity feedback mode and the OTA is producing an OTA offset. This causes the first capacitor C1 to store voltage that is approximately equal to the output voltage during the first clock phase Vout(φ1) plus the OTA offset (e.g., voltage across C1=Vout(φ1)+OTA offset). Also during this first clock phase φ1 the second capacitor C2 positioned between the amplification module 408 and the offset correction module 412 stores the last auxiliary output Vaux measured during the previous clock phase (e.g., immediately previous second clock phase φ2). In this embodiment, the amplification module 408, if operating as a sample-and-hold DAC, may be considered to be in a sample mode of operation.
During the second clock phase φ2 the first switches S1 may switch to an OFF or open position whereas the second switches S2 may switch to an ON or closed position. The OTA mode during this second clock phase φ2 can be considered an error amplification mode of operation and the OTA is producing an output approximately equal to Vout(φ2) minus Vout(φ1). This OTA output causes the first capacitor C1 to discharge and then the second capacitor C2 stores the current auxiliary output Vaux during the second clock phase φ2. This operation also removes the offset of the OTA. In this embodiment, the amplification module 408, if operating as a sample-and-hold DAC, may be considered to be in a hold mode of operation.
With reference now to
In some embodiments, the auxiliary input Vaux provided to the amplifier 416 will see an input level Vaux that is approximately Vos(DAC)×[gm(DAC)/gm(aux)], where gm(DAC) corresponds to the transconductance of the amplifier 416 and gm(aux) corresponds to the transconductance of the OTA when operating as the auxiliary amplifier. The auxiliary input Vaux will reach above level in a Δt=Vos(DAC)/{[gm(error amp)/C2]×[Vout(Φ2)−Vout(Φ1)]×[gm(aux)/gm(DAC)]}. The transconductance gm of the auxiliary amplifier (e.g., the OTA) is made much smaller (e.g., ten times smaller) than the amplifier's 416 transconductance to ensure that the auxiliary input does not significantly reduce the transconductance of the amplifier 416, thereby degrading the amplifier's 416 loop-gain. Having the transconductance of the auxiliary amplifier smaller than the transconductance of the amplifier 416 also decreases the sensitivity of the auxiliary amplifier from input noise. The ratio of the amplifier's 416 transconductance to the auxiliary amplifier's transconductance also contributes to the overall steady state error in the output voltage Vout as shown in Table 2 below, where it should be noted that the Voffs(DAC) is approximately the effective offset stored in capacitors Cs, Cint or effective offset stored during the DAC self-nulling phase/hold phase.
Offset in the auxiliary amplifier is naturally cancelled through the same auxiliary offset cancellation loop. This occurs because any offset present in the auxiliary amplifier would present itself as offset in the amplifier 416, scaled by a factor of αm (ratio of DAC amplifier to auxiliary amplifier Gm). The total offset at the input of the amplifier 416 before nulling would be approximately equal to Vos(DAC)−{Vos(aux)×[gm(aux)/gm(main)]}. An illustration of the correction process is shown in Table 1 below, assuming that the auxiliary input Vaux begins at an incorrect level Vaux(0), with a pre-existing charge in Cs and Cint, which results in an erroneous output voltage Vout in the first sample mode of (V01−ΔVe):
One of the major sources of error to the nulling system is the delta change in charge stored in the first capacitor C1, when the OTA amplifier switches over from a unity gain amplifier to an error amplifier, due to a combination of MOS switch charge injection, sampled noise, and leakage current. To reduce the level of charge injection, a dummy switch that is switched in opposite phases from the error amplifier's unity feedback switch is connected to the negative terminal of the error amplifier. The other source of error is the delta change in charge stored on the second capacitor C2, when the holding capacitor Ch disconnects from the output of the error amplifier, thereby allowing the error amplifier to perform its own offset storage plus sampling of the amplifier 416 output Vout during the DAC hold mode. The steady-state error in the Vout pedestal and absolute Vout level are shown in Table 2 below.
Charge storage deltas in the second capacitor C2 can be seen to contribute to a steady-state error in the absolute level of the amplification module's 408 output, Vo1, while delta changes in the first capacitor C1 limit the pedestal error correction. Close to minimum size switches (w/1=1.2 u/0.5 u) are used to minimize leakage levels. Dummy switches as described above can be employed. A larger am would also counter the effects of charge injection at the second capacitor C2. Capacitors C1 and C2 are sized to give overall pedestal and absolute level errors of acceptable range. Pedestal errors are kept well within 1 mV across corners, while absolute level errors can be maintained within approximately LSB/4 level. For a minimum reference voltage Vref of 2V, at 10-bit output resolution, the LSB/4 would be approximately 488 uV. In such an illustrative system, the capacitors C1 and C2 could be silicon-implementable, at 4 pF and 8 pF, respectively, to fulfill the above steady-state error requirements, at a DAC sample and hold rate of approximately 70 kHz.
An actual simulation result showing a zeroing in the Vout pedestal with an artificially added 20 mV offset in the DAC amplifier input, 20 mV offset in the auxiliary amplifier input and 20 mV offset in the OTA input is shown in
The scheme described in connection with
With reference now to
Theoretically, capacitors C2A and C2B could have been replaced by a single capacitor across the differential outputs of the OTA. However, unlike the single capacitor configuration, the supply rejection of the auxiliary voltage is dependent on the supply rejection of the common mode voltage, unlike in a double capacitor configuration, where the two capacitors to ground naturally keep the auxiliary voltage ground-referenced, thereby causing the circuit 704 to be less sensitive to ground variations. In
Charge injection at capacitors C1A/C1B occurs when switches S1A/S1B go from ON or closed to OFF or open. For the same switch sizes the same delta charge is injected into capacitor C1A and capacitor C1B, hence creating the same ΔV error on both capacitor C1A and capacitor C1B. The same is true with respect to capacitor C2A and capacitor C2B when switches S2A/S2B go from ON to OFF. Given the differential nature of the configuration, the ΔV error on capacitors C1A and C1B cancel out each other and is no longer visible on the differential input voltage seen by the OTA. Again, because the differential output of the OTA is used as the auxiliary input for amplifier 716 offset cancellation, it is immune to the ΔV error on C2A and C2B.
Specific details were given in the description to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments.
While illustrative embodiments of the disclosure have been described in detail herein, it is to be understood that the inventive concepts may be otherwise variously embodied and employed, and that the appended claims are intended to be construed to include such variations, except as limited by the prior art.
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