The present disclosure relates to semiconductor structures and, more particularly, to a back-gate controlled varactor and methods of use and manufacture.
Varactors are used in voltage-controlled oscillators (VCO) for frequency tuning, where the VCO frequency is tuned by a control voltage. Voltage-controlled oscillators have many applications such as frequency modulation for FM transmitters and phase-locked loops. Phase-locked loops can be used for frequency synthesizers that tune, for example, cellular telephones or other wireless devices.
Diode based varactors are operated in a reverse-biased state, where the amount of reverse bias controls the thickness of the depletion zone and therefore the varactor's junction capacitance. The capacitance is inversely proportional to the square root of applied voltage. Conventional MOS based varactors are operated in either accumulation mode or inversion mode. The gate capacitance is a function of the relative gate bias. That is, varactors show capacitance as function of control voltage (C-V curve). By way of example, an LC (inductor/capacitor)-tank based VCO has output frequency as function of the varactor capacitance.
Conventional varactors exhibit high gain, noise, AC coupling and limited control voltage range. More specifically, a conventional Metal-Oxide-Semiconductor Capacitor (MOSCAP) based varactor uses Vgs voltage as the control voltage, which has a C-V curve with a steep slope. The capacitance value is sensitive to control voltage level, with the VCO gain (Kv) being high. Additionally, VCO phase noise is sensitive to the control voltage noise due to high gain. Moreover, to bias the MOSCAP based varactor, AC coupling capacitors and DC coupling resistors are required on the gates of the MOSCAP device, which increases the design complexity, area, and parasitic capacitance. The resistors also contribute to the noise. Lastly, the MOSCAP based varactor has small control voltage range which is limited by the reliability constrain on the gates.
In an aspect of the disclosure, a varactor comprises: a plurality of transistors arranged in parallel; a voltage controlled node coupled to back-gates of the plurality of transistors; and a biasing voltage node coupled to the source and drain of the plurality of transistors.
In an aspect of the disclosure, a varactor comprises: a voltage controlled node directly coupled to back-gates of a pair of transistors to achieve gate capacitance tuning; and a biasing voltage node directly coupled to the source and drain of the transistors. The transistors are back-gate controlled by a voltage applied at the voltage controlled node.
In an aspect of the disclosure, a method of using a varactor comprises applying threshold voltage dependence on a back-gate bias of the varactor to achieve gate capacitance tuning.
The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.
The present disclosure relates to semiconductor structures and, more particularly, to a back-gate controlled varactor and methods of use and methods of manufacture. More specifically, the present disclosure provides a varactor which uses a back-gate as the voltage control (VCTRL) node. Advantageously, the back-gate controlled varactor exhibits low noise, low gain, capability of direct coupling to a VCO and wide control voltage range, compared to conventional varactors.
In embodiments, the back-gate controlled varactor described herein uses threshold voltage dependence on the back-gate bias to achieve gate capacitance tuning. In addition, the front-gates (transistors) of the varactor can be directly coupled to an LC-tank of a VCO (without coupling resistors or coupling capacitors), where the VCO uses the back-gate controlled varactor. For example, the back-gate controlled varactor can be used with a 60 GHz VCO which is suitable for 5G 28 GHz band local oscillator (LO) generation. In operation, the VCO inductor center tap voltage provides the varactor front-gates DC bias. In addition, in operation, the varactor C-V curve can be adjusted by a bias voltage (VS).
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Capacitance tuning of the back-gate controlled varactor 100 is achieved by changing the threshold voltage of the transistors N0, N1 through adjusting the back-gate bias, which creates a varactor C-VBB curve. In the back-gate controlled varactor 100 described herein, capacitance is less sensitive to the back-gate voltage VBB compared to a conventional front-gate voltage controlled varactor. This, in turn, allows the back-gate controlled varactor 100 to exhibit low gain and higher range (compared to conventional front gate biased varactors). The varactor gain can also be adjusted by using different VS bias.
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Accordingly, by using the back-gate controlled varactor 100 it is now possible to provide low gain, low noise, direct coupling to a VCO and wide control voltage range. For example, the low gain is due to the varactor capacitance being less sensitive to the back-gate voltage. Low noise is due to the voltage line noise being suppressed due to low VCO gain. The varactor can be directly coupled to an LC tank of a VCO, since no AC coupling capacitors or DC coupling resistors are required. This saves considerable area, reduces parasitic capacitance, extends tuning range and achieves low noise. In addition, the back-gate controlled varactor exhibits a wide control voltage range due to the back-gate having a very high breakdown voltage.
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The back-gate controlled varactor of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the back-gate controlled varactor of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the back-gate controlled varactor uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.
The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.