Patent Application
20250176255
For the past several decades, the scaling of features in integrated circuit (IC) structures has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize every portion of an IC structure becomes increasingly significant.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
cross-sectional side views at various stages in the fabrication of an example IC structure according to the method of
Disclosed herein is a fabrication method including back-side nanoribbon removal and associated IC structures, and devices. The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
For purposes of illustrating fabrication of nanoribbon-based transistors using back-side nanoribbon removal, described herein, it might be useful to first understand phenomena that may come into play during IC fabrication. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.
Non-planar transistors such as double-gate transistors, tri-gate transistors, FinFETs, and nanowire/nanoribbon/nanosheet transistors refer to transistors having a non-planar architecture. In comparison to a planar architecture where the transistor channel has only one confinement surface, a non-planar architecture is any type of architecture where the transistor channel has more than one confinement surface. A confinement surface refers to a particular orientation of the channel surface that is confined by the gate field. Non-planar transistors potentially improve performance relative to transistors having a planar architecture, such as single-gate transistors.
Nanoribbon-based transistors may be particularly advantageous for continued scaling of metal-oxide-semiconductor (MOS) technology nodes due to the potential to form gates on all four sides of a channel material (hence, such transistors are sometimes referred to as “gate all around” transistors). As used herein, the term “nanoribbon” refers to an elongated structure of a semiconductor material having a longitudinal axis parallel to a support structure (e.g., a substrate, a die, a chip, or a wafer; also referred to herein as, simply, “support”) over which such a structure is built. Typically, a length of a such a structure (i.e., a dimension measured along the longitudinal axis, shown in the present drawings to be along the y-axis of an example x-y-z coordinate system) is greater than each of a width (i.e., a dimension measured along the x-axis of the example coordinate system shown in the present drawings) and a thickness (i.e., a dimension measured along the z-axis of the example coordinate system shown in the present drawings). In some settings, the terms “nanoribbon” or “nanosheet” have been used to describe elongated semiconductor structures that have a rectangular transverse cross-section (i.e., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term “nanowire” has been used to describe similar elongated structures but with circular transverse cross-sections. In the present disclosure, the term “nanoribbon” is used to refer to all such nanowires, nanoribbons, and nanosheets, as well as elongated semiconductor structures with a longitudinal axis parallel to the support structures and with having transverse cross-sections of any geometry (e.g., transverse cross-sections in the shape of an oval or a polygon with rounded corners). A transistor may then be described as a “nanoribbon-based transistor” if the channel of the transistor is a portion of a nanoribbon, i.e., a portion around which a gate stack of a transistor may wrap around. The semiconductor material in the portion of the nanoribbon that forms a channel of a transistor may be referred to as a “channel material,” with source and drain (S/D) regions of a transistor provided on either side of the channel material.
Typically, nanoribbon-based transistor arrangements include stacks of nanoribbons, where each stack includes two or more nanoribbons stacked above one another, with a single gate stack that includes a gate electrode material provided for an entire stack or multiple stacks. Optionally, the gate stack may also include a gate dielectric material around one or more channel regions of each nanoribbon.
Different applications for nanoribbon transistors may have different desired electrical characteristics and performance targets. For example, devices used in lower power applications are typically designed to minimize power consumption, while devices used in high performance applications may be designed to maximize speed. Various factors affect the power consumption and speed of a transistor. For example, in nanoribbon transistor technology, one technique for fabricating different transistors for low-power or high-performance applications is to use different nanoribbon widths. For example, a larger nanoribbon width can enable increased current conduction through the transistor for higher performance devices. A smaller nanoribbon width can enable reduced current conduction through the transistor for lower power applications.
Fabricating devices having different nanoribbon widths can be challenging due to width constraints (e.g., the minimum and maximum nanoribbon widths) due to process and yield limitations. For example, forming nanoribbons with an excessively large width can result in low yield due to the proximity of the metal gate to the nanoribbon edge. Similarly, fabricating nanoribbons with an excessively small width can result in yield issues due to the fin being easily damaged or broken (e.g., during fin patterning).
Another challenge in providing devices having different nanoribbon widths stems from differences in processing results for nanoribbons having different widths. Devices having different nanoribbon widths may be formed on the same wafer, however, the same processes can yield different results for openings with narrow widths compared to openings with wider widths. For example, in an etching process, fewer etchants may reach the bottom of a narrow opening than of a wide opening, resulting in a different etch rate. The phenomenon of such width-dependent process differences may be referred to as micro-loading and can result in geometry differences in the final devices. Improving uniformity in the geometry of devices having different nanoribbon widths can require significant additional processing.
In contrast, back-side nanoribbon removal techniques can enable the fabrication of nanoribbon transistors for both high performance and low-power applications while minimizing some of the width-dependent process challenges that can result from different nanoribbon widths. In one example, back-side nanoribbon removal involves providing stacks of nanoribbons from a first side (referred to herein as a front side) of the IC structure, followed by removing one or more of the nanoribbons from a second side that is opposite the first side (referred to herein as a back side). In one example, an IC structure fabricated with back-side nanoribbon removal techniques includes a first stack of nanoribbons over a support and a second stack of nanoribbons over the support, where the number of nanoribbons in the first stack is less than in the second stack (e.g., due to back-side removal of one or more nanoribbons from the first stack). A first transistor includes first channel regions in the nanoribbons of the first stack and a second transistor includes second channel regions in the nanoribbons of the second stack. Therefore, in one such example, the first transistor has channel regions in fewer nanoribbons than the second transistor.
IC structures as described herein, in particular IC structures fabricated using back-side nanoribbon removal techniques, may be implemented in one or more components associated with an IC or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on an IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. In some embodiments, IC structures as described herein may be included in a radio frequency IC (RFIC), which may, e.g., be included in any component associated with an IC of a radio frequency (RF) receiver, an RF transmitter, or an RF transceiver, e.g., as used in telecommunications within base stations (BS) or user equipment (UE). Such components may include, but are not limited to, power amplifiers, low-noise amplifiers, RF filters (including arrays of RF filters, or RF filter banks), switches, upconverters, downconverters, and duplexers. In some embodiments, IC structures as described herein may be included in memory devices or circuits. In some embodiments, IC structures as described herein may be employed as part of a chipset for executing one or more related functions in a computer.
For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details or/and that the present disclosure may be practiced with only some of the described aspects. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value, e.g., within +/−5% of a target value, based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−10% of a target value, e.g., within +/−5% of a target value, based on the context of a particular value as described herein or as known in the art.
In the following description, references are made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, if a collection of drawings designated with different letters are present, e.g.,
In the drawings, while some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, this is simply for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the fabricating processes used to fabricate semiconductor device assemblies. Therefore, it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of the presence of IC structures fabricated using back-side nanoribbon techniques as described herein.
Various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the terms “oxide,” “carbide,” “nitride,” “silicide,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, silicon, etc.; the term “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide; the term “low-k dielectric” refers to a material having a lower dielectric constant than silicon oxide. Materials referred to herein with formulas or as compounds cover all materials that include elements of the formula or a compound, e.g., TiSi or titanium silicide may refer to any material that includes titanium and silicon, WN or tungsten nitride may refer to any material that includes tungsten and nitrogen, etc. The term “insulating” means “electrically insulating,” the term “conducting” means “electrically conducting,” unless otherwise specified. Furthermore, the term “connected” may be used to describe a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” may be used to describe either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. A first component described to be electrically coupled to a second component means that the first component is in conductive contact with the second component (i.e., that a conductive pathway is provided to route electrical signals/power between the first and second components).
Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. These operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. The terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. Although some materials may be described in singular form, such materials may include a plurality of materials, e.g., a semiconductor material may include two or more different semiconductor materials.
Implementations of the present disclosure may be formed or carried out on any suitable support 102, such as a substrate, a die, a wafer, or a chip. The support 102 may, e.g., be the wafer 1500 of
The nanoribbon 104 may take the form of a nanowire or nanoribbon, for example. In some embodiments, an area of a transversal cross-section of the nanoribbon 104 (i.e., an area in the x-z plane of an x-y-z coordinate system shown in
In various embodiments, the semiconductor material of the nanoribbon 104 may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the nanoribbon 104 may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the nanoribbon 104 may include a combination of semiconductor materials. In some embodiments, the nanoribbon 104 may include a monocrystalline semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, the nanoribbon 104 may include a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb).
For some example N-type transistor embodiments (i.e., for the embodiments where the transistor 110 is an N-type metal-oxide-semiconductor (NMOS) transistor), the channel material of the nanoribbon 104 may include a III-V material having a relatively high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material of the nanoribbon 104 may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InxGa1-xAs fin embodiments, In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In0.7Ga0.3As). For some example P-type transistor embodiments (i.e., for the embodiments where the transistor 110 is a P-type metal-oxide-semiconductor (PMOS) transistor), the channel material of the nanoribbon 104 may advantageously be a group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material of the nanoribbon 104 may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7.
In some embodiments, the channel material of the nanoribbon 104 may be a thin-film material, such as a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, if the transistor formed in the nanoribbon is a thin-film transistor (TFT), the channel material of the nanoribbon 104 may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, and black phosphorus, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. In some embodiments, the channel material of the nanoribbon 104 may have a thickness between about 5 and 75 nanometers, including all values and ranges therein. In some embodiments, a thin-film channel material may be deposited at relatively low temperatures, which allows depositing the channel material within the thermal budgets imposed on back-end fabrication to avoid damaging other components, e.g., front-end components such as the logic devices.
A gate stack 106 including a gate electrode material 108 and, optionally, a gate insulator material 112, may wrap entirely or almost entirely around a portion of the nanoribbon 104 as shown in
The gate electrode material 108 may include one or more gate electrode materials, where the choice of the gate electrode materials may depend on whether the transistor 110 is a PMOS transistor or an NMOS transistor. For a PMOS transistor, gate electrode materials that may be used in different portions of the gate electrode material 108 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, gate electrode materials that may be used in different portions of the gate electrode material 108 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode material 108 may include a stack of a plurality of gate electrode materials, where zero or more materials of the stack are workfunction (WF) materials and at least one material of the stack is a fill metal layer. Further materials/layers may be included next to the gate electrode material 108 for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer.
In some embodiments, the gate insulator material 112 may include one or more high-k dielectrics including any of the materials discussed herein with reference to the insulator material that may surround portions of the transistor 110. In some embodiments, an annealing process may be carried out on the gate insulator material 112 during fabrication of the transistor 110 to improve the quality of the gate insulator material 112. The gate insulator material 112 may have a thickness that may, in some embodiments, be between about 0.5 nanometers and 3 nanometers, including all values and ranges therein (e.g., between about 1 and 3 nanometers, or between about 1 and 2 nanometers). In some embodiments, the gate stack 106 may be surrounded by a gate spacer, not shown in
Turning to the S/D regions 114 of the transistor 110, in some embodiments, the S/D regions may be highly doped, e.g., with dopant concentrations of about 1021 cm7 −3, in order to advantageously form Ohmic contacts with the respective S/D contacts (not shown in
The S/D regions 114 of the transistor 110 may generally be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the nanoribbon 104 to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the nanoribbon 104 may follow the ion implantation process. In the latter process, portions of the nanoribbon 104 may first be etched to form recesses at the locations of the future S/D regions 114. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 114. In some implementations, the S/D regions 114 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the S/D regions 114 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 114. In some embodiments, a distance between the first and second S/D regions 114 (i.e., a dimension measured along the longitudinal axis 120 of the nanoribbon 104) may be between about 5 and 40 nanometers, including all values and ranges therein (e.g., between about 22 and 35 nanometers, or between about 20 and 30 nanometers).
The IC structure 100 shown in
In the example illustrated in
Although the term “stack” typically refers to multiple nanoribbons stacked over one another, references to a stack of nanoribbons herein may refer to a single nanoribbon (e.g., a stack of nanoribbons in which all but one of the nanoribbons were removed). For example, a first stack of nanoribbons may have a single nanoribbon and a second stack may have a number of nanoribbons greater than one (e.g., two, three, four, or more than four nanoribbons). In another example, a first stack of nanoribbons has two nanoribbons, and a second stack may have a number of nanoribbons greater than two (e.g., three, four, or more than four nanoribbons). Various combinations are possible as long as at least one stack of nanoribbons (e.g., the stack 278-1) has at least one fewer nanoribbon than a second stack of nanoribbons (e.g., the stack 278-2). Although only two stacks 278-1, 278-2 are shown, in other examples, an IC structure can include three or more stacks of nanoribbons having different numbers of nanoribbons. For example, one stack may include one nanoribbon, a second stack may include two nanoribbons, a third stack may include three nanoribbons, etc.
Additionally, although the stacks 278-1, 278-2 are depicted as being adjacent stacks (separated by a via 231), the stacks of nanoribbons having different numbers of nanoribbons may not necessarily be adjacent to one another. Although the stacks 278-1, 278-2 may not necessarily be adjacent to one another, the stacks 278-1, 278-2 include nanoribbons in the same planes or layers. For example, the IC structure 200 includes a stack 278-2 of nanoribbons over the support 290, including a first nanoribbon (e.g., the nanoribbon 293-2) in a first plane substantially parallel to the support 290 and a second nanoribbon (e.g., the nanoribbon 293-3) stacked over the first nanoribbon in a second plane substantially parallel to the support 290. The IC structure 200 also includes a third nanoribbon over the support (e.g., the nanoribbon 203-1) in the same plane as the nanoribbon 293-3. Thus, in one example, an individual nanoribbon of the first stack is in a substantially same layer as a corresponding individual nanoribbon of the second stack. However, the IC structure 200 does not include a nanoribbon under the nanoribbon 203-1 in the same plane or layer with the nanoribbon 293-2 (e.g., due to removal of the nanoribbon that was previously stacked under the nanoribbon 203-1). Instead, in one example, the IC structure 200 includes an insulator material (e.g., the insulator material 285 and/or the liner 283) under the nanoribbon 203-1 in substantially the same plane as the nanoribbon 293-2.
In addition to the different numbers of nanoribbons in the stacks 278-1, 278-2, the IC structure 200 depicted in
Also as shown in
Transistors having different numbers of nanoribbons may be formed in the stacks 278-1, 278-2. For example, the nanoribbons 203-1, 203-2 include channel regions of a first transistor, and the nanoribbons 293-1-293-4 in the stack 478-2 include channel regions of a second transistor. Thus, the transistors formed from the stacks 278-1, 278-2 of nanoribbons may have channel regions in a different number of nanoribbons. Transistors having channel regions in different numbers of nanoribbons may have different properties that make the transistors more suitable for low-power or high-performance applications. For example, a transistor with channel regions in two nanoribbons (such as in the stack 278-1) may conduct less (e.g., about half) as much current as a transistor with channel regions in four nanoribbons (such as in the stack 278-2). The additional insulator material under the stack with fewer nanoribbons (such as the stack 278-1) may also result in a transistor with lower capacitance than a transistor formed in a stack with more nanoribbons (such as the stack 278-2). Thus, different transistors for low-power or high-performance applications can be formed with different numbers of nanoribbons. Note that transistors having different numbers of nanoribbons may have the same or different nanoribbons widths. Thus, in some examples, transistors having a variety of electrical characteristics may be fabricated by adjusting the number of nanoribbons and the width of the nanoribbons in which the transistors are formed.
Although the operations of the method of
In addition, the example fabricating method of
Turning to
For example, the IC structure 404 of
As shown in
The semiconductor material 432 may be any of the semiconductor/channel materials described above with reference to the nanoribbon 104 of
Thus, the material 434 may be any suitable sacrificial material that is etch-selective with respect to the semiconductor material 432. Selecting the material 434 to be a semiconductor material may be particularly advantageous because it may improve quality of the semiconductor material 432 if the semiconductor material 432 is epitaxially grown on the material 434. In some embodiments, the process 302 may include epitaxially growing layers of the semiconductor material 432 and the material 434 (e.g., a second semiconductor material) in an alternating manner. In other embodiments, alternate layers of the semiconductor material 432 and the material 434 may be provided in the process 302 using other techniques, such as layer transfer or thin-film deposition. Although
Thus, each of the fins 440-1, 440-2 may be shaped as a structure that extends away from the support 401 and may include a subfin 442-1, 442-2 at the bottom, the subfin being a portion of the respective fin that is at least partially enclosed by an insulator material 436. In some embodiments, the subfins 442-1, 442-2 may include the bottom layer of the semiconductor material 432, as well as an upper portion of the support 401, as is shown in
In some embodiments, the fins 440-1, 440-2 may have widths (i.e., a dimension of the fins 440-1, 440-2 measured along the x-axis of the example coordinate system shown in
In various embodiments, any suitable patterning techniques may be used to form the fins 440-1, 440-2, such as, but not limited to, photolithographic or electron-beam (e-beam) patterning, possibly in conjunction with a suitable etching technique, e.g., a dry etch, such as e.g., RF reactive ion etch (RIE) or inductively coupled plasma (ICP) RIE. In some embodiments, the etch performed to form the fins 440-1, 440-2 may include an anisotropic etch, using etchants in a form of e.g., chemically active ionized gas (i.e., plasma) using e.g., bromine (Br) and chloride (Cl) based chemistries. In some embodiments, during the etch to form the fins 440-1, 440-2, the IC structure may be heated to elevated temperatures, e.g., to temperatures between about room temperature and 200 degrees Celsius, including all values and ranges therein, to promote that byproducts of the etch are made sufficiently volatile to be removed from the surface.
After forming the fins 440-1, 440-2, a dummy gate material may then be provided around gate regions of the fins.
Referring again to
The method can then involve the process of removing the dummy gate material and releasing the nanoribbons.
Referring again to
In some examples, a conductive via may be formed between adjacent stacks of nanoribbons.
Referring again to
The method 300 continues with the process 312 of providing a liner in the openings. An IC structure 413 of
Turning now to
Referring again to
Turning first to
In examples in which multiple nanoribbons are to be removed, removal of the nanoribbons may involve cyclically etching an insulator material (e.g., the gate insulator material), a conductive material (e.g., the gate electrode material), and a semiconductor material (e.g., the semiconductor material of the nanoribbons to be removed).
The method 300 may then continue with removing the semiconductor material 432 of the nanoribbon 403-2. An IC structure 418 of
In one example, etching the semiconductor material of one or more of nanoribbons may result in etching (unintentionally or intentionally) a semiconductor material of a source region and/or a drain region adjacent to the semiconductor material of the nanoribbon(s) being removed. For example,
After removal of one or more nanoribbons, the portions 477 of the S/D regions 459-1, 459-2 that were adjacent to the removed nanoribbons may be “dummy” portions of the S/D regions 459-1, 459-2 in the sense that those portions 477 may not function as source/drain regions during operation of the device. Thus, removal of at least part of the dummy portions of the S/D regions will generally not negatively impact operation of the device and may even have the advantage of reducing capacitance. Therefore, recessing of the S/D material 470 in the portions 477 where nanoribbons were removed may be intentional or a side effect of the etching processes used to remove the nanoribbons. In some examples in which the S/D material 470 is intentionally etched in the areas where nanoribbons were removed, a larger portion of the S/D regions 459-1, 459-2 may be removed than what is depicted in
The percentage of the portions 477 of the S/D regions 459-1, 459-2 that is removed may depend on a number of factors including the etching processes used to remove the nanoribbons. Excessive etching of the portions 477 of the S/D regions may cause the remaining S/D material of the portions 477 to become structurally unstable (e.g., due to the lack of adjacent structure resulting from the removal of nanoribbons). Additionally, excessive etching of the S/D material 470 close to the remaining nanoribbons of the stack 478-1 may negatively impact the operation of the resulting device. Accordingly, it may be desirable to not entirely remove S/D material 470 in the portions 477 of the S/D regions 459-1, 459-2 that were adjacent to the removed nanoribbons.
Referring again to
Referring to
The IC structures 420, 421 and all variations of such structures described herein are examples of the IC structures 100 and 200, described above. Performing the method 300 may result in features in the final IC structures that are characteristic of the use of the method 300. For example, one such feature is illustrated in the IC structures 420, 421 shown in
Other features may be present in the IC structures resulting from back-side nanoribbon removal, such as differences in thickness in the liner under the stacks of nanoribbons, and the thickness or height of the insulator material 485 under the stacks 478-1, 478-2. In the example illustrated in
IC structures fabricated using back-side nanoribbon removal techniques as described herein (e.g., as described with reference to
The IC structures disclosed herein, e.g., the IC structures 100, 200, 420, and 421 may be included in any suitable electronic component.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., the transistors) of the device region 1604 through one or more interconnect layers disposed on the device region 1604 (illustrated in
The interconnect structures 1628 may be arranged within the interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1628 depicted in
In some embodiments, the interconnect structures 1628 may include lines 1628a and/or vias 1628b filled with an electrically conductive material such as a metal. The lines 1628a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the support 102 upon which the device region 1604 is formed. For example, the lines 1628a may route electrical signals in a direction in and out of the page from the perspective of
The interconnect layers 1606-1610 may include a dielectric material 1626 disposed between the interconnect structures 1628, as shown in
A first interconnect layer 1606 may be formed above the device region 1604. In some embodiments, the first interconnect layer 1606 may include lines 1628a and/or vias 1628b, as shown. The lines 1628a of the first interconnect layer 1606 may be coupled with contacts (e.g., contacts to the S/D regions 114 of the IC structure 100) of the device region 1604.
A second interconnect layer 1608 may be formed above the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b to couple the lines 1628a of the second interconnect layer 1608 with the lines 1628a of the first interconnect layer 1606. Although the lines 1628a and the vias 1628b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1608) for the sake of clarity, the lines 1628a and the vias 1628b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
A third interconnect layer 1610 (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1608 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 1619 in the IC device 1600 (i.e., farther away from the device region 1604) may be thicker.
The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606-1610. In
The package substrate 1652 may be formed of a dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, glass, an organic material, an inorganic material, combinations of organic and inorganic materials, embedded portions formed of different materials, etc.), and may have conductive pathways extending through the dielectric material between the face 1672 and the face 1674, or between different locations on the face 1672, and/or between different locations on the face 1674. These conductive pathways may take the form of any of the interconnects 1628 discussed above with reference to
The package substrate 1652 may include conductive contacts 1663 that are coupled to conductive pathways (not shown) through the package substrate 1652, allowing circuitry within the dies 1656 and/or the interposer 1657 to electrically couple to various ones of the conductive contacts 1664 (or to devices included in the package substrate 1652, not shown).
The IC package 1650 may include an interposer 1657 coupled to the package substrate 1652 via conductive contacts 1661 of the interposer 1657, first-level interconnects 1665, and the conductive contacts 1663 of the package substrate 1652. The first-level interconnects 1665 illustrated in
The IC package 1650 may include one or more dies 1656 coupled to the interposer 1657 via conductive contacts 1654 of the dies 1656, first-level interconnects 1658, and conductive contacts 1660 of the interposer 1657. The conductive contacts 1660 may be coupled to conductive pathways (not shown) through the interposer 1657, allowing circuitry within the dies 1656 to electrically couple to various ones of the conductive contacts 1661 (or to other devices included in the interposer 1657, not shown). The first-level interconnects 1658 illustrated in
In some embodiments, an underfill material 1666 may be disposed between the package substrate 1652 and the interposer 1657 around the first-level interconnects 1665, and a mold compound 1668 may be disposed around the dies 1656 and the interposer 1657 and in contact with the package substrate 1652. In some embodiments, the underfill material 1666 may be the same as the mold compound 1668. Example materials that may be used for the underfill material 1666 and the mold compound 1668 are epoxy mold materials, as suitable. Second-level interconnects 1670 may be coupled to the conductive contacts 1664. The second-level interconnects 1670 illustrated in
The dies 1656 may take the form of any of the embodiments of the die 1502 discussed herein (e.g., may include any of the embodiments of the IC device 1600). In embodiments in which the IC package 1650 includes multiple dies 1656, the IC package 1650 may be referred to as a multi-chip package (MCP). The dies 1656 may include circuitry to perform any desired functionality. For example, or more of the dies 1656 may be logic dies (e.g., silicon-based dies), and one or more of the dies 1656 may be memory dies (e.g., high-bandwidth memory).
Although the IC package 1650 illustrated in
In some embodiments, the circuit board 1702 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate.
The IC device assembly 1700 illustrated in
The package-on-interposer structure 1736 may include an IC package 1720 coupled to a package interposer 1704 by coupling components 1718. The coupling components 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1716. Although a single IC package 1720 is shown in
In some embodiments, the package interposer 1704 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the package interposer 1704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the package interposer 1704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The package interposer 1704 may include metal lines 1710 and vias 1708, including but not limited to through-silicon vias (TSVs) 1706. The package interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the package interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 1700 may include an IC package 1724 coupled to the first face 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with reference to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.
The IC device assembly 1700 illustrated in
Additionally, in various embodiments, the electrical device 1800 may not include one or more of the components illustrated in
The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include a memory 1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic RAM (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded dynamic RAM (eDRAM) or spin transfer torque magnetic RAM (STT-MRAM).
In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 1812 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1812 may operate in accordance with other wireless protocols in other embodiments. The electrical device 1800 may include an antenna 1822 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1812 may include multiple communication chips. For instance, a first communication chip 1812 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1812 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1812 may be dedicated to wireless communications, and a second communication chip 1812 may be dedicated to wired communications.
The electrical device 1800 may include battery/power circuitry 1814. The battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).
The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may be in communication with a satellite-based system and may receive a location of the electrical device 1800, as known in the art.
The electrical device 1800 may include an other output device 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1800 may include an other input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The electrical device 1800 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 provides an IC device including a stack of nanoribbons over a support, where the stack of nanoribbons includes a first nanoribbon in a first plane substantially parallel to the support and a second nanoribbon stacked over the first nanoribbon in a second plane substantially parallel to the support. The first nanoribbon and the second nanoribbon include channel regions of a first transistor. The IC device further includes a third nanoribbon over the support in the second plane (e.g., adjacent to the second nanoribbon), where the third nanoribbon includes a channel region of a second transistor, and an insulator material under the channel region of the second transistor in the first plane.
Example 2 provides an IC device according to example 1, where the stack of nanoribbons is a first stack of nanoribbons, where the third nanoribbon is in a second stack of nanoribbons, and where the second stack has fewer nanoribbons than the first stack.
Example 3 provides an IC device according to examples 1 or 2, further including the insulator material (e.g., a materially continuous insulator material) under the stack of nanoribbons, wherein a volume of the insulator material under the channel region of the second transistor is greater than a volume of the insulator material under the channel regions of the first transistor.
Example 4 provides an IC device according to example 3, where the insulator material is a first insulator material, and where the IC device further includes a first liner including a second insulator material (e.g., nitride liner between the nanoribbons and the bunker oxide under the stack without wires removed) between the stack of nanoribbons and the insulator material, and a second liner including the second insulator material (e.g., nitride liner between the nanoribbons and the first insulator material under the stack in which nanoribbon(s) were removed) between the third nanoribbon and the insulator material, where the first liner is thicker than the second liner.
Example 5 provides an IC device according to any one of examples 1-4, further including a region of a doped semiconductor material, where the region is either a source region or a drain region of the second transistor, and where the region includes recessed areas, where the insulator material is in the recessed areas of the region.
Example 6 provides an IC device according to example 5, where the insulator material is a first insulator material, and where the IC device further includes a second insulator material (e.g., in the dimples on sidewalls of the S/D regions where the nanoribbons have been removed) between adjacent recessed areas of the region.
Example 7 provides an IC device according to example 5, where the insulator material is a first insulator material, and where the IC device further includes a liner including a second insulator material in the recessed areas of the region between the doped semiconductor material and the first insulator material.
Example 8 provides an IC device including a first stack of nanoribbons over a support and a second stack of nanoribbons over the support, where a number of nanoribbons in the first stack is less than in the second stack, and where an individual nanoribbon of the first stack is in a substantially same layer as a corresponding individual nanoribbon of the second stack, and where the plane is substantially parallel to the support. The IC device further includes a first transistor including first channel regions in the nanoribbons of the first stack and a second transistor including second channel regions in the nanoribbons of the second stack.
Example 9 provides an IC device according to example 8, further including an insulator material under the first stack of nanoribbons in a substantially same layer with one of the nanoribbons of the second stack.
Example 10 provides an IC device of example 9, further including the insulator material under the second stack of nanoribbons, where the insulator material under the first stack of nanoribbons has a first height, the insulator material under the second stack of nanoribbons has a second height, where the first height is greater than the second height, and where the first height and the second height are dimensions substantially orthogonal to the support.
Example 11 provides an IC device according to any one of examples 8-10, further including a first insulator material under the first stack of nanoribbons and under the second stack of nanoribbons, a first liner including a second insulator material between the first stack of nanoribbons and the insulator material, and a second liner including the second insulator material between the second stack of nanoribbons and the insulator material, where the second liner is thicker than the first liner.
Example 12 provides an IC device according to any one of examples 8-11, further including a region of a doped semiconductor material, where the region is either a source region or a drain region of the first transistor, and where the region includes cavities in the doped semiconductor material, and an insulator material in the cavities.
Example 13 provides an IC device according to example 12, where the insulator material is a first insulator material, and wherein the IC device further includes a second insulator material (e.g., in the dimples on sidewalls of the S/D regions where one or more nanoribbons have been removed) between adjacent cavities.
Example 14 provides an IC device according to example 12, where the insulator material is a first insulator material, and where the IC device further includes a liner including a second insulator material in the cavities between the doped semiconductor material and the first insulator material.
Example 15 provides an IC structure including one or more nanoribbons over a support, where portions of the one or more nanoribbons include channel regions of a transistor, and a region of a doped semiconductor material, where the region is either a source region or a drain region of the transistor, and where the region includes a first portion proximate to the channel regions, and a second portion that is further from the channel regions than the first portion, where the doped semiconductor material is recessed in areas of the second portion, and where the recessed areas include an insulator material.
Example 16 provides an IC structure according to example 15, where the one or more nanoribbons are first nanoribbons and the channel regions are first channel regions of a first transistor, and where the IC structure further includes second nanoribbons stacked over one another over the support, where portions of the second nanoribbons include second channel regions of a second transistor, where the first nanoribbons include a first number of nanoribbons and the second nanoribbons include a second number of nanoribbons that is greater than the first number.
Example 17 provides an IC structure according to example 16, where the first transistor includes the first channel regions in the first number of nanoribbons and the second transistor includes the second channel regions in the second number of nanoribbons.
Example 18 provides an IC structure according to any one of examples 15-17, where the insulator material is a first insulator material, and where the IC structure further includes a second insulator material between adjacent recessed areas of the second portion.
Example 19 provides an IC structure of any one of examples 15-18, where the insulator material is a first insulator material, and where the IC device further includes a liner including a second insulator material in the recessed areas of the second portion between the doped semiconductor material and the first insulator material.
Example 20 provides an IC structure of any one of examples 15-19, where the insulator material is a first insulator material, and where the IC structure further includes a conductive material around the channel portions in the one or more nanoribbons, and a second insulator material between the channel portions and the conductive material, a liner between the first insulator material and the one or more nanoribbons, and a layer of the second insulator material between the liner and the conductive material under the one or more nanoribbons.
Example 21 provides an IC structure according to any one of examples 1-20, where the IC structure includes or is a part of a central processing unit.
Example 22 provides an IC structure according to any one of examples 1-21, where the IC structure includes or is a part of a memory device.
Example 23 provides an IC structure according to any one of examples 1-22, where the IC structure includes or is a part of a logic circuit.
Example 24 provides an IC structure or IC device according to any one of examples 1-23, where the IC structure or IC device includes or is a part of input/output circuitry.
Example 25 provides an IC structure or IC device according to any one of examples 1-24, where the IC structure or IC device includes or is a part of a field programmable gate array transceiver.
Example 26 provides an IC structure or IC device according to any one of examples 1-25, where the IC structure or IC device includes or is a part of a field programmable gate array logic.
Example 27 provides an IC structure or IC device according to any one of examples 1-26, where the IC structure or IC device includes or is a part of a power delivery circuitry.
Example 28 provides an IC package that includes an IC die including an IC structure or IC device according to any one of examples 1-27; and a further IC component, coupled to the IC die.
Example 29 provides an IC package according to example 28 where the further IC component includes a package substrate.
Example 30 provides an IC package according to example 28, where the further IC component includes an interposer.
Example 31 provides an IC package according to example 28, where the further IC component includes a further IC die.
Example 32 provides a computing device that includes a carrier substrate and an IC structure or IC device coupled to the carrier substrate, where the IC structure or device is an IC structure or device according to any one of examples 1-27, or the IC structure or device is included in the IC package according to any one of examples 28-31.
Example 33 provides a computing device according to example 32, where the computing device is a wearable or handheld computing device.
Example 34 provides a computing device according to examples 32 or 33, where the computing device further includes one or more communication chips.
Example 35 provides a computing device according to any one of examples 32-34, where the computing device further includes an antenna.
Example 36 provides a computing device according to any one of examples 32-35, where the carrier substrate is a motherboard.
Example 37 provides a method of fabricating an IC structure, the method including providing a first stack of nanoribbons and a second stack of nanoribbons over a support from a first side of the IC structure (e.g., where the stacks of nanoribbons initially have the same number of nanoribbons), forming a first region in the first stack of nanoribbons and a second region in the second stack of nanoribbons, where the first region is a source or drain region of a first transistor and the second region is a source or drain region of a second transistor, providing a conductive material around portions of the nanoribbons of the first stack and around portions of the nanoribbons of the second stack, flipping over the IC structure to reveal a second side of the IC structure, removing one or more nanoribbons from the first stack of nanoribbons (without removing nanoribbons from the stack, or removing fewer nanoribbons from the second stack), where after the removal of the one or more nanoribbons, the first stack of nanoribbons includes at least one nanoribbon, and has fewer nanoribbons than the second stack. The method further involves forming a first transistor having first channel portions in the first stack of nanoribbons and forming a second transistor having second channel portions in the second stack of nanoribbons.
Example 38 provides a method according to example 37, where removing the one or more nanoribbons from the first stack of nanoribbons includes etching an insulator material, a conductive material, and a semiconductor material of one of the nanoribbons of the first stack, and stopping on a layer of the insulator material (e.g., after etching the semiconductor material of the nanoribbon to remove).
Example 39 provides a method according to examples 37 or 38, where removing the one or more nanoribbons involves removing two or more nanoribbons from the first stack, including cyclically etching an insulator material, a conductive material, and a semiconductor material of one of the nanoribbons, and stopping on a layer of the insulator material (e.g., after etching the semiconductor material of the last nanoribbon to remove).
Example 40 provides a method according to examples 38 or 39, where etching the semiconductor material of one of the nanoribbons includes (e.g., intentionally or unintentionally) etching a second semiconductor material of a source region or a drain region adjacent to the semiconductor material.
Example 41 provides a method according to of any one of examples 38-40, where the insulator material is a first insulator material, and where the method further includes providing a liner over the layer of the first insulator material in an opening resulting from the removal of the one or more nanoribbons, where the liner includes a second insulator material, and filling the opening with a third insulator material.
Example 42 provides a method according to any one of examples 37-41, further including prior to removing the one or more nanoribbons from the first stack, forming openings over the first stack of nanoribbon and over the second stack of nanoribbons (e.g., by removing a semiconductor material over the first stack of nanoribbons and over the second stack of nanoribbons) and providing a liner in the openings.
Example 43 provides a method according to any one of examples 37-42, further including prior to removing the one or more nanoribbons from the first stack, providing a mask over a second side of the IC structure, where the mask covers the second stack of nanoribbons and has an opening over the first stack of nanoribbons (e.g., an opening sufficiently wide to enable removal of one or more nanoribbons through the opening in the mask).
Example 44 provides a method of example 43, further including after removing the one or more nanoribbons from the first stack, removing the mask, revealing a first opening over the first stack and a second opening over the second stack, the second opening including the liner where the liner is a first liner. The method further includes providing a second liner over the first liner in the second opening and in the first opening and filling the first opening and the second opening with an insulator material.
Example 45 provides a method according to any one of examples 37-44, where forming the stacks of nanoribbons includes providing alternate layers of a semiconductor material and a further material and forming fins from the alternate layers of the semiconductor material and the further material.
Example 46 provides a method according to any one of examples 37-45, where forming the first transistor and forming the second transistor include forming conductive contact structures coupled with the source region and the drain region.
Example 47 provides a method according to example 45, where forming the first transistor and forming the second transistor include removing the further material from around the layers of the semiconductor material, releasing the nanoribbons, providing a conductive material around channel regions in the nanoribbons, and forming a conductive contact structure coupled with the conductive material.
Example 48 provides a method according to any one of examples 37-47, where the IC structure is an IC structure according to any one of the preceding examples.
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.
