This application claims priority to Korean Patent Application No. 10-2022-0133213, filed on Oct. 17, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The disclosure relates to a backlight apparatus and an operating method thereof.
A display device may include a display panel displaying an image. When a light-receiving display panel such as a liquid crystal display (LCD) panel is used as the display panel, the display device may include a backlight apparatus. The backlight apparatus may include a plurality of light emitting diodes (LEDs) and may be disposed on a rear side of the display panel.
In recent display devices, a large number of LEDs may be arranged on the rear side of the display panel, and accordingly, a large number of driving circuits may be required to drive the LEDs. However, when the number of driving circuits increases, the number of wires for connecting the driving circuits may increase. As a result, a problem of transferring data for driving the LEDs to the driving circuit may occur.
One or more embodiments may provide a backlight apparatus and an operating method thereof for efficiently transferring data.
According to an aspect of an example embodiment, a backlight apparatus includes: a plurality of blocks, each of the plurality of blocks comprising a plurality of light emitting elements; a master driving circuit configured to generate a transmission frame comprising a training period and a data period, the training period comprising a clock training pattern, and the data period comprising a plurality of data packets respectively corresponding to the plurality of blocks; and a plurality of slave driving circuits respectively corresponding to the plurality of blocks and connected to the master driving circuit in a daisy chain structure, each of the plurality of slave driving circuits configured to: receive the transmission frame through the daisy chain structure, recover a clock based on the clock training pattern, and drive the plurality of light emitting elements in a corresponding block among the plurality of blocks based on its own data packet among the plurality of data packets.
According to an aspect of an example embodiment, a backlight apparatus includes: a plurality of blocks, each of the plurality of blocks comprising a plurality of light emitting elements; a master driving circuit configured to generate a transmission frame comprising a data period comprising a plurality of data packets respectively corresponding to the plurality of blocks; and a plurality of slave driving circuits respectively corresponding to the plurality of blocks and connected to the master driving circuit in a daisy chain structure, each of the plurality of slave driving circuits configured to: receive the transmission frame through the daisy chain structure, transfer a frame obtained by masking at least a part of its own data packet in the transmission frame received through the daisy chain structure as the transmission frame of a next slave driving circuit among the plurality of slave driving circuits, and drive the plurality of light emitting elements in a corresponding block among the plurality of blocks based on its own data packet among the plurality of data packets.
According to an aspect of an example embodiment, a method of operating a backlight apparatus comprising a plurality of blocks includes: generating a transmission frame comprising a clock training pattern and a plurality of data packets respectively corresponding to the plurality of blocks; transferring the transmission frame to a plurality of driving circuits respectively corresponding to the plurality of blocks and connected in a daisy chain structure; and recovering a clock based on the clock training pattern in each of the plurality of driving circuits.
The above and other aspects and features will be more apparent from the following description of example embodiments, taken in conjunction with the accompanying drawings, in which:
In the following detailed description, only certain embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.
Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. The sequence of operations or steps is not limited to the order presented in the claims or figures unless specifically indicated otherwise. The order of operations or steps may be changed, several operations or steps may be merged, a certain operation or step may be divided, and a specific operation or step may not be performed.
As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Although the terms first, second, and the like may be used herein to describe various elements, components, steps and/or operations, these terms are only used to distinguish one element, component, step or operation from another element, component, step, or operation.
Referring to
The display panel 140 may include a plurality of source lines SL1, SL2 . . . SLN, a plurality of gate lines GL1, GL2 . . . GLM, and a plurality of pixels PX. The source lines SL1 to SLN may extend substantially in a column direction, and the gate lines GL1 to GLM may extend substantially in a row direction. Each pixel PX may be connected to a corresponding source line among the source lines SL1 to SLN and a corresponding gate line among the gate lines GL1 to GLM. In some embodiments, the display panel 140 may be, for example, a liquid crystal display panel.
The timing controller 110 may control operations of the display device 100. For example, the timing controller 110 may control the source driver 120 and the gate driver 130 to display image data IMG received from an external device on the display panel 140. The timing controller 110 may generate pixel data RGB based on the image data IMG and provide the pixel data RGB to the source driver 120. Further, the timing controller 110 may provide a control signal CTRL1 for controlling a timing of the source driver 120 to the source driver 120 and a control signal CTRL2 for controlling a timing of the gate driver 130 to the gate driver 130.
The timing controller 110 may generate luminance data LDT representing luminance of the image based on the image data IMG and provide the luminance data LDT to the backlight driver 160. In some embodiments, the luminance data LDT may be generated for each frame. In some embodiments, the timing controller 110 may reflect at least a portion of the luminance data LDT to the pixel data RGB.
The source driver 120 may convert the pixel data RGB received from the timing controller 110 into data signals (e.g., data voltages), and output the data signals to the display panel 140 through the source lines SL1 to SLN. The gate driver 130 may be connected to the gate lines GL1 to GLM of the display panel 140 and sequentially drive the gate lines GL1 to GLM of the display panel 140.
The backlight unit 150 may be disposed on a rear side of the display panel 140. The backlight unit 150 may include a plurality of light emitting elements that emit light under control of the backlight driver 160. In some embodiments, the light emitting element may be, for example, a light emitting diode (LED), although embodiments are not limited thereto. Hereinafter, an embodiment is described in which the light emitting element is an LED, though other embodiments may have a different light emitting element. In some embodiments, the LEDs may be divided into a plurality of dimming blocks respectively corresponding to a plurality of regions of the display panel 140.
The backlight driver 160 may drive the LEDs of the backlight unit 150. The backlight driver 160 may control the LEDs based on the luminance data LDT received from the timing controller 110 so that each LED may emit light with brightness corresponding to the luminance data LDT. In some embodiments, the backlight driver 160 may control the LEDs so that each of the dimming blocks emits individual luminance.
Referring to
In some embodiments, the backlight unit 220 may also be divided into a plurality of blocks 221 in the m×n array, which correspond to the regions 211, respectively. In this case, the blocks 221 existing in the same row in the m×n array may be referred to as a block row, and the blocks 221 existing in the same column may be referred to as a block column. Each block 221 may include a plurality of LEDs 222 and operate as a light source of a corresponding region 211. The LEDs 222 of each block 221 may be driven by a backlight driver (e.g., 160 in
Referring to
As shown in
The pixel driving IC 310 may generate a plurality of data respectively corresponding to the pixel ICs 3201 to 320n. Each data may be brightness data indicating brightness to be emitted by the LEDs driven by the corresponding pixel IC 320i. In some embodiments, the pixel driving IC 310 may generate the data based on luminance data LDT received from a timing controller (e.g., 110 in
Referring to
Referring to
The data packets PIC1_DATA to PICn_DATA may correspond to the pixel ICs 3201 to 320n, respectively, and include data, for example, brightness data of LEDs driven by the corresponding pixel IC. The data packets PIC1_DATA to PICn_DATA may be arranged in the transmission frame 500 in the connection order of the pixel ICs 3201 to 320n connected in the daisy chain structure.
Each data packet 520 may include data 521 of LEDs driven by a corresponding pixel IC 320i. In some embodiments, each data packet 520 may further include a start of transmission (SOT) pattern 522 located before the data 521. The SOT pattern 522 may indicate a start of the corresponding data packet 520. In some embodiments, a blank (BK) 523 may be located at an end of each data packet 520.
In some embodiments, the transmission frame 500 may further include a start of frame (SOF) pattern 530 between the clock training pattern 510 and the first data packet PIC1_DATA. The SOF pattern 530 may indicate a start of the data period in the transmission frame 500. In some embodiments, a blank 540 may exist between the SOF pattern 530 and the first data packet PIC1_DATA.
In some embodiments, the data 521 of the data packet 520 may include a plurality of fields that correspond to a plurality of LEDs driven by the corresponding pixel IC 320i, respectively. Each field may include data bits indicating brightness of a corresponding LED among the LEDs.
Referring to
Referring to
The CDR circuit 610 may recover a clock by performing a CDR process on the clock training pattern 510 of the received transmission frame 500. In some embodiments, the CDR circuit 610 may recover the clock by performing the CDR process on a clock pattern included in the data period of the transmission frame 500. Accordingly, in an embodiment, the pixel IC 320i may operate based on the recovered clock.
The masking circuit 620 may mask at least a part of its own data packet in the received transmission frame 500 with a masking pattern. In some embodiments, a transmission frame 500 received by the pixel IC 320i may be a transmission frame 500 in which data packets corresponding to the pixel ICs 3201 to 320i−1 are masked. In some embodiments, when masking at least a part of its own data packet with the masking pattern, the masking circuit 620 may mask data packets corresponding to the pixel ICs 3201 to 320i−1 again.
The masking circuit 620 may transfer the masked transmission frame 500 to a next pixel IC 320i+1. The next pixel IC 320i+1 may indicate a pixel IC 320i+1 connected an output of the corresponding pixel IC 320i in the daisy chain structure, that is, a pixel IC 320i+1 whose input terminal DI is connected to an output terminal DO of the corresponding pixel IC 320i. In this case, the masking circuit 620 may bypass the clock training pattern 510 and a data period after its own data packet and transfer them to the next pixel IC 320i+1.
Next, an operation of a backlight driver according to various embodiments is described with reference to
Referring to
The pixel IC 320i may bypass a clock training pattern of the received transmission frame TF1i to the next pixel IC 320i+1. The pixel IC 320i may perform a CDR process to recover a clock based on the clock training pattern. In some embodiments, the pixel IC 320i may detect a frequency based on the clock training pattern, lock the detected frequency, and recover the clock. Because the clock training pattern is transferred to a plurality of pixel ICs 3201 to 320n through the bypass, the pixel ICs 3201 to 320n may simultaneously recover the clock based on the clock training pattern.
The pixel IC 320i may mask at least a part of its own data packet PICi_DATA in the received transmission frame TF1i, and transfer the masked transmission frame TF1i+1 to the next pixel IC 320i+1.
The first pixel IC 320i of the daisy chain structure may receive a data packet PIC1_DATA after the clock training pattern. The pixel IC 3201 may receive the first data packet (i.e., a beginning data packet) PIC1_DATA among a plurality of data packets PIC1_DATA to PICn_DATA after the clock training pattern as its own data packet. The pixel IC 3201 may transfer the transmission frame TF12 in which at least a part of its own data packet PIC1_DATA is masked with a masking pattern to the next pixel IC 3202.
The second pixel IC 3202 may receive the masked transmission frame TF12 from the previous pixel IC 3201. Since the data packet PIC1_DATA is masked in the masked transmission frame TF12, the second data packet PIC2_DATA of the original transmission frame TF11 may be the first data packet of the masked transmission frame TF12. Accordingly, the pixel IC 3202 may receive the first data packet PIC2_DATA of the masked transmission frame TF12 as its own data packet. The pixel IC 3202 may transfer the transmission frame TF13 in which at least a part of its own data packet PIC2_DATA is masked with a masking pattern in the masked transmission frame TF12 to the next pixel IC 3203.
In this way, the ith pixel IC 320i may receive the masked transmission frame TF1i from the (i−1)th pixel IC 320i−1. Because the first to (i−1)th data packets PIC1_DATA to PIC(i−1)_DATA are masked in the masked transmission frame TF1i, the ith data packet PICi_DATA of the original transmission frame TF11 may be the first data packet (beginning data packet) of the masked transmission frame TF1i. Accordingly, the pixel IC 320i may receive the first data packet PICi_DATA of the masked transmission frame TF1i as its own data packet. The pixel IC 320i may output the transmission frame TF1i+1 in which at least a part of its own data packet PICi_DATA is masked with a masking pattern in the masked transmission frame TF1i to the next pixel IC 320i+1.
In some embodiments, the pixel IC 320i may mask the whole of the data packet PICi_DATA of the pixel IC 320i with the masking pattern. In some embodiments, the pixel IC 320i may mask a part of its own data packet PICi_DATA with the masking pattern. In this case, the part masked in the data packet PICi_DATA may include an SOT pattern (e.g., 522 of
In some embodiments, the pixel IC 320i may identify the start of a data period based on an SOF pattern (e.g., 530 in
As described above, because the backlight driver 300 uses the masking pattern, even if there is no identification information for identifying the pixel IC corresponding to the data packet or information indicating the order of the data packets, each pixel IC 320i may identify its own data packet PICi_DATA so that a size of the transmission frame may be reduced. In addition, since, in an embodiment, there is no need to transmit clocks to all pixel ICs by using an embedded clock signal, high electromagnetic interference (EMI) that may be caused by having clocks transmitted to all pixel ICs may be prevented.
Referring to
When an SOT pattern SOTi is input in the transmission frame TF2i, the pixel IC 320i may receive the SOT pattern SOTi and data DATAi following the SOT pattern SOTi as its own data packet. When the data DATAi of the data packet ends, the pixel IC 320i may set the masking signal MS to a second level. In some embodiments, the pixel IC 320i may set the masking signal MS to the second level in the blank BK after the data DATAi. The second level may be, for example, a low level (‘0’) as a logic level. When the masking signal MS reaches the second level, the pixel IC 320i may end masking and output the transmission frame TF2i as the transmission frame TF2i+1. In this way, the pixel IC 320i may mask a period (hereinafter referred to as a “masking period”) from after the SOF pattern to the data DATAi of its own data packet.
Since the first data packet to the ith data packet in the transmission frame TF2i+1 have been masked with the masking pattern by the masking signal MS, the next pixel IC 320i+1 may receive the first SOT pattern, i.e., an SOT pattern SOTi+1 of the (i+1)th data packet and data DATAi+1 following the SOT pattern SOTi+1 as its own data packet in the transmission frame TF2i+1. Further, as described above, the pixel IC 320i+1 may output the transmission frame masked with the masking pattern during a period from after the SOF pattern to the data DATAi+1.
As described above, each pixel IC 320i may receive its own data packet without identification information by receiving the data DATAi following the first unmasked SOT pattern SOTi as its own data. Further, each pixel IC 320i may efficiently control masking by starting masking based on the SOF pattern and ending masking after the data DATAi following the first SOT pattern SOTi.
Referring to
A plurality of data packets respectively corresponding to a plurality of pixel ICs 3201 to 320n may be transmitted in the data period. The data period may include a clock pattern and data. The clock pattern may repeat every cycle of the clock, and may have a pattern in which an edge of the clock can be identified. For example,
The pixel IC 3201 may receive its own data packet in the data period, set a masking signal MS1 to a predetermined level to mask a period (i.e., create a masking period) corresponding to its own data packet in the data period, and output the masked transmission frame TF32 through an output terminal. When a clock pattern is included in the masking period, the pixel IC 3201 may not mask a region corresponding to the edge of the clock. That is, the pixel IC 3201 may stop masking in the region corresponding to the edge of the clock. In some embodiments, as shown in
The next pixel IC 3202 may receive the transmission frame TF32 transferred through the output terminal of the pixel IC 3201 through an input terminal. The pixel IC 3202 may lock a frequency of a clock CLK2 based on the clock training pattern of the transmission frame TF32 (LOCK2) and output the clock training pattern through an output terminal. Further, the pixel IC 3202 may recover the clock CLK2 by detecting a timing at which a bit value transitions in the clock pattern as an edge (e.g., rising edge) of the clock CLK2 based on the frequency locked by the clock training pattern. In some embodiments, the pixel IC 3202 may recover the clock CLK2 by detecting the edge of the clock CLK2 based on the pulses 910 and 920 of the regions corresponding to the edges of the clock.
The pixel IC 3202 may receive its own data packet in the data period of the transmission frame, set the masking signal MS2 to the predetermined level to mask a period (masking period) corresponding to its own data packet, and output the masked transmission frame TF33 through an output terminal. When the clock pattern is included in the masking period, the pixel IC 3202 may not mask a region corresponding to the edge of the clock. That is, the pixel IC 3202 may stop masking in the region corresponding to the edge of the clock.
As such, each pixel IC 320i may mask at least a part of the masking period. Because each pixel IC 320i masks its own data packet, the next pixel IC 320i+1 may receive the first data packet as its own data packet in the transmission frame TF1i+1. Further, each pixel IC 320i may not mask the region corresponding to the edge of the clock in the clock pattern during the masking period. Accordingly, the next pixel IC 320i+1 may also recover the clock based on the edge of the clock.
A transmission frame may be transferred as a differential signal. In this case, as shown in
A plurality of pixel ICs 10201 to 1020n may be connected in a daisy chain structure. That is, the input terminals DIP and DIN of the (i+1)th pixel IC 1020i+1 may be connected to the output terminals DOP and DON of the ith pixel IC 1020i, respectively. In this case, the input terminals DIP and DIN of the first pixel IC 10201 may be connected to the output terminals XDOP and XDON of the pixel driving IC 1010, respectively, and the output terminals DOP and DOP of the last pixel IC 1020n may not be connected to the input terminals DIP and DIN of another pixel IC.
Referring to
The pixel ICs 112011 to 1120mn may be divided into a plurality of pixel IC groups, and the jth pixel IC group may include a plurality of pixel ICs 1120j1 to 1120jn connected in a daisy chain structure. Here, j is an integer between 1 and m. That is, the pixel ICs 112011 to 11201n connected in the daisy chain structure may form the first pixel IC group, the pixel ICs 112021 to 11202n connected in the daisy chain structure may form the second pixel IC group, and the pixel ICs 1120m1 to 1120mn connected in the daisy chain structure may form an mth pixel IC group. In some embodiments, the pixel ICs 1120j1 to 1120jn of the jth pixel IC group may correspond to a plurality of blocks (221 in
The pixel driving IC 1110 may have a plurality of output terminals XDO1, XDO2 . . . XDOm. Each output terminal XDOj may be connected to the first pixel IC 1120j1 among the pixel ICs 1120j1 to 1120jn included in a corresponding pixel IC group among the plurality of pixel IC groups. The pixel driving IC 1110 may generate a plurality of transmission frames respectively corresponding to the plurality of pixel IC groups, and transfer each transmission frame to a corresponding one of the pixel IC groups 1120j1 to 1120jn through a corresponding output terminal XDOj.
As described above, the pixel driving IC may control a plurality of LEDs included in the plurality of blocks of the backlight unit.
Referring to
Each pixel IC may recover a clock by performing a CDR process on the clock training pattern of the training period at S1220. Each pixel IC may receive the first unmasked data packet in the data period as its own data packet at S1230. Each pixel IC may drive LEDs connected to the corresponding pixel IC based on data included in its own data packet. Each pixel IC may mask at least a part of its own data packet at S1240. Accordingly, the pixel IC may receive from a previous pixel IC a transmission frame in which a data packet of the previous pixel IC is masked.
In some embodiments, each of the components, elements, modules, or units represented by a block may be implemented as various numbers of hardware, software, and/or firmware structures that execute respective functions described above, according to embodiments. For example, at least one of these components, elements, modules, or units may include various hardware components including a digital circuit, a programmable or non-programmable logic device or array, an application specific integrated circuit (ASIC), or other circuitry using a digital circuit structure, such as a memory, a processor, a logic circuit, a look-up table, etc., that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. Further, at least one of these components, elements, modules, or units may include a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions, and executed by one or more microprocessors or other control apparatuses. Furthermore, at least one of these components, elements, modules, or units may further include or may be implemented by a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like. Functional aspects of embodiments may be implemented in algorithms that execute on one or more processors.
While this invention has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
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