The present invention relates to backlight modulation circuits that are typically used in liquid crystal displays (LCDs).
An LCD has the advantages of portability, low power consumption, and low radiation. LCDs have been widely used in various portable information products such as notebooks, personal digital assistants (PDAs), video cameras and the like. Furthermore, the LCD is considered by many to have the potential to completely replace CRT (cathode ray tube) monitors and televisions.
A typical LCD includes an LCD panel, a backlight for illuminating the LCD panel, and a backlight control circuit for controlling the backlight. The backlight control circuit includes a pulse generator configured for generating a square pulse, a backlight modulation circuit configured for generating a backlight adjusting signal according to the square pulse, and an inverter circuit configured for transforming a low direct current (DC) voltage to a high alternating current (AC) voltage. The high AC voltage drives the backlight according to relative duty ratios of the backlight adjusting signal. The backlight can include one or more lamps, such as cold cathode fluorescent lamps.
The amplifier 150 includes a negative input, a positive input, and an output.
The oscillator circuit 140 includes a low frequency oscillator 143 and a capacitor 141. The low frequency oscillator 143 is connected to ground via the capacitor 141. An electrical connecting node between the low frequency oscillator 143 and the capacitor 141 is connected to the positive input of the amplifier 150. A capacitance of the capacitor 141 is approximately 4.7 nF (nanofarads).
The pulse generator 110 includes a scaler 111, an NMOSFET (n-channel metal-oxide-semiconductor field-effect transistor) 112, a bias resistor 113, and a 5V (volts) DC power supply 114. The NMOSFET 112 includes a source electrode “S” connected to ground, a drain electrode “D” connected to the power supply 114 via the bias resistor 113, and a gate electrode “G” connected to an output of the scaler 111 for receiving a pulse signal therefrom.
The integrating circuit 120 includes an integrating resistor 121 and an integrating capacitor 122. The drain electrode “D” of the NMOSFET 112 is connected to ground via the integrating resistor 121 and the integrating capacitor 122 in series. A resistance of the integrating resistor 121 is approximately 47Ω (ohms). A capacitance of the integrating capacitor 122 is approximately 0.1 μF (microfarads).
The voltage division circuit 130 includes two voltage division resistors 131, 132. An electrical connecting node between the integrating resistor 121 and the integrating capacitor 122 is connected to ground via the voltage division resistor 131 and the voltage division resistor 132 in series. An electrical connecting node between the two voltage division resistors 131, 132 is connected to the negative input of the amplifier 150. A resistance of the voltage division resistor 131 is approximately 100 KΩ (kiloohms). A resistance of the voltage division resistor 132 is approximately 47 KΩ.
The regulation circuit 160 includes a current limiting resistor 161, a filter capacitor 162, and a 5V DC reference power supply 163. The reference power supply 163 is connected to ground via the current limiting resistor 161 and the filter capacitor 162 in series. An electrical connecting node between the current limiting resistor 161 and the filter capacitor 162 is connected to the negative input of the amplifier 150.
The pulse generator 110 outputs a square pulse at the drain electrode “D” of the NMOSFET 112. This square pulse is shown in
Because the backlight modulation circuit 100 includes the integrating circuit 120, the voltage division circuit 130, and the regulation circuit 160, the backlight modulation circuit 100 is somewhat complicated. Furthermore, the 5V square pulse outputted from the pulse generator circuit 110 is transmitted to the positive input of the amplifier 150 via the integrating circuit 120, the voltage division circuit 130, and the regulation circuit 160 in series. Thus interference may occur when the 5V square pulse is transmitted to the amplifier 150.
It is desired to provide a new backlight modulation circuit which can overcome the above-described deficiencies.
In one preferred embodiment, a backlight modulation circuit includes a pulse generator circuit configured for generating a first square pulse; a voltage division circuit configured for receiving the first square pulse and generating a second square pulse according to the first square pulse; an oscillator circuit configured for generating a reference voltage; and an amplifier comprising a negative input configured for receiving the second square pulse from the voltage division circuit, and a positive input configured for receiving the reference voltage from the oscillator circuit as a reference pulse signal, the amplifier being configured for generating a backlight adjusting signal according to the reference pulse signal and the second square pulse.
Other novel features and advantages of the backlight modulation circuit will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
Reference will now be made to the drawings to describe various embodiments of the present invention in detail.
The amplifier 251 includes a negative input, a positive input, and an output.
The oscillator circuit 240 includes a low frequency oscillator 243, a capacitor 241, and a resistor 242. The capacitor 241 and the resistor 242 are connected in parallel between the low frequency oscillator 243 and ground. An electrical connecting node between the low frequency oscillator 243 and the resistor 242 is connected to the positive input of the amplifier 150. A capacitance of the capacitor 241 is approximately 4.7 nF. A resistance of the resistor 242 is approximately 604 KΩ.
The pulse generator 210 includes a scaler 211, an NMOSFET 212, a bias resistor 213, and a 5V DC power supply 214. The NMOSFET 212 includes a source electrode “S” connected to ground, a drain electrode “D” connected to the power supply 214 via the bias resistor 213, and a gate electrode “G” connected to an output of the scaler 111 for receiving a pulse signal therefrom.
The voltage division circuit 230 includes two voltage division resistors 231, 232. The drain electrode “D” of the NMOSFET 212 is connected to ground via the voltage division resistor 231 and the voltage division resistor 232 in series. An electrical connecting node between the two voltage division resistors 231, 232 is connected to the negative input of the amplifier 251. A resistance of the voltage division resistor 231 is approximately 22 KΩ. A resistance of the voltage division resistor 232 is approximately 10 KΩ.
The pulse generator 210 outputs a first square pulse at the drain electrode “D” of the NMOSFET 212. This first square pulse is shown in
The oscillator circuit 240 generates a 0.7V DC voltage (as shown in
Because the backlight modulation circuit 200 does not include an integrating circuit or a regulation circuit, the backlight modulation circuit 200 is relatively simple. Furthermore, the 5V square pulse outputted from the pulse generator circuit 210 is provided to the positive input of the amplifier 251 only via the voltage division circuit 230. Thus any interference generated when the 5V square pulse is transmitted to the amplifier 251 is reduced.
It is to be understood, however, that even though numerous characteristics and advantages of the preferred embodiments have been set out in the foregoing description, together with details of the structures and functions of the embodiments, the disclosure is illustrative only; and that changes may be made in detail, especially in matters of arrangement of parts within the principles of present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
Number | Date | Country | Kind |
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95124888 A | Jul 2006 | TW | national |
Number | Name | Date | Kind |
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3781470 | Horn | Dec 1973 | A |
5272327 | Mitchell et al. | Dec 1993 | A |
6114814 | Shannon et al. | Sep 2000 | A |
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6885532 | Noro | Apr 2005 | B2 |
Number | Date | Country | |
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20080007186 A1 | Jan 2008 | US |