Patent Grant
11488548
This U.S. non-provisional application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2020-0130199, filed on Oct. 8, 2020, and Korean Patent Application No. 10-2020-0154074, filed on Nov. 17, 2020, in the Korean Intellectual Property Office (KIPO), the disclosures of which are incorporated by reference herein in their entireties.
The disclosure relates to semiconductor integrated circuits, and more particularly to a backlight system, a display device including the backlight system and a method of transferring data in the backlight system.
A display device such as a liquid crystal display (LCD) device represents gray scales of an image by adjusting an amount of transmission light from a backlight source. The display may include a backlight source of various kinds such as a cold cathode fluorescent lamp (CCFL) scheme, a directed-down type light emitting diode (LED) scheme, an edge type LED scheme, a local dimming scheme, etc. Recently a full array local dimming (FALD) scheme arranging LEDs in a two-dimensional array is noted because the FALD scheme results in high image quality. The FALD scheme is widely adopted in display products requiring high image quality such as a premium TV, but it is difficult to drive a huge number of backlight sources (e.g. LED light sources) by the FALD scheme. Noise may be increased due to increase of the number of driving integrated circuits (ICs), nonuniformity of the driving ICs, increase of connectors to a printed circuit board (PCB), etc., and it is difficult to secure luminance quality of the backlight sources.
Provided are a backlight system and a display device including the backlight system capable of efficiently performing the local dimming.
Provided are a method of transferring data in the backlight system capable of efficiently loading luminance data.
In accordance with an aspect of the disclosure, a backlight system includes a backlight including a plurality of slave driving circuits and a plurality of light sources driven by the plurality of slave driving circuits, wherein the plurality of slave driving circuits are arranged in a matrix of driving rows and driving columns such that first through m-th slave driving circuits, where m is a positive integer greater than one, are arranged in each driving row of the driving rows, and the first through m-th slave driving circuits are connected in a daisy chain structure; and a master driving circuit configured to generate a plurality of input data signals, wherein each input data signal of the plurality of input data signals corresponds to the each driving row, and the each input data signal includes first through m-th packets including luminance data corresponding to the first through m-th slave driving circuits.
In accordance with an aspect of the disclosure, a display device includes a display panel including a plurality of pixels configured to display an image corresponding to input image data; a display panel driver configured to drive the display panel based on the input image data; a backlight including a plurality of slave driving circuits and a plurality of light sources driven by the plurality of slave driving circuits, wherein the plurality of slave driving circuits are arranged in a matrix of driving rows and driving columns such that first through m-th slave driving circuits, where m is a positive integer greater than one, are arranged in each driving row of the driving rows, and the first through m-th slave driving circuits are connected in a daisy chain structure; and a master driving circuit configured to generate a plurality of input data signals, wherein each input data signal of the plurality of input data signals corresponds to the each driving row, and the each input data signal includes first through m-th packets including luminance data corresponding to the first through m-th slave driving circuits.
In accordance with an aspect of the disclosure, a method of transferring data in a backlight system including a plurality of slave driving circuits and a plurality of light sources driven by the plurality of slave driving circuits, the plurality of slave driving circuits being arranged in a matrix of driving rows and driving columns such that first through m-th slave driving circuits, where m is a positive integer greater than one, arranged in each driving row of the driving rows are connected in a daisy chain structure, includes generating an input data signal including first through m-th packets including virtual identifiers and luminance data corresponding to the first through m-th slave driving circuits such that values of the virtual identifiers are sequentially increased or sequentially decreased; transferring the input data signal sequentially from an m-th slave driving circuit of the first through m-th slave driving circuits to a first slave driving circuit of the first through m-th slave driving circuits by applying the input data signal to the m-th slave driving circuit; in each of the first through m-th slave driving circuits, increasing or decreasing the a value of a virtual identifier of a reception packet transferred from a latter stage slave driving circuit to transfer a transmission packet including the virtual identifier having the increased or decreased value to a former stage slave driving circuit; and in the each of the first through m-th slave driving circuits, storing the luminance data included in the reception packet based on a result of comparing the value of the virtual identifier of the reception packet with a fixed address.
The backlight system according to example embodiments may reduce the number of wirings of the backlight and enhance noise margin by connecting the slave driving circuits in the daisy chain structure and transferring the luminance data by a digital scheme.
In addition, the backlight system and the method of transferring luminance data according to example embodiments may reduce the size of the backlight and increase the speed of the local dimming operation by loading the luminance data to the corresponding slave driving circuit among the plurality of slave driving circuits connected in the daisy chain structure using the virtual identifier to omit configuration and operation for imposing identifiers to the slave driving circuits.
The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. In the drawings, like numerals refer to like elements throughout. Duplicate descriptions of various elements may be omitted.
As is traditional in the field, embodiments may be described and illustrated in terms of blocks which carry out a described function or functions. These blocks, which may be referred to herein as units or modules or the like, or by names such as driver, controller, device, or the like, may be physically implemented by analog or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits, or the like, and may be driven by firmware and software. The circuits may, for example, be embodied in one or more semiconductor chips, or on substrate supports such as printed circuit boards and the like. Circuits included in a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware to perform some functions of the block and a processor to perform other functions of the block. Each block of the embodiments may be physically separated into two or more interacting and discrete blocks. Likewise, the blocks of the embodiments may be physically combined into more complex blocks.
Referring to
The backlight 700 may include a plurality of slave driving circuits PDR1,1˜PDRn,m and a plurality of light sources driven by the plurality of slave driving circuits PDR1,1˜PDR1,m. The plurality of light sources are omitted in
The plurality of slave driving circuits PDR1,1˜PDRn,m, where each of n and m is a positive integer greater than one, may be arranged in a matrix of driving rows DR1˜DRn and driving columns DC1˜DCm. As illustrated in
The master driving circuit MDR 600 may generate a plurality of input data signals SDT1,m˜SDTn,m respectively corresponding to the plurality of driving rows DR1˜DRn. Each input data signal SDTi,m corresponding to each driving row DRi may include first through m-th packets including luminance data to be loaded respectively to the first through m-th slave driving circuits PDRi,1˜PDRi,m. Examples of the data signal and the packet transferred in the backlight system 10 will be further described below with reference to
The master driving circuit MDR 600 may apply each input data signal SDTi,m to the m-th slave driving circuit PDRi,m, which is the last slave driving circuit in the daisy chain. The first through m-th slave driving circuits PDRi,1˜PDRi,m arranged in each driving row DRi may transfer each input data signal SDTi,m sequentially from the m-th slave driving circuit PDRi,m to the first slave driving circuit PDRi,1. In other words, each slave driving circuit PDRi,j (i=1˜n, j=1˜m) arranged in each driving row DRi may receive a data signal SDTi,j transferred from a latter slave driving circuit PDRi,j+1, which may be, for example, a slave driving circuit in a latter stage than a stage of the slave driving circuit PDRi,j, and may transfer a data signal SDTi,j−1 to a former slave driving circuit PDRi,j−1, which may be a slave driving circuit in a former stage than a stage of the slave driving circuit PDRi,j.
The plurality of slave driving circuits PDR1,1˜PDRn,m may receive clock signals SCLK1,1˜SCLKn,m, respectively, and operate based on the receive clock signal. Example embodiments of providing the clock signals SCLK1,1˜SCLKn,m will be described below with reference to
Conventional backlight systems adopt a direct driving scheme or a peer-to-peer driving scheme in which a plurality of slave driving circuits are connected to a master driving circuit through respective connection lines and the master driving circuit control directly each of the plurality slave driving circuits. In this case, the connection lines are increased as the number of the plurality of slave driving circuits, design margin is degraded by complex routing of the connection lines and enlargement of a display device is limited.
To simplify the routing of the connection lines, a backlight panel may be divided into a plurality of sub panels and the plurality of sub panels may be controlled by a plurality of master driving circuits. However, the problem of the complex routing may remain still and the local dimming may not be uniform due to characteristic deviations of the plurality of master driving circuits.
The backlight system according to example embodiments may reduce the number of wirings of the backlight and enhance noise margin by connecting the slave driving circuits in the daisy chain structure and transferring the luminance data by a digital scheme.
Referring to
The start identifier STT may indicate a start position of the packet PKT. For example, the start identifier STT may be one-bit data and each slave driving circuit may detect the start of packet PKT when the start identifier STT has a value of 0. The size or the total bit number of the packet PKT may be determined in advance, and each slave driving circuit may recognize, as one packet PKT, data bits corresponding to the total bit number received after the start identifier STT.
The virtual identifier VID may indicate the slave driving circuit corresponding to the packet PKT. As will be described below with reference to
The lock identifier LCK may indicate whether the virtual identifier VID is fixed. For example, the rock identifier LCK may be one-bit data, the virtual identifier VID may be changed while passing through the slave driving circuits when the lock identifier LCK has a value of 0, and the virtual identifier VID may be fixed with the value output from the master driving circuit MDR 600 without change when the lock identifier LCK has a value of 1.
The type identifier TP may indicate a type of the packet PKT. According to the value of the type identifier TP, the type identifier TP may indicate whether the packet PKT includes the luminance data, whether the packet PKT includes control data other than the luminance data, a row address of local dimming blocks corresponding to the luminance data, an operation mode, etc.
The luminance data DMD1˜DMDk may correspond to a plurality of local dimming blocks. The luminance data DMD1˜DMDk may be replaced with other data depending on the type of the packet PKT.
The parity bits PRT may be used to check errors of the luminance data DMD1˜DMDk. Each slave driving circuit may include a decoder DEC as will be described below with reference to
Referring to
At operation S200, the input data signal may be transferred sequentially from the m-th slave driving circuit to the first slave driving circuit by applying the input data signal to the m-th slave driving circuit.
In each of the first through m-th slave driving circuits, at operation S300 the value of the virtual identifier of a reception packet transferred from the slave driving circuit in a latter stage may be increased or decreased in order to transfer a transmission packet including the virtual identifier having the increased or decreased value to the slave driving circuit in a former stage.
In each of the first through m-th slave driving circuits, at operation S400 the luminance data included in the reception packet may be stored based on a result of comparing the value of the virtual identifier of the reception packet with a fixed address.
In
Referring to
In some example embodiments, as a first case CS1, the master driving circuit MDR 600 may generate each input data signal SDTi,m by sequentially decreasing the values of the virtual identifiers VID included in the first through m-th packets PKTi,1˜PKTi,m. For convenience of illustration,
In some example embodiments, as a second case CS2, the master driving circuit MDR 600 may generate each input data signal SDTi,m by sequentially increasing the values of the virtual identifiers VID included in the first through m-th packets PKTi,1˜PKTi,m. As illustrated in
Referring to
Examples of the data transfer method using the virtual identifier VID will be further described below with reference to
Referring to
The display panel 100 includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels electrically connected to the gate lines GL and the data lines DL. The gate lines GL may extend in a first direction and the data lines DL may extend in a second direction crossing the first direction.
The display panel 100 may be a liquid crystal display panel. The display panel 100 may include a first base substrate including the gate lines GL, the data lines DL, the pixels and the switching element, a second base substrate facing the first base substrate and including a common electrode, and a liquid crystal layer disposed between the first base substrate and the second base substrate.
The driving controller 200 may receive the input image data IMG and an input control signal CONT from the host device 60. For example, the input image data IMG may include red image data, green image data, and blue image data. In some embodiments, the input image data IMG may include white image data. In some embodiments, the input image data IMG may include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronizing signal and a horizontal synchronizing signal.
The driving controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.
The driving controller 200 generates the first control signal CONT1 for controlling an operation of the gate driver GDRV 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver GDRV 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.
The driving controller 200 generates the second control signal CONT2 for controlling an operation of the data driver DDRV 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver DDRV 500. The second control signal CONT2 may include a horizontal start signal and a load signal.
The driving controller 200 generates the data signal DATA based on the input image data IMG The driving controller 200 outputs the data signal DATA to the data driver DDRV 500.
The driving controller 200 generates the third control signal CONT3 for controlling an operation of the gamma reference voltage generator GGEN 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator GGEN 400.
In some example embodiments, the driving controller 200 may generate the dimming information DIMM based on the input image data IMG and the driving controller instead of the host device 60 may provide the dimming information DIMM to the master driving circuit MDR 600. In some example embodiments, as illustrated in
The gate driver GDRV 300 generates gate signals for driving the gate lines GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver GDRV 300 may output the gate signals to the gate lines GL.
The gamma reference voltage generator GGEN 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator GGEN 400 provides the gamma reference voltage VGREF to the data driver DDRV 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA. The gamma reference voltage generator GGEN 400 may be disposed in the driving controller 200, or in the data driver DDRV 500.
The data driver DDRV 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200, and receives the gamma reference voltages VGREF from the gamma reference voltage generator GGEN 400. The data driver DDRV 500 converts the data signal DATA into data voltages having an analog type using the gamma reference voltages VGREF. The data driver DDRV 500 outputs the data voltages to the data lines DL.
Referring to
Each of the display panel 100 and the backlight BLU has a rectangular shape having short sides in a first direction D1 and long sides in a second direction D2 that crosses the first direction DI. However, the shape of each of the display panel 100 and the backlight unit BLU is not limited thereto, and may differ in other embodiments.
The backlight BLU generates light and provides the generated light to the display panel 100. The backlight BLU may include a plurality of slave driving circuits such that the slave driving circuits arranged in each driving row are connected in a daisy chain structure, as described above. The display panel 100 generates an image using the light received from the backlight BLU. The generated image is displayed to a user through an upper portion of the display panel 100.
The display panel 100 includes a first substrate 101, a second substrate 102 that faces the first substrate 101, and a liquid crystal layer LC disposed between the first substrate 101 and the second substrate 102. Each of the first substrate 101 and the second substrate 102 has a rectangular shape having short sides in the first direction D1 and long sides in the second direction D2.
A plurality of pixels PX, a plurality of gate lines GL1 to GLm, and a plurality of data lines DL1 to DLn are disposed on the first substrate 101. Here, m and n are natural numbers. Although only one pixel PX is illustrated in
The gate lines GL1 to GLm and the data lines DL1 to DLn are insulated from each other and cross each other. The gate lines GL1 to GLm extend in the second direction D2 and are connected to the gate driver GDRV 300. The data lines DL1 to DLn extend in the first direction D1 and are connected to the data driver DDRV 500. The pixels PX are connected to the gate lines GL1 to GLm and the data lines DL1 to DLn, respectively.
The gate driver GDRV 300 is disposed on a predetermined portion of the first substrate 101 adjacent to one of the short sides of the first substrate 101. The gate driver GDRV 300 is formed in a same process as transistors of the pixels PX and then mounted on the first substrate 101 in the form of an amorphous silicon TFT gate driver circuit (ASG) or oxide semiconductor TFT gate driver circuit (OSG). However, embodiments are not limited thereto. For example, the gate driver GDRV 300 may be provided as a plurality of driving chips and mounted on flexible circuit boards and then be connected to the first substrate 101 as a tape carrier package (TCP). In embodiments, the driving chips of the gate driver GDRV 300 may be mounted on the first substrate 101 as a chip on glass (COG).
The data driver DDRV 500 includes source driving chips 501 mounted on a flexible circuit board 502. For example, although four source driving chips 501 and four flexible circuit boards 502 are illustrated in
One side of each of the flexible circuit boards 502 is connected to one side of the first substrate 101. The one side of the first substrate 101 is one of the long sides of the first substrate 101. The other side of each of the flexible circuit boards 502, which is opposite to the one side of each of the flexible circuit boards 502, is connected to the printed circuit board 80. The source driving chips 501 are connected to the first substrate 101 and the printed circuit board 80 through the flexible circuit boards 502.
The timing controller as described above is disposed on the printed circuit board 80. The timing controller is mounted on the printed circuit board 80 as an integrated circuit chip. The timing controller is connected to the gate driver GDRV 300 and the data drivers DDRV 500 through the flexible circuit boards 502. The timing controller outputs a gate control signal, a data control signal, and image data.
The gate driver GDRV 300 receives the gate control signal from the timing controller and generates a plurality of gate signals in response to the gate control signal. The gate driver GDRV 300 sequentially outputs the gate signals. The gate signals are provided to the pixels PX row-by-row through the gate lines GL1 to GLm. As a result, the pixels PX are driven row-by-row.
The data driver DDRV 500 receives the image data and the data control signal from the timing controller. The data driver DDRV 500 generates and output analog data voltages that correspond to the image data in response to the data control signal. The data voltages are transmitted to the pixels PX through the data lines DL1 to DLn.
The pixels PX receive the data voltages through the data lines DL1 to DLn in response to the gate signals received through the gate lines GL1 to GLm. The pixels PX display gray scales that correspond to the data voltages. As a result, an image can be displayed.
Referring to
In the local dimming method, when the grayscale data of the image displayed on the display block is high, the degree of dimming of the local dimming block corresponding to the display block may be increased. On the other hand, when the grayscale data of the image displayed on the display block is low, the degree of dimming of the local dimming block corresponding to the display block may be decreased.
Referring to
As an example,
Referring to
Referring to
Each slave driving circuit PDRi,j in
The clock supply structure by the daisy chain scheme of
Referring to
In a slave driving circuit PDRb of a second type, the shifting register SREG may operate based on the received clock signal SCLK and the driver DRU may operate based on an oscillation signal generated by an oscillator OSC.
In a slave driving circuit PDRc of a third type, both of the shifting register SREG and the driver DRU may operate based on the received clock signal SCLK. In some example embodiments, the slave driving circuit PDRc may further include a clock divider CDV configured to divide the frequency of the clock signal SCLK to provide a divided clocks signal to the driver DRU.
The slave driving circuits included in the backlight according to example embodiments may be implemented as the slave driving circuit PDRc of the third type. In other words, the shifting register SREG and the driver DRU included in each slave driving circuit may operate based on the same clock signal SCLK. In this example, a clock pin to receive the additional clocks signal GCLK may be removed, the trimming operation of the oscillator OSC is not required, the size of the slave driving circuit may be reduced, and synchronization of the entire system may be implemented conveniently using the same clock signal SCLK.
Referring to
The shift register SREG 810 may store a reception packet in the data signal SDTi,j transferred from the slave driving circuit in a latter stage by bit-by-by shifting the reception packet and output the stored reception packet. The control circuit CLG 820 may generate a latch signal LATj based on a value of the virtual identifier included in the reception packet. The data register DREG 830 may latch and store the luminance data include in the reception packet based on the latch signal LATj. The driver DRU 840 may drive the light sources LED1˜LEDk connected to the slave driving circuits PDRi,j 800 based on the luminance data stored in the data register DREG 830.
The control circuit CLG 820 may include an address updater AUP, a decoder DEC and an address comparator ACMP.
The address comparator ACMP may compare the value ADD of the virtual identifier of the reception packet included in the data signal SDTi,j with a fixed address AFX and activate the latch signal LATj when the value ADD of the virtual identifier of the reception packet is identical to the fixed address AFX. The data register DREG 830 may latch and store the luminance data included in the reception packet in response to activation of the latch signal LATj. The decoder may check the error of the luminance data DMD based on the parity bits PRT as described with reference to
In some example embodiments, the address updater AUP in the control circuit CLG 820 may generate an updated value ADD′ by increasing or decreasing the value ADD of the virtual identifier of the reception packet and generate an address selection signal ASEL that is activated while the virtual identifier of the reception packet is output from the shift register SREG 810. The address selector AMX 811 may select the updated value ADD′ in response to activation of the address selection signal ASEL and select output ROUT of the shift register SREG 810 in response to deactivation of the address selection signal ASEL. As a result, the slave driving circuit PDRi,j 800 may transfer the transmission packet including the virtual identifier of the updated value ADD′ instead of the received value ADD to the slave driving circuit in the former stage.
Hereinafter, example embodiments of generating the latch signal using the virtual identifier by the address comparator ACMP and storing of the luminance data by the data register DREG 830 based on the latch signal are described with reference to
Referring to
For example, in case of the first packet PKTi,1, the fourth slave driving circuit PDRi,4 may receive the first packet PKTi,1 including the value of 3 of the virtual identifier VID during the first shifting period PD1, the third slave driving circuit PDRi,3 may receive the first packet PKTi,1 including the value of 2 of the virtual identifier VID during the second shifting period PD2, the second slave driving circuit PDRi,2 may receive the first packet PKTi,1 including the value of 1 of the virtual identifier VID during the third shifting period PD3, and the first slave driving circuit PDRi,1 may receive the first packet PKTi,1 including the value of 0 of the virtual identifier VID during the fourth shifting period PD4.
As such, the value of the virtual identifier VID may be decreased by one while passing through each slave driving circuit and all of the values of the virtual identifiers VID may be zero during the fourth shifting period PD4, with respect to the fourth packet PKTi,4 received by the fourth slave driving circuit PDRi,4, the third packet PKTi,3 received by the third slave driving circuit PDRi,3, the second packet PKTi,2 received by the second slave driving circuit PDRi,2, and the first packet PKTi,1 received by the first slave driving circuit PDRi,1.
As described above, the address comparator ACMP in the control circuit CLG 820 may compare the value of the virtual identifier VID of the reception packet included in the data signal with the fixed address AFX (e.g., zero) and activate the latch signal when the value of the virtual identifier VID of the reception packet is identical to the fixed address AFX.
As a result, the address comparators ACMP in the first through fourth slave driving circuits PDRi,1˜PDRi,4 may simultaneously activate the latch signals LAT1˜LAT4 at time point Ta, the data registers DREG 830 in the first through fourth slave driving circuits PDRi,1˜PDRi,4 may simultaneously latch and store the corresponding luminance data in the first through fourth packets PKTi,1˜PKTi,4 based on the latch signals LAT1˜LAT4.
Referring to
For example, in case of the first packet PKTi,1, the fourth slave driving circuit PDRi,4 may receive the first packet PKTi,1 including the value of 0 of the virtual identifier VID during the first shifting period PD1, the third slave driving circuit PDRi,3 may receive the first packet PKTi,1 including the value of 1 of the virtual identifier VID during the second shifting period PD2, the second slave driving circuit PDRi,2 may receive the first packet PKTi,1 including the value of 2 of the virtual identifier VID during the third shifting period PD3, and the first slave driving circuit PDRi,1 may receive the first packet PKTi,1 including the value of 3 of the virtual identifier VID during the fourth shifting period PD4.
As such, the value of the virtual identifier VID may be increased by one while passing through each slave driving circuit and all of the values of the virtual identifiers VID may be three during the fourth shifting period PD4, with respect to the fourth packet PKTi,4 received by the fourth slave driving circuit PDRi,4, the third packet PKTi,3 received by the third slave driving circuit PDRi,3, the second packet PKTi,2 received by the second slave driving circuit PDRi,2, and the first packet PKTi,1 received by the first slave driving circuit PDRi,1.
As described above, the address comparator ACMP in the control circuit CLG 820 may compare the value of the virtual identifier VID of the reception packet included in the data signal with the fixed address AFX (e.g., zero) and activate the latch signal when the value of the virtual identifier VID of the reception packet is identical to the fixed address AFX.
As a result, the address comparators ACMP in the first through fourth slave driving circuits PDRi,1˜PDRi,4 may simultaneously activate the latch signals LAT1˜LAT4 at time point Ta, the data registers DREG 830 in the first through fourth slave driving circuits PDRi,1˜PDRi,4 may simultaneously latch and store the corresponding luminance data in the first through fourth packets PKTi,1˜PKTi,4 based on the latch signals LAT1˜LAT4.
The identifiers to designate each of the slave driving circuits may be imposed through additional terminals for providing the identifiers or through an initialization operation to transfer signals such as command signals for providing the identifiers before the dimming operation. In these cases, the configuration of the slave driving circuit may become complex or the efficiency of the dimming operation may be degraded because the time of the initialization operation is increased.
In contrast, the slave driving circuit may not require the additional terminal to receive the identifier and the initialization process for imposing the identifier.
As such, the backlight system and the method of transferring luminance data according to example embodiments may reduce the size of the backlight and increase the speed of the local dimming operation by loading the luminance data to the corresponding slave driving circuit among the plurality of slave driving circuits connected in the daisy chain structure using the virtual identifier to omit configuration and operation for imposing identifiers to the slave driving circuits.
Referring to
The shift register 510 may receive a clock signal CLK and an input/output control signal DIO, and may generate a plurality of latch clock signals LCLK0 to LCLKn−1 based on the clock signal CLK. Each of the latch clock signals LCLK0 to LCLKn−1 may determine a latch point in time of the data latch 530 as a clock signal of a specific period.
The data latch 530 may store data DDT in response to the latch clock signals LCLK0 to LCLKn−1 provided by the shift register 510. The data latch 530 may output the stored data to the DAC 550 in response to a load signal TP. The data latch 530 may provide output signals DO to Dn−1 in response to the load signal TP. The DAC 550 may generate input voltage signals VIN0 to VINn−1, which are analog signals corresponding to the output signals D0 to Dn−1 of the data latch 530, using a gray voltage GMA.
The output buffer block 570 may buffer the input voltages signals VIN0 to VINn−1 and generate source driving signals, that is, the pad output voltage signals VPO0 to VPOn−1. The output buffer block 570 may include a plurality of output buffer circuits OBF respectively driving the source lines (or the data lines) of the display panel.
Referring to
The output enable signal SOEN may be deactivated during a pre-latch period tPL corresponding to a second portion of the unit period 1H and may be activate during an output period corresponding to a first portion of the unit period 1H.
The transfer of the luminance data as described above may be performed during the pre-latch period tPL. The latch operation of the data driver DDRV 500, which may be for example a source driver, and the transfer of the luminance data of the backlight system may be performed during the pre-latch period tPL in advance, and the data driver DDRV 500 and the backlight may commonly use the output enable signal SOEN and the synchronization between the display image by the pixels and the local dimming operation of the light sources may be implemented conveniently.
Referring to
Each packet as described above may include luminance data corresponding to each of the light sources LED1˜LEDk, and each luminance data may include first digital data DMDa for analog driving and second digital data DMDd for digital driving. For example, each luminance data corresponding to each light source may be 20-bit data such that the first digital data DMDa are eight bits and the second digital data DMDd are twelve bits.
The analog driver 841 may include a digital-to-analog converter DAC and sampling and holding circuits SH1˜SHk. The digital-to-analog converter DAC may convert the values of the first digital data DMDa of the luminance data stored in the data register to sequentially output voltages V1˜Vk corresponding to the values of the first digital data DMDa. The sampling and holding circuits SH1˜SHk may store the voltages V1˜Vk and provide driving currents ILed1˜ILedk to the light sources LED1˜LEDk connected to each slave driving circuit based on the voltages V1˜Vk.
The digital driver 842 may include a modulator MOD and dimming switches SWD1˜SWDk. The modulator MOD may generate pulse signals PL1˜PLk based on the values of the second digital data DMDd of the luminance data. In some example embodiments, the modulator MOD may perform a pulse width modulation (MOD) to convert the values of the second digital data DMDd to pulse widths of the pulse signals PL1˜PLk.
Referring to
Referring to
A conventional driver includes a plurality of digital-to-analog converters corresponding to the number of the light sources LED1˜LEDk to respectively generate the driving currents ILed1˜ILedk. In this case, the size and the power consumption may be increased as the number of the light sources LED1˜LEDk is increased.
As described with reference to
Referring to
A backlight system 13 and a slave driving circuit 801 of
Referring to
Referring to
The band gap reference circuit BGR may generate a reference voltage having a uniform voltage level regardless of operational conditions. The amplifier AMP and the transistor PM1 form a negative feedback loop and an output voltage of the amplifier may track the reference voltage from the band gap reference circuit BGR. As a result, a reference current IR flowing through the resistor Rtune from the power supply voltage VDD to the ground voltage VSS may have a uniform magnitude corresponding to the reference voltage.
The output voltage of the amplifier AMP may be applied commonly to the gate electrodes of the transistors PM1, PM2 and PM3. In some example embodiments, the size nX of the transistor PM3 may be n times the size 1× of the transistors PM1 and PM2. In this case, the reference current IR may be generated through the drain of the transistor PM2 and the amplified current nIR that is n times the reference current IR may be generated through the drain of the transistor PM3.
The path selector PMX may generate a monitoring current IMON based on a path control signal PSEL provided from the control circuit CLG 820 in
As such, each slave driving circuit may perform correlated double sampling to sample the reference current IR and the amplified current nIR.
The master driving circuit 603 in
The calibration circuit CAL in the master driving circuit 603 may compensate for the operational deviations based on the difference nIR-IR between the reference current IR and the amplified current nIR by the correlated double sampling. The effects by the external noises may be reduced through the correlated double sampling and the operational deviations of the slave driving circuits may be compensated exactly.
As described with reference to
Referring to
The luminance data may be transferred to the slave driving circuits by a frame rate (e.g., 60 Hz or 120 Hz) of a display device and the transferred luminance data may be used for the one frame period 1F corresponding to an inverse of the frame rate.
Referring to
The slave driving circuits in each dimming block row BRi may drive the corresponding light sources based on the corresponding luminance data DMDi during a first portion of the sub frames SF1˜SFp and based on black data BLD during a second portion of the sub frames SF1˜SFp. The black data BLD indicate the data that the luminance of the light from the light source is zero.
For example, as illustrated in
As such, an effect of inserting a black frame may be achieved by applying the black dimming for a portion of the sub frames, and the afterimage phenomenon in the display device may be relieved.
Referring to
The computing system 1100 may further include a radio frequency (RF) chip 1160, which may include a physical layer PHY 1161 and a DigRF slave 1162. A physical layer PHY 1113 of the application processor 1110 may perform data transfer with the physical layer PHY 1161 of the RF chip 1160 using a MIPI DigRF. The physical layer PHY 1113 of the application processor 1110 may interface (or for example communicate) a DigRF MASTER 1114 for controlling the data transfer with the physical layer PHY 1161 of the RF chip 1160.
The computing system 1100 may further include a global positioning system (GPS) 1120, a storage device 1170, a microphone 1180, a DRAM 1185 and/or a speaker 1190. The computing system 1100 may communicate with external devices using an ultra-wideband (UWB) communication interface 1210, a wireless local area network (WLAN) communication interface 1220, a worldwide interoperability for microwave access (WIMAX) communication interface 1230, or the like. However, embodiments are not limited to configurations or interfaces of the computing system 1000 and 1100 illustrated in
According to example embodiments, the display device 1150 includes a backlight system BLS including a master driving circuit and a backlight as described above. The backlight may include a plurality of slave driving circuits and a plurality of light sources driven by the plurality of slave driving circuits. The plurality of slave driving circuits may be arranged in a matrix of driving rows and driving columns such that first through m-th slave driving circuits arranged in each driving row are connected in a daisy chain structure. The master driving circuit may generate a plurality of input data signals. Each input data signal corresponding to each driving row may include first through m-th packets including luminance data to be loaded respectively to the first through m-th slave driving circuits.
As described above, the backlight system according to example embodiments may reduce the number of wirings of the backlight and enhance noise margin by connecting the slave driving circuits in the daisy chain structure and transferring the luminance data by a digital scheme. In addition, the backlight system and the method of transferring luminance data according to example embodiments may reduce the size of the backlight and increase the speed of the local dimming operation by loading the luminance data to the corresponding slave driving circuit among the plurality of slave driving circuits connected in the daisy chain structure using the virtual identifier to omit configuration and operation for imposing identifiers to the slave driving circuits.
Embodiments may be applied to a display device and any electronic devices and systems including the display device. For example, embodiments may be applied to systems such as a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, a personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, a wearable device, an internet of things (IoT) device, an internet of everything (IoE) device, an e-book, a virtual reality (VR) device, an augmented reality (AR) device, a vehicle navigation system, a video phone, a monitoring system, an auto focusing system, a tracking system, a motion monitoring system, etc.
The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2020-0130199 | Oct 2020 | KR | national |
| 10-2020-0154074 | Nov 2020 | KR | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 8482698 | Atkins | Jul 2013 | B2 |
| 8786191 | Kuang et al. | Jul 2014 | B2 |
| 8878828 | Baek et al. | Nov 2014 | B2 |
| 10121454 | Ninan et al. | Nov 2018 | B2 |
| 20050168429 | Chou | Aug 2005 | A1 |
| 20070223477 | Eidson | Sep 2007 | A1 |
| 20090066676 | Jo | Mar 2009 | A1 |
| 20180350308 | Zhang | Dec 2018 | A1 |
| Number | Date | Country |
|---|---|---|
| 10-1885186 | Aug 2018 | KR |
| 10-2019-0006007 | Jan 2019 | KR |
| 10-2012994 | Aug 2019 | KR |
| Number | Date | Country | |
|---|---|---|---|
| 20220114975 A1 | Apr 2022 | US |
