Patent Application
20150221249
This application claims priority from and the benefit of Korean Patent Application No. 10-2014-0012183, filed on Feb. 3, 2014, which is hereby incorporated by reference for all purposes as if fully set forth herein.
1. Field
Exemplary embodiments of the inventive concept described herein relate to a backlight unit and a display device including the same.
2. Discussion of the Background
As a user interface, a display device has become an essential component of an electronic device. A flat panel display device is typically used for implementation of light, thin, and low-power electronic devices.
The most common flat panel display device is a liquid crystal display (LCD) device. The LCD device is configured to receive light and display images by adjusting the amount of light received from the outside; hence, it includes a separate light source for providing a light to a liquid crystal panel. For example, the light source may be a backlight unit with a backlight lamp.
In recent years, low-power, slim, and eco-friendly LEDs (light emitting diodes) have been widely used as a light source. In such case, implementing uniform brightness and color over an entire display device is difficult in terms of optical design. Also, a high technology is required to instantly adjust a current of a light emitting diode for color combination.
The backlight unit contains a plurality of light emitting diode strings to provide brightness the display device requires. The same amount of current may be supplied to each of the plurality of light emitting diode strings for uniform brightness among each of the light emitting diode strings.
Each of the light emitting diode strings has a plurality of light emitting diodes that are connected in series. If a forward voltage across the serially-connected light emitting diodes is identical, upon providing the voltage to one end of the light emitting diode strings, the amount of current flowing via each of the light emitting diode strings may be constant.
In the event that forward voltages of light emitting diodes are different from one another because of a process variation, however, voltage levels of the other ends of the light emitting diode strings may be different from one another. Light emitting diodes may be damaged upon a sharp increase in a voltage level of the other end of any light emitting diode string.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form any part of the prior art nor what the prior art may suggest to a person of ordinary skill in the art.
Exemplary embodiments of the present inventive concept provide a backlight unit comprising a controller; a power converter configured to generate a light-source voltage in response to a control of the controller; and at least one light emitting diode string connected between a first node and a second node and supplied with the light-source voltage via the first node.
Exemplary embodiments of the present inventive concept also provide a display device including the same.
Additional features of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention.
An exemplary embodiment of the present invention discloses a backlight unit including, a controller configured to generate a control signal, a power converter configured generate a light-source voltage in response to the control signal, and at least one light emitting diode string connected between a first node and a second node and supplied with the light-source voltage from the first node, wherein the controller includes a current controller configured to adjust a current flow through the light emitting diode string, and an overvoltage controller connected between the light emitting diode string and the current controller, including a passive element, wherein the overvoltage controller is configured to connect the passive element between the second node and the current controller when a voltage of the second node of the light emitting diode is higher than a reference voltage.
An exemplary embodiment of the inventive concept also provides a display device including a display panel including a plurality of pixels, a driver circuit configured to control the display panel so as to display images, and a backlight unit configured to supply a light to the display panel, wherein the backlight unit comprises a controller configured to generate a control signal, a power converter configured to generate a light-source voltage in response to the control signal; and at least one light emitting diode string connected between a first node and a second node and supplied with the light-source voltage from the first node, wherein the controller includes a current controller configured to adjust a current flow through the light emitting diode string, and an overvoltage controller connected between the light emitting diode string and the current controller, including a passive element, wherein the overvoltage controller is configured to connect the passive element between the second node and the current controller when a voltage of the second node of the light emitting diode is higher than a reference voltage.
With embodiments of the inventive concept, a backlight unit decreases a voltage level using a passive element when a voltage level of one of the other ends of light emitting diode strings sharply increases due to a difference between forward voltages of the light emitting diode strings. Thus, it is possible to limit the damage due to a difference between forward voltages of the light emitting diode strings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the principles of the invention.
Embodiments will be described in detail with reference to the accompanying drawings. The inventive concept, however, may be embodied in various different forms, and should not be construed as being limited only to the illustrated embodiments. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the concept of the inventive concept to those skilled in the art. Accordingly, known processes, elements, and techniques are not described with respect to some of the embodiments of the inventive concept. Unless otherwise noted, like reference numerals denote like elements throughout the attached drawings and written description, and thus descriptions will not be repeated. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.
It will be understood that, although the terms “first”, “second”, “third”, etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.
Spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be understood that for the purposes of this disclosure, “at least one of X, Y, and Z” can be construed as X only, Y only, Z only, or any combination of two or more items X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Also, the term “exemplary” is intended to refer to an example or illustration.
It will be understood that when an element or layer is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another element or layer, it can be directly on, connected, coupled, or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to”, “directly coupled to”, or “immediately adjacent to” another element or layer, there are no intervening elements or layers present.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Referring to
The display panel 110 displays images. In exemplary embodiments, the display panel 110 may be a liquid crystal display panel, but the inventive concept is not limited thereto. For example, the display panel 110 may be any type of display panel that necessitates the backlight unit 130.
The display panel 110 may include a plurality of gate lines GL1 to GLn extending in a first direction D1, a plurality of data lines DL1 to DLm extending in a second direction D2, and a plurality of pixels PX arranged at each intersection between each of the plurality of gate lines GL1 to GLn and each of the plurality of data lines DL1 to DLm. The plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm are isolated from one another. Each pixel PX includes a thin film transistor TR, a liquid crystal capacitor CLC, and a storage capacitor CST.
Since each of the plurality of pixels PX have the same structure, its structure will be described using one pixel. The thin film transistor TR of the pixel PX has a gate electrode connected to a first gate line GL1 of the gate lines GL1 to GLn, a source electrode connected to a first data line DL1 of the data lines DL1 to DLm, and drain electrode connected to the capacitors CLC and CST. One ends of the capacitors CLC and CST are connected in parallel to the drain electrode of the thin film transistor TR, and the other ends thereof are connected to a common voltage.
The driver circuit 120 includes a timing controller 122, a gate driver 124, and a data driver 126. The timing controller 122 receives an image signal RGB and control signals CTRL from an external device. The control signals CTRL may include, for example, a vertical synchronization signal, a horizontal synchronization signal, a main clock signal, a data enable signal, etc. Based on the control signals CTRL, the timing controller 122 provides the data driver 126 with a data signal DATA and a first control signal CTRL1 and the gate driver 124 with a second control signal CTRL2. Here, the data signal may be generated by processing an image signal to be suitable for an operating condition of the display panel 110. The first control signal CTRL1 includes a horizontal synchronization start signal, a clock signal, and a line latch signal, and the second control signal CTRL2 includes a vertical synchronization start signal, an output enable signal, and a gate pulse signal.
The timing controller 122 changes the data signal DATA variably, based on arrangement of the pixels of the display panel 110 and a display frequency. The timing controller 122 provides the backlight unit 130 with a backlight control signal BLC for controlling the backlight unit 130.
The gate driver 124 drives the gate lines GL1 to GLn in response to the second control signal CTRL2 from the timing controller 122. The gate driver 124 may include a gate driver IC. The gate driver 124 may be implemented with a circuit using at least one of oxide semiconductor, amorphous semiconductor, crystalline semiconductor, polycrystalline semiconductor, etc.
The data driver 126 drives the data lines DL1 to DLm in response to the first control signal CTRL1 and the data signal DATA from the timing controller 122.
The backlight unit 130 is disposed under the display panel 110 to be opposite to the pixels PX. The backlight unit 130 operates in response to the backlight control signal BLC from the timing controller 122. A structure and an operation of the backlight unit 130 will be more fully described with reference to
Referring to
Each of the light emitting diode strings 221, 222, and 223 includes a plurality of light emitting diodes connected in series. The light emitting diodes may include a white light emitting diode emitting white light, a red light emitting diode emitting red light, a green light emitting diode emitting green light, and a blue light emitting diode emitting blue light. Emission characteristics of the white, red, green, and blue light emitting diodes are different from one another. In particular, the white, red, green, and blue light emitting diodes may each have different forward driving voltages Vf to emit light. Using Light emitting diodes with relatively lower forward driving voltage Vf may reduce overall power consumption. Also, a difference between forward driving voltages Vf of light emitting diodes may be decreased for uniform brightness. In exemplary embodiments, the light source 220 includes the light emitting diode strings 221, 222, and 223 formed of a plurality of light emitting diodes, but the inventive concept is not limited thereto. For example, the light source 220 may include at least one of laser diodes and carbon nano tubes.
One ends of the light emitting diode strings 221, 222, and 223 are connected to receive a light-source voltage VLED from the power converter 210 through a first node N11. The other ends of the light emitting diode strings 221, 222, and 223, that is, a second node N12, a third node N13, and a fourth node N14 are connected to the controller 230.
The power converter 210 converts a power supply voltage EVDD from an external device into the light-source voltage VLED. The light-source voltage VLED may be set to a voltage level sufficient for driving light emitting diodes of the light emitting diode strings 221, 222, and 223.
The power converter 210 includes an inductor 211, an NMOS transistor 212, a diode 213, and a capacitor 214. The inductor 211 is connected between a power supply voltage EVDD from an external device and a node Q1. The NMOS transistor 212 is connected between the node Q1 and a ground voltage and has a gate connected to receive a voltage control signal CTRLV from the controller 230. The diode 213 is connected between the node Q1 and a node Q2. In exemplary embodiments, the diode 213 may be formed of a Schottky diode. The capacitor 214 is connected between the node Q2 and the ground voltage. A light-source voltage VLED of the node Q2 is supplied to one ends of the light emitting diode strings 221, 222, and 223.
The power converter 210 converts the power supply voltage EVDD into the light-source voltage VLED. In particular, a level of the light-source voltage VLED may be adjusted by turning on or off the NMOS transistor 212 in response to the voltage control signal CTRLV.
The controller 230 receives a power supply voltage VCC. The controller 230 operates in response to a backlight control signal BLC from a timing controller 122 (refer back to
Referring to
The first controller 230A, the second controller 230B, and the third controller 230C are respectively connected to the second node N12 connected to the other end of a light emitting diode string 221, the third node N13 connected to the other end of a light emitting diode string 222, and the fourth node N14 connected to the other end of a light emitting diode string 223.
Referring to
The first transistor TF1 is connected in parallel with the fourth resistor RF4 between the second node N12 and the first internal node N21 and has a gate electrode connected to a third internal node N23. The first resistor RF1 and the second resistor RF2 are sequentially connected in series between the second node N12 and a ground voltage.
The first comparator 311 compares a voltage of a second internal node N22, a connection between the first resistor RF1 and the second resistor RF2, with a first reference voltage VREF1 and outputs a first comparison signal CMP1 as a comparison result. The third resistor RF3 is connected between the power supply voltage VCC and a third internal node N23. The second transistor TF2 is connected between the third internal node N23 and the ground voltage and has a gate electrode connected to the output of the first comparator 311 to receive the comparison signal CMP1.
The current controller 320 includes a third transistor TF3, a sixth resistor RF6, and a second comparator 321. The third transistor TF3 is connected between the first internal node N21 and a fourth internal node N24 and has a gate electrode connected to the output of the second comparator 321. The sixth resistor RF6 is connected between the fourth internal node N24 and the ground voltage. The second comparator 321 compares a voltage of the fourth internal node N24 with a second reference voltage VREF2 to output a second comparison signal CMP2. The second comparison signal CMP2 is provided to a gate electrode of the third transistor TF3.
When a voltage of the fourth internal node N24 is lower than the second reference voltage VREF2, the second comparator 321 outputs a high level of second comparison signal CMP2; hence, the third transistor TF3 is turned on. When a voltage of the fourth internal node N24 is higher than the second reference voltage VREF2, the second comparator 321 outputs a low level of second comparison signal CMP2. At this time, the third transistor TF3 is turned off by the low level of second comparison signal CMP2. As a turn-on time of the third transistor TF3 is decided according to a voltage of the fourth internal node N24, the current controller 320 adjusts the amount of current flowing via the light emitting diode string 221.
Referring to
Referring to
That is, when a voltage level of the second node N12 is at a normal level, the first transistor TF1 is turned on, and the drain terminal of the third transistor TF3 of a current controller 320 is directly connected to the second node N12.
Referring to
Referring to
Referring back to example shown in
Referring to
The second node N12 and the first internal node N21 are connected with passive elements including a diode DF1, a capacitor CF1, and a fifth resistor RF5. The diode DF1 is connected between the second node N12 and a first internal node N21. The capacitor CF1 and the fifth resistor RF5 are connected in series between the second node N12 and the first internal node N21, in parallel with the diode DF1.
Like a first controller 230A shown in
In contrast, if a voltage level of the second node N12 is higher than the normal level, the first transistor TF1 is turned off. At this time, a current of the second node N12 flows to the third transistor TF3 via a diode DF1, a capacitor CF1, and a resistor RF5. Thus, an overvoltage is limited from being supplied to the drain terminal of the third transistor TF3 when a voltage level of the second node N12 is higher than the normal level.
Referring to
Like a first controller 230A shown in
A fourth resistor RF4 of the overvoltage controller 510 is connected between the first internal node N21 and the fourth internal node N24. In exemplary embodiments, the fourth resistor RF4 is used as a passive element connected between the first internal node N21 and the fourth internal node N24, but the present inventive concept is not limited thereto. For example, passive element connected between the second node N12 and the first internal node N21 may include at least one of a capacitor, an inductor, a diode, and the like.
The first transistor TF1 is connected in parallel with the fourth resistor RF4 between the first internal node N21 and the fourth internal node N24 and has a gate electrode connected to a third internal node N23. The first resistor RF1 and the second resistor RF2 are sequentially connected in series between the second node N12 and a ground voltage.
The first comparator 311 compares a voltage of a second internal node N22, being a connection between the first resistor RF1 and the second resistor RF2, with a first reference voltage VREF1 and outputs a first comparison signal CMP1 as a comparison result. The third resistor RF3 is connected between a power supply voltage VCC and a third internal node N23. The second transistor TF2 is connected between the third internal node N23 and the ground voltage and has a gate electrode connected to receive the comparison signal CMP1.
When a voltage of the second node N12 is at a normal level, the first transistor TF1 is turned on; therefore, the current flows via the light emitting diode string 221, the third transistor TF3, the first transistor TF1, and the sixth resistor RF6. If a voltage of the second node N12 is higher than the normal level, the first transistor TF1 is turned off. The current flows via the light emitting diode string 221, the third transistor TF3, the fourth resistor RF4, and the sixth resistor RF6. Since the voltage is dropped by the fourth resistor RF4, an overvoltage may be limited from being supplied to the third transistor TF3.
While the inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention. Therefore, it should be understood that the above embodiments are not limiting, but illustrative, and it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2014-0012183 | Feb 2014 | KR | national |
