BACKSIDE DIELECTRIC LINERS

BACKGROUND

Complementary Metal-oxide-semiconductor (CMOS) technology is commonly used for field effect transistors (hereinafter “FET”) as part of advanced integrated circuits (hereinafter “IC”), such as central processing units (hereinafter “CPUs”), memory, storage devices, and the like. As demands to reduce the dimensions of transistor devices continue, nanosheet FETs help achieve a reduced FET device footprint while maintaining FET device performance. A nanosheet FET includes a plurality of stacked nanosheets extending between a pair of source drain epitaxial regions. The device may be a gate-all-around device or transistor in which the gate surrounds a portion of the nanosheet channel. A nanosheet device contains one or more layers of semiconductor channel material portions having a vertical thickness that is substantially less than its width.

SUMMARY

According to an embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include a nanosheet transistor device including a backside source drain contact, where the backside source drain contact includes a top portion, a middle portion, and a bottom portion, and a dielectric liner disposed along sidewalls of the top portion of the backside source drain contact.

According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include a nanosheet transistor device including a backside source drain contact, where the backside source drain contact includes a top portion having a first width, a middle portion having a second width, and a bottom portion having a third width, and a dielectric liner disposed along sidewalls of the first portion of the backside source drain contact.

According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include a nanosheet transistor device including a source drain region and a backside source drain contact, where the backside source drain contact includes a top portion having a first width, a middle portion having a second width, and a bottom portion having a third width, where the first width of the top portion is substantially equal to a width of the source drain region, and a dielectric liner disposed along sidewalls of the first portion of the backside source drain contact.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description, given by way of example and not intended to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, in which:

FIG. 1, a top view of a generic structure is shown to provide spatial context to the different cross-sectional views and structural orientations of the semiconductor structures shown in the subsequent figures;

FIGS. 2 and 3 are cross-sectional views of the semiconductor structure during an intermediate step of a method of fabricating nanosheet transistor structures according to an exemplary embodiment;

FIGS. 4 and 5 are cross-sectional views of the semiconductor structure after flipping the assembly and recessing the substrate according to an exemplary embodiment;

FIGS. 6 and 7 are cross-sectional views of the semiconductor structure after removing and recessing remaining portions of the substrate and trimming the placeholders according to an exemplary embodiment;

FIGS. 8 and 9 are cross-sectional views of the semiconductor structure after forming a dielectric liner according to an exemplary embodiment;

FIGS. 10 and 11 are cross-sectional views of the semiconductor structure after forming a mask and removing portions of the dielectric liner according to an exemplary embodiment;

FIGS. 12 and 13 are cross-sectional views of the semiconductor structure after removing the mask and forming a backside dielectric layer according to an exemplary embodiment;

FIGS. 14 and 15 are cross-sectional views of the semiconductor structure after forming a backside contact mask and backside contact trenches according to an exemplary embodiment;

FIGS. 16 and 17 are cross-sectional views of the semiconductor structure after removing some of the placeholders according to an exemplary embodiment;

FIGS. 18 and 19 are cross-sectional views of the semiconductor structure after enlarging the backside contact trenches according to an exemplary embodiment; and

FIGS. 20 and 21 are cross-sectional views of the semiconductor structure after forming backside contact structures and backside wiring layers according to an exemplary embodiment;

The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. For clarity and ease of illustration, scale of elements may be exaggerated. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements.

DETAILED DESCRIPTION

Detailed embodiments of the claimed structures and methods are disclosed herein; however, it can be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

References in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Also, the term “sub-lithographic” may refer to a dimension or size less than current dimensions achievable by photolithographic processes, and the term “lithographic” may refer to a dimension or size equal to or greater than current dimensions achievable by photolithographic processes. The sub-lithographic and lithographic dimensions may be determined by a person of ordinary skill in the art at the time the application is filed.

The terms substantially, substantially similar, about, or any other term denoting functionally equivalent similarities refer to instances in which the difference in length, height, or orientation convey no practical difference between the definite recitation (e.g. the phrase sans the substantially similar term), and the substantially similar variations. In one embodiment, substantial (and its derivatives) denote a difference by a generally accepted engineering or manufacturing tolerance for similar devices, up to, for example, 10% deviation in value or 10° deviation in angle.

In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention.

Complementary field effect transistors, including gate-all-around transistor devices and nanosheet transistor devices, have known advantages over conventional transistor structures in terms of density, performance, power consumption, and integration. However, fabricating device contacts on a backside of the wafer presents unique challenges. More specifically, for example, conventional backside contacts and placeholder fabrication techniques run the risk of shorting the backside contact to the gate.

The present invention generally relates to semiconductor structures, and more particularly to nanosheet transistor structures having backside dielectric liners to prevent shorting between direct backside contacts and gate structures. More specifically, the nanosheet transistor structures and associated method disclosed herein enable a novel solution for providing backside dielectric liners to prevent shorting between direct backside contacts and gate structures. Exemplary embodiments of nanosheet transistor structures having backside dielectric liners to prevent shorting between direct backside contacts and gate structures are described in detail below by referring to the accompanying drawings in FIGS. 1 to 21. Those skilled in the art will readily appreciate that the detailed description given herein with respect to these figures is for explanatory purposes as the invention extends beyond these limited embodiments.

Referring now to FIG. 1, a top view of a generic structure is shown to provide spatial context to the different cross-sectional views and structural orientations of the semiconductor structures shown in the figures and described below. Additionally, XYZ Cartesian coordinates may be also shown in each of the drawings to provide additional spatial context. The terms “vertical” or “vertical direction” or “vertical height” as used herein denote a Z-direction of the Cartesian coordinates shown in the drawings, and the terms “horizontal,” or “horizontal direction,” or “lateral direction” as used herein denote an X-direction and/or a Y-direction of the Cartesian coordinates shown in the drawings.

The generic structure illustrated in FIG. 1 shows multiple fins/stacks and multiple gate regions situated perpendicular to one another. FIGS. 1-21 represent cross section views oriented as indicated in FIG. 1

Referring now to FIGS. 2 and 3, a structure 100 is shown during an intermediate step of a method of fabricating a nanosheet transistor structure according to an embodiment of the invention. FIG. 2 depicts a cross-sectional view of the structure 100 shown in FIG. 3 taken along line X-X and FIG. 3 depicts a cross-sectional view of the structure 100 shown in FIG. 4 taken along line Y-Y.

The structure 100 illustrated in FIGS. 2-3 includes an array of nanosheet transistors formed on a substrate 102 in accordance with known techniques. As illustrated, the array of nanosheet transistors includes nanosheet stacks 104. Each nanosheet stack 104 includes a plurality of silicon channels 106 surrounded by a single gate 108. For purposes of orientation, the substrate 102 is herein referred to as being on a “backside” of the structure 100 and the array of nanosheet transistors are herein referred to as being on a “frontside” of the structure 100. Further, certain features may be described herein as having a relative position with respect to the frontside or backside of the structure 100.

The substrate 102 may be a layered semiconductor such as a silicon-on-insulator or SiGe-on-insulator, where an etch stop layer 110 separates a base substrate 112 from a top semiconductor layer 114. Unlike conventional layered semiconductor substrates, the etch stop layer 110 of the substrate 102 may include any material which affects the desired etch selectivity during subsequent processing. For example, the etch stop layer 110 may be a conventional buried oxide layer, or it may be a silicon germanium layer with a specific germanium concentration. In practice, the etch stop layer 110 will function as an etch stop layer and can be composed of any material which supports that function.

In the present embodiment, both the base substrate 112 and the top semiconductor layer 114 may be any bulk substrate made from any of several known semiconductor materials such as, for example, silicon, germanium, silicon-germanium alloy, and compound (e.g. III-V and II-VI) semiconductor materials. For example, both the base substrate 112 and the top semiconductor layer 114 may be made from silicon. Additionally, both the etch stop layer 110 and the base substrate 112 are sacrificial and will not remain in the final structure. As such, thickness of the top semiconductor layer 114, and similarly the position of the etch stop layer 110, approximately denote a relative position of subsequently formed backside features, such as, backside wiring layers or a backside power delivery network.

The structure 100 further includes placeholders 116, buffer layers 118, and source drain regions 120 generally arranged between adjacent nanosheet stacks 104, as illustrated.

The placeholders 116 are formed by filling self-aligned openings in the top semiconductor layer 114 between adjacent nanosheet stacks 104 with a sacrificial material according to known techniques. Specifically, after filling, the sacrificial material is recessed to create the placeholders 116 according to known techniques. In an embodiment, the sacrificial material is silicon germanium epitaxially grown from the surfaces of the top semiconductor layer 114. In another embodiment, the sacrificial material is SiC, SiOC deposited using, for example, chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD) and subsequently recessed using, for example, reactive ion etching (RIE). Other suitable deposition and recessing techniques may be used provided they do not induce a physical or chemical change to the silicon channels 106.

The buffer layers 118 are formed on top of the placeholders 116 according to known techniques. Specifically, an etch stop material is formed directly on top of the placeholders 116. In an embodiment, the etch stop material can be any silicon-based material suitable to provide needed etch stop properties during backside processing. For example, the buffer layers 118 are designed to allow the subsequent removal of the placeholders 116 selective to the source drain regions 120.

The source drain regions 120 are formed on top of the buffer layer 118 according to known techniques. Specifically, the source drain regions 120 are disposed between adjacent nanosheet stacks 104 in direct contact with exposed ends of the silicon channels 106. More specifically, the source drain regions 120 may be epitaxially grown from the exposed ends of the silicon channels 106 according to known techniques.

The structure 100 further includes shallow trench isolation regions (hereinafter “STI regions”) which extend partially into the substrate 102 below the array of nanosheet transistors. In general, the STI regions may each include an isolation liner 122 and an isolation fill 124. For example, the isolation liner 122 is SiN, SiON, or SiOCN, and the isolation fill 124 is silicon oxide (SiO) or silicon nitride (SiN).

The structure 100 further includes stack spacers 126, inner spacers 128, and gate spacers 130.

The stack spacers 126 are disposed directly beneath the nanosheet stacks 104 separating them from the substrate 102. Specifically, for example, a relatively thin layer of silicon nitride is conformally deposited prior to forming the nanosheet stacks 104. In some embodiments, for example, the stack spacers 126 may be composed of SiN, SiBCN, SiOCN, SiOC, or any other combination of low-k materials. Like the buffer layers 118, the stack spacers 126 can provide etch selectivity during backside processing.

As used herein, “conformal” it is meant that a material layer has a continuous thickness, or substantially continuous thickness. For example, a continuous thickness generally means a first thickness as measured from a bottom surface to a topmost surface that is the same as a second thickness as measured from an inner sidewall surface to an outer sidewall surface.

The inner spacers 128 are disposed between alternate channels (106), and laterally separate the gates 108 from the source drain regions 120, as illustrated. The inner spacers 128 provide necessary electrical insulation between the gates 108 and the source drain regions 120.

The gate spacers 130 are added to define the channel length and the source drain regions, and ultimately electrically insulate the gates 108 from subsequently formed structures, such as, for example, source drain contact structures. The gate spacers 130 are critical for electrically insulating the gates 108 from the source drain regions 120 or subsequently formed contact structures. In at least one embodiment, the gate spacers 130 include silicon nitride, silicon boron nitride, silicon carbon nitride, silicon boron carbon nitride, or other known equivalents.

Finally, the structure 100 further includes a dielectric layer 132 directly above and surrounding the source drain regions 120. The dielectric layer 132 is composed of any suitable interlayer dielectric material, such as, for example, oxides such as silicon oxide (SiO_x), nitrides such as silicon nitride (Si_xN_y), and/or low-κ materials such as SiCOH or SiBCN. In another embodiment, is composed of silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer or any combination thereof. In yet another embodiment, a self-planarizing material such as a spin-on glass (SOG) or a spin-on low-k dielectric material such as SiLK™ can be used to form the dielectric layer 132. Using a self-planarizing dielectric material as the dielectric layer 132 can avoid the need to perform a subsequent planarizing step. After formation, top surfaces of the dielectric layer 132 are typically made flush, or substantially flush, with top surfaces of the gates 108 and the gate spacers 130 by chemical mechanical polishing techniques.

The structure 100 further includes a middle-of-line 134, a back-end-of-line 136, a carrier wafer 138.

The middle-of-line 134 includes source drain contacts 140 and gate contacts 142 which may be generally referred to as middle-of-line contacts. The source drain contacts 140 and the gate contacts 142 are formed according to known techniques. The back-end-of-line 136 may include vias and metal lines which may be generally referred to as back-end-of-line interconnects. The vias and the metal lines are formed according to known techniques. Finally, the wafer 138 is secured to a top of the structure 100 according to an embodiment of the invention. The carrier wafer 138 is attached, or removably secured, to the back-end-of-line 136. In general, and not depicted, the carrier wafer 138 may be thicker than the other layers. Temporarily bonding the structure 100 to a thicker carrier provides improved handling and additional support for backside processing of thin wafers. After backside processing described below, the structure 100 may be de-bonded, or removed, from the carrier wafer 138 according to known techniques.

Although only a limited number of components, devices, or structures are shown, embodiments of the present invention shall not be limited by any quantity otherwise illustrated or discussed herein.

Referring now to FIGS. 4 and 5, the structure 100 is shown after flipping the assembly and recessing the substrate 102 according to an embodiment of the invention. FIG. 4 depicts a cross-sectional view of the structure 100 shown in FIG. 5 taken along line X-X and FIG. 5 depicts a cross-sectional view of the structure 100 shown in FIG. 4 taken along line Y-Y.

First, the structure 100 is flipped 180 degrees to prepare for backside processing. In general, backside processing includes fabrication or processing of the structure 100 opposite the active device and wiring layers. Next, the substrate 102 is recessed according to known techniques. Specifically, the base substrate 112 is recessed or completely removed to expose the etch stop layer 110, as shown. It is noted, the orientation of the cross-sectional views referenced and illustrated hereafter will remain unchanged despite the actualities of flipping of the structure 100 for purposes of fabrication. As such, all references to “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall continue to relate to the disclosed structures and methods, as oriented in the drawing figures.

Referring now to FIGS. 6 and 7, the structure 100 is shown after removing and recessing remaining portions of the substrate 102 and trimming the placeholders 116 according to an embodiment of the invention. FIG. 6 depicts a cross-sectional view of the structure 100 shown in FIG. 7 taken along line X-X and FIG. 7 depicts a cross-sectional view of the structure 100 shown in FIG. 6 taken along line Y-Y.

First, the etch stop layer 110 is selectively removed and the top semiconductor layer 114 is recessed according to known techniques. Specifically, the etch stop layer 110 is removed selective to the top semiconductor layer 114 and the top semiconductor layer 114 is removed selective to the placeholders 116, the stack spacers 126, the gates 108, and the STI regions, as illustrated. As indicated in the figures, some erosion of the placeholders 116 is anticipated to be an unintended consequence resulting from selectively removing the top semiconductor layer 114.

Referring now to FIGS. 8 and 9, the structure 100 is shown after forming a dielectric liner 144 according to an embodiment of the invention. FIG. 8 depicts a cross-sectional view of the structure 100 shown in FIG. 9 taken along line X-X and FIG. 9 depicts a cross-sectional view of the structure 100 shown in FIG. 8 taken along line Y-Y.

First, the dielectric liner 144 is formed across the backside of the structure 100 according to known techniques. Specifically, a dielectric liner material is conformally deposited across exposed surfaces on the backside of the structure 100 including directly on the placeholders 116 and the stack spacers 126 (see FIG. 9) and within the openings between STI regions (see FIG. 9), as illustrated. In some embodiments, for example, the dielectric liner 144 may be composed of other low-k materials, such as, for example, SiN, SiBCN, SiOCN, SiOC, or other combinations thereof. According to embodiments of the present invention, the dielectric liner 144 provide etch selectivity during backside processing.

Referring now to FIGS. 10 and 11, the structure 100 is shown after forming a mask 146 and removing portions of the dielectric liner 144 according to an embodiment of the invention. FIG. 10 depicts a cross-sectional view of the structure 100 shown in FIG. 11 taken along line X-X and FIG. 11 depicts a cross-sectional view of the structure 100 shown in FIG. 10 taken along line Y-Y.

First, the mask 146 is deposited and subsequently recessed to expose certain portions of the structure 100 according to known techniques. The mask 146 can be an organic planarization layer (OPL) or a layer of material that is capable of being planarized or etched by known techniques. In an embodiment, for example, the mask 146 can be an amorphous carbon layer able to withstand subsequent processing temperatures. The mask 146 can preferably have a thickness sufficient to cover existing structures. After deposition of the mask 146, a dry etching technique is applied to pattern or recess the mask 146 according to known techniques. The mask 146 is preferably recessed at least to expose portions of the dielectric liner 144 to a point somewhere above bottommost surfaces of the placeholders 116. According to an embodiment, for example, the mask 146 is recessed a depth equal to approximately 30 percent to 70 percent of the total height of the placeholder 116.

Next, exposed portions of the dielectric liner 144 are selectively remove according to known techniques. Specifically, exposed portions of the dielectric liner 144 are removed using known etching techniques suitable to remove nitrides selective to the placeholders 116 and the mask 146. In an embodiment, the exposed portions of the dielectric liner 144 are removed using an anisotropic etch such as, for example, reactive ion etching. After removing the exposed portions of the dielectric liner 144, bottom portions of the placeholders 116 are exposed.

In all cases, at least portions of the dielectric liner 144 must remain along sidewalls of the placeholders 116 as illustrated. For example, the portions of the dielectric liner 144 remaining along sidewalls of the placeholders 116 will be approximately 70 percent to approximately 30 percent of the total height of the placeholders 116. In such cases, for example, about 30 percent to about 70 percent of the total height of the placeholders 116 are exposed. In all cases, the primary goal is to cause a reasonably long portion the dielectric liner 144 to remain along sidewalls of the placeholders 116 in order to effectively limit or control a topmost portion of a subsequently formed backside contact, as described below.

at least to expose portions of the dielectric liner 144 to a point somewhere above bottommost surfaces of the placeholders 116.

Furthermore, at least vertical portions of the dielectric liner 144 also remain along sidewalls of the STI regions and protect bottommost portions of the gates 108, as best illustrated in FIG. 11.

Referring now to FIGS. 12 and 13, the structure 100 is shown after removing the mask 146 and forming a backside dielectric layer 148 according to an embodiment of the invention. FIG. 12 depicts a cross-sectional view of the structure 100 shown in FIG. 13 taken along line X-X and FIG. 13 depicts a cross-sectional view of the structure 100 shown in FIG. 12 taken along line Y-Y.

First, the mask 146 is removed according to known techniques. Next, the backside dielectric layer 148 is deposited according to known techniques. Specifically, a backside dielectric material is blanket deposited across the structure 100. The backside dielectric layer 148 completely covers remaining portions of the dielectric liner 144 and the placeholders 116. After deposition, known chemical mechanical polishing may be used to remove excess portions of the backside dielectric material from bottom surfaces of the structure 100.

Referring now to FIGS. 14 and 15, the structure 100 is shown after forming a backside contact mask 150 and backside contact trenches 152 according to an embodiment of the invention. FIG. 14 depicts a cross-sectional view of the structure 100 shown in FIG. 15 taken along line X-X and FIG. 15 depicts a cross-sectional view of the structure 100 shown in FIG. 14 taken along line Y-Y.

First, a hard mask material is deposited on the structure 100. According to an exemplary embodiment, the hard mask material is deposited onto the backside of the structure 100, and then patterned into a plurality of individual hard masks, hereinafter the backside contact mask 150. The backside contact mask 150, and subsequently formed backside contact trenches 152, define positions or locations of future backside contacts.

Next, the pattern created by the backside contact mask 150 is transferred into the backside dielectric layer 148, as illustrated. Specifically, portions of the backside dielectric layer 148 are etched or removed to form the backside contact trenches 152. Portions of the backside dielectric layer 148 are etched or removed selective to the STI regions to a depth sufficient to expose certain placeholders 116 aligned with the backside contact mask 150. The portions of the backside dielectric layer 148 can be removed using a silicon RIE process. The backside contact trenches 152 described herein are self-aligned to the STI regions in the x-direction.

Referring now to FIGS. 16 and 17, the structure 100 is shown after removing some of the placeholders 116 according to an embodiment of the invention. FIG. 16 depicts a cross-sectional view of the structure 100 shown in FIG. 17 taken along line X-X and FIG. 17 depicts a cross-sectional view of the structure 100 shown in FIG. 16 taken along line Y-Y.

The placeholders 116 exposed within the backside contact trenches 152 are selectively removed according to known techniques. Specifically, the exposed placeholders 116 are etched or removed selective to backside dielectric layer 148, the dielectric liner 144, the stack spacers 126, and the buffer layer 118, as illustrated in FIG. 16. The exposed placeholders 116 can be removed using a RIE process.

In doing so, portions of the backside contact trenches 152 directly beneath the source drain regions 120 (see FIG. 16) become deeper without exposing the source drain regions 120. Meanwhile, since the chosen etching technique used to remove the placeholders 116 is selective to the backside dielectric layer 148, portions of the backside contact trenches 152 directly beneath the gates 108 (see FIG. 15) remain substantially unchanged.

Finally, the backside contact mask 150 is removed according to known techniques.

Referring now to FIGS. 18 and 19, the structure 100 is shown after enlarging the backside contact trenches 152 according to an embodiment of the invention. FIG. 18 depicts a cross-sectional view of the structure 100 shown in FIG. 19 taken along line X-X and FIG. 19 depicts a cross-sectional view of the structure 100 shown in FIG. 18 taken along line Y-Y.

After removing the placeholders 116 the backside contact trenches 152 are enlarged according to known techniques. Specifically, after removing an additional etching tech is used to increase the size of the backside contact trenches 152 in the y-direction (see FIG. 18). In doing so, the portions of the backside dielectric layer 148 are removed selective to the STI regions and the dielectric liner 144, as illustrated. Meanwhile the top of the backside contact trenches 152 remains anchored by the dielectric liner 144. Said differently, the dielectric liner 144 prevents lateral dimensions, both in the x-direction and the y-direction, at the top of the backside contact trenches 152 from increasing. The backside contact trenches 152 can be enlarged using a RIE process.

Furthermore, the STI regions prevent lateral dimensions of the backside contact trenches 152 in the y-direction from increasing. (see FIG. 19). Lateral dimensions of the backside contact trenches 152 in the x-direction may increase along portions not protected by dielectric liner 144. (see FIG. 18). It is further noted that the source drain regions 120 remain protected by the buffer layers 118.

Finally, exposed buffer layers 118 are subsequently removed selective to the surrounding structures according to known techniques.

Referring now to FIGS. 20 and 21, the structure 100 is shown after forming backside contact structures 154 and backside wiring layers 156 according to an embodiment of the invention. FIG. 20 depicts a cross-sectional view of the structure 100 shown in FIG. 21 taken along line X-X and FIG. 21 depicts a cross-sectional view of the structure 100 shown in FIG. 20 taken along line Y-Y.

The backside contact trenches 152 are then filled with a conductive material to form the backside contact structures 154 according to known techniques. The backside contact structures 154 may include any suitable conductive material, such as, for example, copper, ruthenium, aluminum, tungsten, cobalt, or alloys thereof. In some embodiments, a metal silicide is formed at the bottom of the backside contact trenches 152 prior to filling them with the conductive material. After, excess conductive material can be polished using known techniques until bottommost surfaces of the backside contact structures 154 are flush, or substantially flush, with bottommost surfaces of the backside dielectric layer 148, as illustrated. It is noted, the backside contact structures 154 may include, for example, backside source drain contacts, as illustrated, as well as backside gate contacts (not shown).

After forming the backside contact structures 154, the backside wiring layers 156 are subsequently formed according to known techniques. The backside wiring layers 156 typically include at least backside power rails 158 and a backside power delivery network 160.

With continued reference to FIGS. 20 and 21, and according to an embodiment, the structure 100 includes a nanosheet transistor device including a backside source drain contact, where the backside source drain contact includes a top portion, a middle portion, and a bottom portion, and a dielectric liner disposed along sidewalls of the top portion of the backside source drain contact.

With continued reference to FIGS. 20 and 21, and according to an embodiment, the structure further includes a placeholder adjacent to the backside source drain contact and directly beneath a source drain region, where the dielectric liner is disposed along sidewalls a portion of the placeholder.

With continued reference to FIGS. 20 and 21, and according to an embodiment, the structure further includes a buffer layer between and physically separating the placeholder from a source drain region.

With continued reference to FIGS. 20 and 21, and according to an embodiment the dielectric liner further separated a backside dielectric layer from stack spacers arranged directly beneath a nanosheet stacks of the nanosheet transistor device.

With continued reference to FIGS. 20 and 21, and according to an embodiment the dielectric liner further separates a backside dielectric layer from a gate.

With continued reference to FIGS. 20 and 21, and according to an embodiment sidewalls of the dielectric liner directly contact sidewalls of shallow trench isolation regions.

With continued reference to FIGS. 20 and 21, and according to an embodiment the backside source drain contact is self-aligned to shallow trench isolation regions.

With continued reference to FIGS. 20 and 21, and according to an embodiment, the structure 100 includes a nanosheet transistor device includes a backside source drain contact, where the backside source drain contact includes a top portion having a first width, a middle portion having a second width, and a bottom portion having a third width, and a dielectric liner disposed along sidewalls of the first portion of the backside source drain contact.

With continued reference to FIGS. 20 and 21, and according to an embodiment, the structure 100 includes a nanosheet transistor device including a source drain region and a backside source drain contact, where the backside source drain contact includes a top portion having a first width, a middle portion having a second width, and a bottom portion having a third width, where the first width of the top portion is substantially equal to a width of the source drain region, a dielectric liner disposed along sidewalls of the first portion of the backside source drain contact.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

BACKSIDE DIELECTRIC LINERS

Information

Publication Number

Date Filed

Date Published

Inventors

Original Assignees

CPC

International Classifications

Abstract

Description

Claims