This relates generally to image sensors, and more particularly, to global shutter image sensors.
Image sensors are commonly used in electronic devices such as cellular telephones, cameras, and computers to capture images. In a typical arrangement, an image sensor includes an array of image pixels arranged in pixel rows and pixel columns.
Typical image pixels contain a photodiode for generating charge in response to incident light. Image pixels may also include a charge storage region such as a storage capacitor for storing charge that is generated in the photodiode. Image sensors can operate using a global shutter or a rolling shutter scheme. In a global shutter, every pixel in the image sensor may simultaneously capture an image, whereas in a rolling shutter each row of pixels may sequentially capture an image. Global shutter image sensors may require a charge storage region to store charge that is subsequently read out in a row-by-row manner.
In backside illuminated (BSI) image sensors, it may be difficult to shield a charge storage region for implementing global shutter functionality from incident light. The charge storage region may also be susceptible to high levels of dark current.
It would therefore be desirable to be able to provide improved backside illuminated global shutter image sensors.
Embodiments of the present invention relate to image sensors. It will be recognized by one skilled in the art that the present exemplary embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to unnecessarily obscure the present embodiments.
Electronic devices such as digital cameras, computers, cellular telephones, and other electronic devices may include image sensors that gather incoming light to capture an image. The image sensors may include arrays of pixels. The pixels in the image sensors may include photosensitive elements such as photodiodes that convert the incoming light into image signals. Image sensors may have any number of pixels (e.g., hundreds or thousands or more). A typical image sensor may, for example, have hundreds of thousands or millions of pixels (e.g., megapixels). Image sensors may include control circuitry such as circuitry for operating the pixels and readout circuitry for reading out image signals corresponding to the electric charge generated by the photosensitive elements.
As shown in
Each image sensor in camera module 12 may be identical or there may be different types of image sensors in a given image sensor array integrated circuit. During image capture operations, each lens may focus light onto an associated image sensor 14. Image sensor 14 may include photosensitive elements (i.e., pixels) that convert the light into digital data. Image sensors may have any number of pixels (e.g., hundreds, thousands, millions, or more). A typical image sensor may, for example, have millions of pixels (e.g., megapixels). As examples, image sensor 14 may include bias circuitry (e.g., source follower load circuits), sample and hold circuitry, correlated double sampling (CDS) circuitry, amplifier circuitry, analog-to-digital converter circuitry, data output circuitry, memory (e.g., buffer circuitry), address circuitry, etc.
Still and video image data from camera sensor 14 may be provided to image processing and data formatting circuitry 16 via path 28. Image processing and data formatting circuitry 16 may be used to perform image processing functions such as data formatting, adjusting white balance and exposure, implementing video image stabilization, face detection, etc. Image processing and data formatting circuitry 16 may also be used to compress raw camera image files if desired (e.g., to Joint Photographic Experts Group or JPEG format). In a typical arrangement, which is sometimes referred to as a system on chip (SOC) arrangement, image sensor 14 and image processing and data formatting circuitry 16 are implemented on a common semiconductor substrate (e.g., a common silicon image sensor integrated circuit die). If desired, camera sensor 14 and image processing circuitry 16 may be formed on separate semiconductor substrates. For example, camera sensor 14 and image processing circuitry 16 may be formed on separate substrates that have been stacked.
Imaging system 10 (e.g., image processing and data formatting circuitry 16) may convey acquired image data to host subsystem 20 over path 18. Host subsystem 20 may include processing software for detecting objects in images, detecting motion of objects between image frames, determining distances to objects in images, filtering or otherwise processing images provided by imaging system 10.
If desired, system 100 may provide a user with numerous high-level functions. In a computer or advanced cellular telephone, for example, a user may be provided with the ability to run user applications. To implement these functions, host subsystem 20 of system 100 may have input-output devices 22 such as buttons, keypads, touch-sensitive areas, input-output ports, joysticks, and displays and storage and processing circuitry 24. Storage and processing circuitry 24 may include volatile and nonvolatile memory (e.g., random-access memory, flash memory, hard drives, solid-state drives, etc.). Storage and processing circuitry 24 may also include microprocessors, microcontrollers, digital signal processors, application specific integrated circuits, etc.
An example of an arrangement for camera module 12 of
Column control and readout circuitry 42 may include column circuitry such as column amplifiers for amplifying signals read out from array 32, sample and hold circuitry for sampling and storing signals read out from array 32, analog-to-digital converter circuits for converting read out analog signals to corresponding digital signals, and column memory for storing the read out signals and any other desired data. Column control and readout circuitry 42 may output digital pixel values to control and processing circuitry 44 over line 26.
Array 32 may have any number of rows and columns. In general, the size of array 32 and the number of rows and columns in array 32 will depend on the particular implementation of image sensor 14. While rows and columns are generally described herein as being horizontal and vertical, respectively, rows and columns may refer to any grid-like structure (e.g., features described herein as rows may be arranged vertically and features described herein as columns may be arranged horizontally).
Pixel array 32 may be provided with a color filter array having multiple color filter elements which allows a single image sensor to sample light of different colors. As an example, image sensor pixels such as the image pixels in array 32 may be provided with a color filter array which allows a single image sensor to sample red, green, and blue (RGB) light using corresponding red, green, and blue image sensor pixels arranged in a Bayer mosaic pattern. The Bayer mosaic pattern consists of a repeating unit cell of two-by-two image pixels, with two green image pixels diagonally opposite one another and adjacent to a red image pixel diagonally opposite to a blue image pixel. In another suitable example, the green pixels in a Bayer pattern are replaced by broadband image pixels having broadband color filter elements (e.g., clear color filter elements, yellow color filter elements, etc.). These examples are merely illustrative and, in general, color filter elements of any desired color and in any desired pattern may be formed over any desired number of image pixels 34.
If desired, array 32 may be part of a stacked-die arrangement in which pixels 34 of array 32 are split between two or more stacked substrates. In such an arrangement, each of the pixels 34 in the array 32 may be split between the two dies at any desired node within the pixel. As an example, a node such as the floating diffusion node may be formed across two dies. Pixel circuitry that includes the photodiode and the circuitry coupled between the photodiode and the desired node (such as the floating diffusion node, in the present example) may be formed on a first die, and the remaining pixel circuitry may be formed on a second die. The desired node may be formed on (i.e., as a part of) a coupling structure (such as a conductive pad, a micro-pad, a conductive interconnect structure, a conductive via, etc.) that connects the two dies. Before the two dies are bonded, the coupling structure may have a first portion on the first die and may have a second portion on the second die. The first die and the second die may be bonded to each other such that first portion of the coupling structure and the second portion of the coupling structure are bonded together and are electrically coupled. If desired, the first and second portions of the coupling structure may be compression bonded to each other. However, this is merely illustrative. If desired, the first and second portions of the coupling structures formed on the respective first and second dies may be bonded together using any metal-to-metal bonding technique, such as soldering or welding.
As mentioned above, the desired node in the pixel circuit that is split across the two dies may be a floating diffusion node. Alternatively, the desired node in the pixel circuit that is split across the two dies may be the node between a floating diffusion region and the gate of a source follower transistor (i.e., the floating diffusion node may be formed on the first die on which the photodiode is formed, while the coupling structure may connect the floating diffusion node to the source follower transistor on the second die), the node between a floating diffusion region and a source-drain node of a transfer transistor (i.e., the floating diffusion node may be formed on the second die on which the photodiode is not located), the node between a source-drain node of a source follower transistor and a row select transistor, or any other desired node of the pixel circuit.
In general, array 32, row control circuitry 40, column control and readout circuitry 42, and control and processing circuitry 44 may be split between two or more stacked substrates. In one example, array 32 may be formed in a first substrate and row control circuitry 40, column control and readout circuitry 42, and control and processing circuitry 44 may be formed in a second substrate. In another example, array 32 may be split between first and second substrates (using one of the pixel splitting schemes described above) and row control circuitry 40, column control and readout circuitry 42, and control and processing circuitry 44 may be formed in a third substrate.
An example of an image sensor split between two or more substrate layers is shown in
Middle chip 54 may be bonded to upper chip 52 with an interconnect layer at every pixel or an interconnect for a group of pixels (e.g., two pixels, three pixels, more than three pixels, etc.). Bonding each pixel in upper chip 52 to corresponding circuitry 64 in middle chip 54 may be referred to as hybrid bonding. Middle chip 54 and lower chip 56 may not be coupled with hybrid bonding. Only peripheral electrical contact pads 58 of each chip may be bonded together (e.g., chip-to-chip connections 60). Each chip in image sensor 14 may include relevant circuitry. The upper chip may contain pinned photodiodes, floating diffusion regions, reset transistors, and a first source follower transistor. The middle chip may include an additional source follower transistor, one or more charge storage regions, one or more capacitors, and additional transistors. The bottom chip may include one or more of clock generating circuits, pixel addressing circuits, signal processing circuits such as the CDS circuits, analog to digital converter circuits, digital image processing circuits, and system interface circuits.
The example of
Image sensor 14 may have global shutter capabilities and may be a backside illuminated (BSI) image sensor. During global shutter operations, every pixel in the image sensor may simultaneously capture an image, then the signals from the pixels are read out row-by-row. To enable global shutter capabilities, a storage node may be incorporated into the imaging pixel that allows storage of the signals. However, in backside illuminated image sensors (where the image sensor wiring is positioned below the semiconductor substrate with the photodiode), it may be difficult to prevent light leakage from compromising the charge stored in the pixel. To shield the charge storage region from light leakage, the charge storage region may be implemented as a storage capacitor in the second substrate (that is connected to the first substrate, that includes a photodiode, by a conductive interconnect layer). However, the storage capacitor may be coupled to a diffusion region in the second substrate and may therefore have a high dark current (particularly at high temperatures). The high dark current increases noise within the image sensor, reducing image sensor performance.
To provide global shutter functionality while reducing noise, a charge coupled device (CCD) may be used as a storage device for the image sensor pixels. The charge coupled device serves as analog memory storage for pixel reset (e.g., SHR) and sample (e.g., SHS) voltages.
Source follower transistor 114 has a gate terminal coupled to floating diffusion region FD and a first terminal of reset transistor 108. Source follower transistor 114 also has a first source-drain terminal coupled to voltage supply 110. In this application, each transistor is illustrated as having three terminals: a source, a drain, and a gate. The source and drain terminals of each transistor may be changed depending on how the transistors are biased and the type of transistor used. For the sake of simplicity, the source and drain terminals are referred to herein as source-drain terminals or simply terminals. A second source-drain terminal of source follower transistor 114 is coupled to sampling transistor 116 (sometimes referred to as row select transistor 116).
In the example of
A gate terminal of transfer transistor 104 receives control signal TX. A gate terminal of reset transistor 108 receives control signal RG. A gate terminal of row select transistor 116 receives control signal RS. A gate terminal of anti-blooming transistor 112 receives control signal AB. Control signals TX, RG, RS, and AB may be provided by row control circuitry (e.g., row control circuitry 40 in
As shown in
Conductive interconnect layer 118 may be coupled to an analog memory charge coupled device (CCD) 120 (sometimes referred to as CCD 120, memory CCD 120 etc.). CCD 120 may include a charge injector 122, an input gate 124, a first storage gate 126, a second storage gate 128, and an output gate 130. Charge injector 122 may be formed from an n-type diffusion region in substrate 54 that is coupled to a bias voltage (INJ). Input gate 124 may be coupled to conductive interconnect layer 118 and may receive an input voltage (VIN) that is proportional to the voltage on floating diffusion region 106 in substrate 52 (when row select transistor 116 is asserted). Storage gates 126 and 128 may be used to shift charge within the CCD. Output gate 130 may be used to selectively transfer charge from the CCD to floating diffusion region 132 in substrate 54. The CCD gates may include doped portions (e.g., boron-doped portions) underneath the gates that set the potential profiles of the gates.
A reset transistor 134 may be coupled between floating diffusion region 132 (FD) and voltage supply 136. Voltage supply 134 may provide a voltage VDD (that may the same or different from the voltage provided by supply 110). Floating diffusion region 132 may be a doped semiconductor region (e.g., a region in a silicon substrate that is doped by ion implantation, impurity diffusion, or other doping process). Source follower transistor 138 has a gate terminal coupled to floating diffusion region 132 and a first terminal of reset transistor 134. Source follower transistor 138 also has a first source-drain terminal coupled to voltage supply 136. A second source-drain terminal of source follower transistor 138 is coupled to sampling transistor 140 (sometimes referred to as row select transistor 140). Transistor 142 (which is used to provide a bias current) is also coupled to the conductive interconnect layer 118.
A gate terminal of reset transistor 134 receives control signal RG2. A gate terminal of row select transistor 140 receives control signal RS′. Storage gate 126 receives control signal SG1. Storage gate 128 receives control signal SG2. Output gate 130 receives control signal OG. Control signals RG2, SG1, SG2, OG, and RS′ may be provided by row control circuitry (e.g., row control circuitry 40 in
Transistor 142, CCD 120 (including charge injector 122, input gate 124, storage gates 126 and 128, and output gate 130), floating diffusion region 132, reset transistor 134, power supply terminal 136, source follower transistor 138, and row select transistor 140 may all be formed in substrate 54 as shown in
During operation of pixel 34, charge may accumulate in photodiode 102 in response to incident light. The amount of charge accumulated in the photodiode may be proportional to the intensity of the incident light received and the exposure time of the imaging pixel. Before the conclusion of the integration time of the pixel, the floating diffusion region 106 may be reset to a reset voltage by asserting reset transistor 108. Then, charge from the photodiode may be transferred to floating diffusion region 106 by asserting transfer transistor 104.
The pixel of
The reset and signal values may be stored in CCD 120 (as will be discussed in greater detail in connection with
As shown in
At time 2 in
At time 4, SG1 is lowered and SG2 is raised. As shown by potential diagram 4 in
At time 5, SG1 is returned to a high level and SG2 is returned to a low level. Then, charge is transferred from photodiode 102 to floating diffusion region 106 by raising control signal TX (e.g., at assertion 152) and asserting transfer transistor 104. This causes a corresponding drop in the voltage at floating diffusion region 106. Accordingly, voltage VIN drops to a different level.
At time 6, the bias voltage (INJ) provided to charge injector 122 is lowered. This fills the region under gate 126 with charge, as shown by potential diagram 6 in
At time 8, RS, SG1, TX, and SG2 may all be low. As shown by potential diagram 8 in
The n-type diffusion regions that are used to form charge injector 122 and floating diffusion region 132 may be susceptible to dark current. However, as shown by potential diagram 8 in
The sampling sequence of
Because the SHR and SHS samples are transferred to and ultimately read from floating diffusion 132, an additional reset sample is obtained as shown in potential diagram 8 in
To read out the samples, the control signal OG is raised high, as shown in potential diagram 9. This causes the SHR sample to be transferred to the floating diffusion region. Then, as shown by potential diagram 10, the control signal OG may be returned to a lower level. Next, the SHS sample may be transferred from storage gate 126 to storage gate 128 (e.g., by toggling SG1 and SG2 as shown in potential diagrams 11 and 12).
After the SHR sample is transferred to floating diffusion region 132, the voltage of the floating diffusion region 132 is equal to a sum of the reset voltage of the floating diffusion 132 (SHR0) and the SHR sample transferred to the floating diffusion region. This combination (which may be referred to as SHR1) may be sampled (e.g., by determining VOUT). SHR0 may then be subtracted from SHR1 to determine SHR.
To read out the SHS sample, the control signal OG is raised high, as shown in potential diagram 13. This causes the SHS sample to be transferred to the floating diffusion region. Then, as shown by potential diagram 14, the control signal OG may be returned to a lower level. After the SHS sample is transferred to floating diffusion region 132, the voltage of the floating diffusion region 132 is equal to the sum of the reset voltage of the floating diffusion 132 (SHR0) and the SHR and SHS samples transferred to the floating diffusion region. This combination (which may be referred to as SHS1) may be sampled (e.g., by determining VOUT). SHR1 may then be subtracted from SHS1 to determine SHS. Finally, SHR may be subtracted from SHS to determine how much charge was originally transferred out of the photodiode.
It should be noted that the amount of charge stored in the CCD (e.g., SHS and SHR at potential diagram 8 in
In the example of
Sampling more than two signals from the pixel circuitry may be particularly useful depending upon the specific pixel circuitry design. An example of pixel circuitry is depicted in
Regardless of the specific arrangement of pixel circuitry 202, it may be desirable to sample and store more than two signals from pixel circuitry 202. CCD 120 in
CCD 120 may include any desired number of gates (e.g., one, two, three, four, more than four, more than six, more than eight, more than ten, less than ten, between 1 and 5, etc.).
Storage gates may be selectively combined during operation of the image sensor if desired. For example, the CCD of
In
A single storage and readout circuit 204 is coupled to the conductive interconnect layer 118 for storing and reading charge from pixel circuits 202-1 and 202-2. The storage and readout circuit 204 has the same arrangement as in
The example of sharing a CCD between pixels in
Additionally or instead of sharing pixel circuits between a single CCD, CCDs may share a single source follower transistor. For example, multiple analog memory CCDs (e.g., two, three, four, more than four, more than eight, more than sixteen, etc.) may have output gates coupled to a common floating diffusion region and source follower transistor.
Another possible sharing arrangement for the image sensor is shown in
Charge from multiple pixel circuits may therefore be stored simultaneously in a single CCD. The CCD may have a plurality of injection points, each associated with a respective pixel circuit, distributed along the CCD. This is in contrast to
The CCD is coupled to a single output gate 130 and floating diffusion region 132. Therefore, only a single source follower transistor 138, single select transistor 140, and single reset transistor 134 are required. The storage gates may be clocked to sequentially transfer each stored charge to floating diffusion region 132 for readout.
As previously mentioned, storage gates 126 and 128 of CCD 120 may be held at a negative voltage while storing charge to prevent dark current. This may be referred to as holding the storage gates in accumulation. In
Therefore, to mitigate any noise from dark current from input gate 124, an additional gate may be interposed between input gate 124 and storage gate 126.
It should be reiterated that the arrangement of the pixel circuitry shown herein (e.g., in
It should be noted that, if desired, the dopant types described herein may be reversed. For example, n-type dopants may be switched with p-type dopants and p-type dopants may be switched with n-type dopants. In general, the pixels may accumulate electrons or holes as desired.
The foregoing is merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art. The foregoing embodiments may be implemented individually or in any combination.