Patent Application
20250176284
This relates generally to imaging devices and more particularly, to image sensors with charge transfer gates.
Image sensors are commonly used in electronic devices such as cellular telephones, cameras, and computers to capture images. In a typical arrangement, an image sensor is provided with an array of image pixels arranged in pixel rows and pixel columns. The image sensor can sometimes include global shutter pixels. It can be challenging to design global shutter pixels. If care is not taken, the global shutter pixels may suffer from poor global shutter efficiency, lower charge capacity due to the requirement of an extra storage gate node, and higher pixel noise.
It is within this context that the embodiments described herein arise.
Embodiments of the present invention relate to image sensors. It will be recognized by one skilled in the art that the present exemplary embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to unnecessarily obscure the present embodiments.
Electronic devices such as digital cameras, computers, cellular telephones, and other electronic devices may include image sensors that gather incoming light to capture an image. The image sensors may include arrays of pixels. The pixels in the image sensors may include photosensitive elements such as photodiodes that convert the incoming light into image signals. Image sensors may have any number of pixels (e.g., hundreds or thousands or more). A typical image sensor may, for example, have hundreds or thousands or millions of pixels (e.g., megapixels). Image sensors may include control circuitry such as circuitry for operating the pixels and readout circuitry for reading out image signals corresponding to the electric charge generated by the photosensitive elements.
As shown in
Each image sensor in camera module 12 may be identical or there may be different types of image sensors in a given image sensor array integrated circuit. During image capture operations, each lens may focus light onto an associated image sensor 14. Image sensor 14 may include photosensitive elements (i.e., image sensor pixels) that convert the light into digital data. Image sensors may have any number of pixels (e.g., hundreds, thousands, millions, or more). A typical image sensor may, for example, have millions of pixels (e.g., megapixels). As examples, image sensor 14 may further include bias circuitry (e.g., source follower load circuits), sample and hold circuitry, correlated double sampling (CDS) circuitry, amplifier circuitry, analog-to-digital converter circuitry, data output circuitry, memory (e.g., buffer circuitry), address circuitry, etc.
Still and video image data from camera sensor 14 may be provided to image processing and data formatting circuitry 16 via path 28. Image processing and data formatting circuitry 16 may be used to perform image processing functions such as data formatting, adjusting white balance and exposure, implementing video image stabilization, face detection, etc. Image processing and data formatting circuitry 16 may also be used to compress raw camera image files if desired (e.g., to Joint Photographic Experts Group or JPEG format). In a typical arrangement, which is sometimes referred to as a system on chip (SoC) arrangement, camera sensor 14 and image processing and data formatting circuitry 16 are implemented on a common semiconductor substrate (e.g., a common silicon image sensor integrated circuit die). If desired, camera sensor 14 and image processing circuitry 16 may be formed on separate semiconductor substrates. For example, camera sensor 14 and image processing circuitry 16 may be formed on separate substrates that have been stacked.
Imaging system 10 (e.g., image processing and data formatting circuitry 16) may convey acquired image data to host subsystem 20 over path 18. Host subsystem 20 may include processing software for detecting objects in images, detecting motion of objects between image frames, determining distances to objects in images, filtering or otherwise processing images provided by imaging system 10.
If desired, system 100 may provide a user with numerous high-level functions. In a computer or advanced cellular telephone, for example, a user may be provided with the ability to run user applications. To implement these functions, host subsystem 20 of system 100 may have input-output devices 22 such as keypads, input-output ports, joysticks, and displays and storage and processing circuitry 24. Storage and processing circuitry 24 may include volatile and nonvolatile memory (e.g., random-access memory, flash memory, hard drives, solid-state drives, etc.). Storage and processing circuitry 24 may also include microprocessors, microcontrollers, digital signal processors, application specific integrated circuits, etc.
An example of an arrangement of image sensor 14 of
Row control circuitry 40 may receive row addresses from control and processing circuitry 44 and may supply corresponding row control signals to image pixels 34 over control paths 36 (e.g., pixel reset control signals, charge transfer control signals, blooming control signals, row select control signals, dual conversion gain control signals, or any other desired pixel control signals).
Column control and readout circuitry 42 may be coupled to the columns of pixel array 32 via one or more conductive lines such as column lines 38. Column lines 38 may be coupled to each column of image pixels 34 in image pixel array 32 (e.g., each column of pixels may be coupled to a corresponding column line 38). Column lines 38 may be used for reading out image signals from image pixels 34 and for supplying bias signals (e.g., bias currents or bias voltages) to image pixels 34. During image pixel readout operations, a pixel row in image pixel array 32 may be selected using row driver circuitry 40 and image data associated with image pixels 34 of that pixel row may be read out by column readout circuitry 42 on column lines 38. Column readout circuitry 42 may include column circuitry such as column amplifiers for amplifying signals read out from array 32, sample and hold circuitry for sampling and storing signals read out from array 32, analog-to-digital converter circuits for converting read out analog signals to corresponding digital signals, and column memory for storing the read out signals and any other desired data. Column control and readout circuitry 42 may output digital pixel readout values to control and processing logic 44 over line 26.
Array 32 may have any number of rows and columns. In general, the size of array 32 and the number of rows and columns in array 32 will depend on the particular implementation of image sensor 14. While rows and columns are generally described herein as being horizontal and vertical, respectively, rows and columns may refer to any grid-like structure (e.g., features described herein as rows may be arranged vertically and features described herein as columns may be arranged horizontally).
In general, backside illuminated (BSI) pixel architectures exhibit improved performance relative to front side illuminated (FSI) pixel architectures. However, BSI pixels that uses the global shutter (GS) readout method that relies on charge domain storage nodes often suffer from low global shutter efficiency due to difficulties in shielding in-pixel charge storage nodes from stray light.
Photodiode PD may be coupled to a storage gate that is controlled by control signal SG. The storage gate may serve as a temporary memory node for pixel 34 and is therefore sometimes referred to as a storage node, storage gate node, storage gate memory node, or global shutter storage node. Storage gate may be coupled to a floating diffusion node FD via a charge transfer transistor controlled by signal TX. The charge transfer transistor is sometimes referred to as a charge transfer gate.
Any charge transferred to floating diffusion node FD causes the potential on this node to change, and this change is sensed by a source follower transistor SF. The source terminal of the source follower transistor is connected via a row select transistor to the sensor array column sensing line 38 that delivers the pixel signal to the periphery of the array for further processing. Row select control signal RS is asserted to activate the row select transistor to transfer the pixel signal to column sensing line 38. After charge sensing has been completed, floating diffusion node FD may be reset to supply voltage Vaa (e.g., a nominal positive power supply voltage provided on the power supply line) by asserting reset control signal RST to turn on the reset transistor. If desired, the storage gate can be reset at the same time as the floating diffusion node by simultaneously asserting signals RST and TX.
The global shutter image sensor pixel 34 shown in
Each pixel 34 may also include a storage gate structure 114 formed at the front surface of substrate 100. Storage gate structure 114 may represent the storage gate controlled by signal SG in
Implementing the storage gate as a trench transistor dramatically reduces the footprint of the storage gate, which allows for a large PD region and can help improve global shutter efficiency. A trench storage gate can have increased charge capacity because the area of the storage gate is not limited by the pixel size; simply increasing the depth of the trench storage gate increase the charge storage capacity. If desired, the charge transfer transistor that is controlled by signal TX (see
The storage gate conductor 114 may be coupled to one or more metal layers in dielectric stack 102 using vertical vias 134. Dielectric stack 102 may include alternating metal routing layers 130 and dielectric layers 132 through which conductive vias can be formed. Dielectric stack 102 is sometimes referred to as an interconnect stack. Dielectric stack 102 may include at least two metal routing layers, at least three metal routing layers, four or more metal routing layers, five or more metal routing layers, six or more metal routing layers, or other number of conductive routing layers.
Deep trench isolation (DTI) structures such as DTI structures 140 may be formed in and at the back side of substrate 100. Deep trench isolation structures 140 may have a trench depth that is greater than that compared to shallow trench isolation structures 110. For example, DTI structures 140 may be at least 2×, 4×, 6×, 8×, 2-10×, or more than 10× deeper than the STI structures 110. Each pixel 34 may include a photodiode region PD that is at least partially surrounded by DTI structures 140. Each PD region may have a portion 144 that extends laterally beneath the channel region 116 of the associated storage gate structure 114. The region between buried channel 116 and PD portion 114 is a transfer region through which charge can be transferred from the photodiode to the global shutter storage node. A p-type (p-doped) well such as p-well 112 may be formed in substrate 100 for providing charge isolation between the photodiode region below well 112 and the planar transistor structures above well 112.
In particular, storage gates 114 may be laterally aligned with the DTI structures 140 (i.e., each storage gate 114 may be hidden under a corresponding backside deep trench isolation structure). In other words, the DTI structures 140 overlap with the storage gate structures 114 when viewing image sensor 14 from above (see plan view of
Backside dielectric stack 104 may include at least one metal routing layer sandwiched between two dielectric layers. In other suitable arrangements, dielectric stack 104 may include at least two metal routing layers, at least three metal routing layers, four or more metal routing layers, five or more metal routing layers, six or more metal routing layers, or other number of conductive routing layers.
An array of color filter structures may be formed on dielectric stack 104. In the example of
An array of microlens structures 150 may be formed over the color filter array. Each microlens 150 may be configured to direct incoming light 152 away from the storage gate regions. As an example, some of the microlens 150 can be configured to focus red light away from the storage gate nodes. As another example, some of the microlens 150 may be configured to focus blue light away from the storage gate nodes. As yet another example, some of the microlens 150 may be configured to focus green light away from the storage gate nodes. Image sensor 14 implemented as such is referred to as a backside illuminated image sensor because light 152 is entering the image sensor from the back (bottom) surface of substrate 100.
At step 202, a shallow p-well 112 is implanted from the front surface of substrate 100.
At step 204, shallow trench isolation structures 110 can be formed at the front surface of substrate 100. The STI structures 110 may form an active area for the planar pixel transistors.
At step 206, trenches are etched for the storage gates (and/or optionally for the charge transfer gates). At step 208, a potential well 116 is implanted from the front surface of substrate 100 into the region of substrate 100 between the trenches. At step 210, threshold adjust dopants (e.g., p-type dopants) can be implanted for the storage gate. At step 212, the trench gate oxide liner 118 can be grown and conductive gate material such as polysilicon can be deposited into the trenches to form trench gate conductor 118.
At step 214, the planar transistors (e.g., row select transistor, source follower transistor, charge transfer transistor, reset transistor, and/or other pixel switching transistors) can be formed in the active area surrounded by the STI structures 110.
At step 216, dielectric stack 102 and associated interconnect wiring can be formed on the front side of substrate 100. At step 218, the image sensor can be flipped (capsized), bonded to a carrier wafer, and thinned to the desired thickness. A relatively thicker substrate 100 generally improves global shutter efficiency. For example, the thickness of substrate 100 can be greater than 5 microns, greater than 10 microns, greater than 1 micron, 1-10 microns, 5-10 microns, 10-20 microns, or other suitable thickness.
At step 220, a layer of anti-reflective coating can be formed on the back surface of substrate 100. The deep trench isolation structures can be formed in the back surface. The deep trench isolation structures can optionally be filled with metal or other light-blocking material.
At step 222, a color filter array can be formed on the back surface of substrate 100, and a microlens array can be formed over the color filter array.
These steps are merely illustrative. At least some of the described steps may be modified or omitted; some of the described steps may be performed in parallel; additional steps may be added or inserted between the described steps; the order of certain steps may be reversed or altered; or the timing of the described steps may be adjusted so that they occur at slightly different times.
Various embodiments are disclosed. In accordance with some embodiments, an image sensor is provided that includes a substrate having a front surface and a back surface, a photodiode formed in the substrate, a charge transfer transistor coupled to the photodiode and formed in the front surface of the substrate, a storage gate coupled between the photodiode and the charge transfer transistor, where the storage gate comprises a trench transistor formed in the front surface of the substrate, and a deep trench isolation structure formed in the back surface of the substrate, where the deep trench isolation structure is laterally aligned with the storage gate. The deep trench isolation structure can be filled with light-shielding material such as metal. The storage gate can include a gate conductor formed in a trench, a buried channel region at least partially surrounded by the trench, and a gate insulating layer between the gate conductor and the buried channel region. The storage gate can have a first footprint, whereas the deep trench isolation structure can have a second footprint that is identical or larger than the first footprint.
In accordance with some embodiments, a method of manufacturing an image sensor is provided that includes: obtaining a substrate having a front surface and a back surface, etching a trench in the front surface of the substrate, implanting a potential well in a region of the substrate at least partially surrounded by the trench, growing a gate oxide layer in the trench, depositing conductive gate material into the trench, and forming a deep trench isolation structure in the back surface of the substrate, where the deep trench isolation structure is aligned with the trench. The deep trench isolation structure can be filled with light-blocking material. The method can further include: forming planar transistors at the front surface of the substrate, forming a photodiode region in the substrate, and forming an isolation well between the photodiode region and the planar transistors.
In accordance with some embodiments, an image sensor pixel is provided that includes: a substrate having an upper surface and a lower surface, a trench transistor formed in the upper surface, and a deep trench isolation structure formed in the lower surface, where the deep trench isolation structure at least partially covers the trench transistor from the lower surface. The trench transistor can serve as a global shutter storage gate or can serve as a charge transfer transistor. The pixel can further include a photodiode region laterally surrounded by the deep trench isolation structure, where the photodiode region has a portion that extends into a region of the substrate between the trench transistor and the deep trench isolation structure.
The foregoing is merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. The foregoing embodiments may be implemented individually or in any combination.
