The present invention relates to a method for communicating data over a mixing segment of an Ethernet network, and more particularly, to a method for communicating data over a 10BASE-T1S Ethernet network segment using nodes communicatively connected to the mixing segment.
IEEE Std 802.3cg-2019 established a new pair of Ethernet physical layer devices (PHYs), one of which, the short-reach 10BASE-T1S, uses 4B/5B mapping over Differential Manchester Encoding (DME) to maintain a data rate of 10 Mb/s at a MAC/PLS interface, while providing in-band signaling between transmitter and receiver(s). However, 10BASE-T1S does not have any error correcting scheme built into it.
As a response to emerging building, industrial, and transportation requirements, an object of the present invention is to create a low-complexity, backward compatible Forward Error Correction (FEC) with per-frame configurable guaranteed burst error and erasure correcting capabilities over any 10BASE-T1S Ethernet network segment. Another object of the present invention is to combine a specialized, systematic Reed-Solomon code and a novel three-tier technique to avoid the appearance of certain inadmissible codeword symbols at the output of the encoder, thus enabling error and erasure correction while maintaining backward compatibility with the current version of the standard.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a first aspect of the invention is a method for communicating data over a mixing segment of an Ethernet network, in particular over a 10BASE-T1S Ethernet network segment, by means of node A and node B communicatively connected to the mixing segment. The method comprises: generating, by node A, an Ethernet frame E addressed to a node B, applying, by node A, a Reed-Solomon-type encoding to the Ethernet frame E to generate an encoded Ethernet frame E′, and transmitting, by node A, the encoded Ethernet frame E′ over the mixing segment.
According to an embodiment of the first aspect, receiving, by node B, from the mixing segment the Ethernet frame E′, and applying, by node B, a Reed-Solomon-type decoding to the Ethernet frame E′ to obtain a forward error correction representative of the original Ethernet frame E.
According to an embodiment of the first aspect, applying a Reed-Solomon-type encoding comprises: generating a list of forbidden symbols FS, and when applying Reed-Solomon parity symbols to the Ethernet frame E, removing or blocking the forbidden symbols FS from the encoded Ethernet frame E′. Forbidden symbols FS may comprise the symbols listed in table 2 below.
A second aspect of the invention is an Ethernet bus node, comprising a transceiver circuit, which comprises a media access control MAC and a PHY. The Ethernet node is configured to run the method according to the first aspect.
According to an embodiment, the Ethernet bus node is configured to communicate over a mixing segment, in particular over a 10BASE-T1S Ethernet network segment.
According to an embodiment, the mixing segment comprises a twisted-pair cable, and the transceiver circuit of the Ethernet bus node is configured to be connected to the twisted-pair cable.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee. In the drawings:
In the following detailed description, reference is made to the accompanying drawing figures which form a part hereof, and which show by way of illustration specific embodiments of the invention. It is to be understood by those of ordinary skill in this technological field that other embodiments may be utilized, and structural, electrical, as well as procedural changes may be made without departing from the scope of the present invention. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or similar parts.
For purposes of this written description, the term “PHY” will be used to refer to an Ethernet physical layer device, while the term “MAC” (an acronym for medium access control) will be used to refer to a link layer device to be connected by the PHY to a physical medium (e.g., optical fiber or copper cable).
The Institute of Electrical and Electronics Engineers (IEEE) project 802.3cg (P802.3cg) concluded in 2019 after about 3 years of research and standardization work involving several key individuals working in the automotive, industrial, building automation, process control, in-system networking technology. The project defined two 10 Mb/s baseband Ethernet Physical Layer (PHY) devices, each for use over a single balanced pair of conductors. One PHY, 10BASE-T1L, was for reaching up to 1 km, and the other PHY, 10BASE-T1S, was specified for short reach applications such as automotive or in-system networks. 10BASE-T1S included a mode for shared-media, a.k.a. multidrop, operation. This project marked a return for Ethernet standards not only to 10 Mb/s speeds, but also to shared media communications, allowing more than two nodes to be attached to a single piece of wire. The shared media mode has garnered interest for extending the capabilities of 10BASE-T1S.
Details about IEEE P802.3cg can be found in the following documents, both of which are incorporated herein by reference in their entireties:
IEEE Std 802.3 (i.e., IEEE Standard for Ethernet, IEEE Std. 802.3-2018) uses certain nomenclature which we will use here as well. The standard refers to the “portion of the Physical Layer that contains the functions for transmission, reception, and—depending on the PHY—collision detection, clock recovery, and skew alignment” as the Physical Medium Attachment (PMA). Above the PMA, further from the medium, resides the Physical Coding Sublayer (PCS), which “contains the functions to encode data bits for transmission via the PMA and to decode the received conditioned signal from the PMA.” An explanation will be provided later of constraints and design on a Forward Error Correction (FEC) approach, which would reside in the PCS, as shown in
The 10BASE-T1L PHY is a long-reach, strictly point-to-point PHY supporting full-duplex low-power operation. 10BASE-T1L is specified by Clause 146.
The 10BASE-T1S PHY is a 10 Mb/s, short-reach, ultra-low complexity PHY, with an optional multidrop mode of operation. Additionally, a multidrop 10BASE-T1S PHY can provide packet fairness (see Sujan Pandey, Philip Axer, Don Pannell, “PLCA data-rate fairness,” March 2018, which is incorporated herein by reference in its entirety), bounded and calculable channel access delay, and effective throughput of near 10 Mb/s even at network saturation using the Physical Layer Collision Avoidance (PLCA) protocol specified in Clause 148 of IEEE Std 802.3cg-2019 and a Physical Layer Collision Avoidance (PLCA) technique, capable offering bounded channel-access time and a total effective throughput of near 10 Mb/s even at network saturation (see Piergiorgio Beruto, Antonio Orzelli, “Proposal for short-reach multidrop 10M SPE (formerly PLCA),” Sep. 14 2017, the entire contents of which are incorporated herein by reference; and Piergiorgio Beruto, Antonio Orzelli, “802.3cg draft 2.0 PLCA (Clause 148) Overview,” Jul. 9, 2018, the entire contents of which being incorporated herein by reference).
Traditionally, point-to-point Ethernet links, such as 10/100/1000BASE-T, have dealt with feature enhancements by using an Autonegotiation (AN) protocol to signal the capabilities of the PHY at the other end of the link and agree on the highest level of functionality common to the two PHYs. On a point-to-point Ethernet link AN affects only two PHYs making negotiation and single-ended upgrades simple. However, when the PHYs are on a shared media mixing segment, an extension of the AN approach would limit all PHYs on the mixing segment to the capabilities of the least capable node on the mixing segment, making upgrades more difficult. Because impulse noise might be location-dependent in an operational environment, it is possible that only a subset of network nodes might be impacted by noise, creating a situation where some nodes might gain more benefit from upgrading to FEC transmission and reception than others.
An alternative to requiring upgrade of all the nodes on a shared segment would be to provide a method of coexistence so that messages intended for a node capable of decoding the new FEC could be transmitted without spreading errors throughout the network from PHYs incapable of decoding the FEC. While there are many well-known error-correcting codes which might be used (see, e.g., W. Carry Huffman, Fundamentals of Error-Correcting Codes, Cambridge University Press, February 2010), the unique primary challenge in this case is backwards compatibility. Backwards compatibility requires that the encoding is formulated so that any new (FEC-enabled) nodes are able to coexist on the same shared medium as the nodes previously specified in IEEE 802.3cg without knowledge of the FEC. In short, any FEC must fit within the existing line coding scheme and not cause existing 802.3cg nodes to forward erroneous frames to their MACs. Achieving these goals while keeping PHY complexity (measured in gate count) and encoding/decoding latency low are the primary objectives of this paper.
To remain compatible with the present 802.3cg 10BASE-T1S PHY with PLCA (sometimes referred to hereinafter as a “PPHY”), while also implementing an FEC with known burst and erasure correcting capabilities, a new type of PHY (sometimes referred to hereinafter as a “NPHY”) must meet a specific set of conditions described in detail later in our paper. These conditions can be met by the careful selection and combined application of a set of techniques. These techniques take advantage of the inherent and unused redundancy present in the PPHY's 4B/5B mapping while systematically avoiding certain inadmissible 5B symbols, subsequently referred to as Forbidden Symbols (FS), in order to control how the new frames are interpreted by the receiver in a PPHY. As to forbidden symbols (FS), a discussion can be found in Declercq, M. Fossorier, E. Biglieri, Channel Coding—Theory, Algorithms, and Applications, Academic Press Library in Mobile and Wireless Communications, 2014, which is incorporated herein by reference in its entirety.
It should be noted that, while the solution being presented herein is described in regard to the specific coding in 10BASE-T1S, the method described in this specification may be used to enhance any similar system where code groups are used to encode control information along with transmitted data in a network, allowing both enhanced and legacy nodes to be supported.
Section 2 of this specification introduces the inner workings of the 10BASET1S PHY, including the necessary conditions to remain backward-compatible with it, and what constitutes an FS at different parts of the FEC codeword. Section 3 explains how the unused redundancy present in PPHY's 4B/5B mapping may be used in exemplary embodiments to implement a backward-compatible FEC for burst errors and erasures, including restrictions on the rate, field size and code parameters, and it shows that candidate codes exist. This is followed by Section 4, which describes novel techniques and their unique combination, according to exemplary embodiments of the invention, as well as various constraints related to avoiding the appearance of FS in the codeword. Section 5 describes techniques to implement error-resilient framing to achieve arbitrary burst error correcting capabilities, according to exemplary embodiments. Section 6 analyzes the error burst error correcting capabilities and the encoding delay of exemplary embodiments, and the method through which its correctness was verified. The last section offers conclusions (Section 7).
Additionally, several of the results mentioned in Section 4 are explained through the {19, 19} coding scheme and an example based on that. For reasons discussed below, the {19, 19} coding scheme may be the simplest coding scheme to exist.
The following table defines certain terms that will be referred to in the following sections:
For purposes of this specification, and following industrial and automotive requirements, it is assumed that exemplary embodiments of the present invention are used in connection with a binary burst error channel with optional erasure detection, where the erasure detection may rely on side-channel information coming from a receiver that is capable of signaling erasure.
The burst error environment assumed here is rooted in IEC 61000-4-4 Electrical Fast Transient (EFT) test common in industrial systems (as described in IEC 61000-4-4:2012, Electromagnetic compatibility (EMC)—Part 4-4: Testing and measurement techniques—Electrical fast transient/burst immunity test, which is incorporated herein by reference in its entirety). This test exposes the communications link to a sequence of 50 ns disturbance pulses in the test setup shown by
It is believed that these values represent a test setup that is specific to industrial environment, and thus exemplary embodiments of the present invention are aimed at leaving burst error correcting capabilities as a free variable, possibly configured for each frame separately as required by the specific system and the actual, assumed, or predicted status of the segment.
An Ethernet frame is encapsulated into a 10BASE-T1S frame, which starts off with a fixed sequence of 5B symbols with carefully crafted auto- and cross-correlation properties (see Gergely Huszak, Hiroyoshi Morita, “On the 10BASE-T1S preamble for multidrop,” presented at the GIIS 2019, Paris, France, Dec. 18-20, 2019, which is incorporated herein by reference in its entirety), followed by five 5B symbols (25 bits) encoding a per-frame lock sequence for the 17-bit scrambler of the PPHY. The lock sequence is followed by the actual data received from the MAC/PLS, and the frame is terminated by the appropriate End Sequence Delimiters (ESD), indicating success or failure of the frame transmission attempt.
The PPHY incorporates a multiplicative scrambler (see Byeong G. Lee, Seok C. Kim, Scrambling Techniques for Digital Transmission (Telecommunication Networks and Computer Systems), Springer, May 16, 2000, which is incorporated herein by reference in its entirety), to eliminate unacceptable electromagnetic emissions (see Subclause “147.5.4.4.2 PSD mask” in IEEE Std 802.3cg-2019) from so-called “killer packets” containing periodic data patterns. The multiplicative scrambler operates only on payload data and not on 4B/5B encoded control symbols. Because multiplicative scramblers propagate errors in the received data sequence, it is desirable to place the FEC to operate on the scrambled data sequence to minimize errors into the descrambler at the receiver as shown in
Clause 147 defines a specific 4B/5B mapping as follows:
At the MII, 4-bit nibbles are clocked at a rate of 2.5 Mb/s, while the PMA is handling DME bits at 12.5 Mb/s, the details of which are shown by
In order for 10BASE-T1S NPHYs and PPHYs to be backwards compatible and coexist on the same network segment, the following requirements must be met:
Achieving the 1st criterion constrains the NPHY to DME transmission of 5B symbols at a 12.5 Mb/s line rate. This, together with the 4th criterion of a 10 Mb/s rate at the MAC/PLS interface, implies that whatever encoding is used must have a rate of no less than 4/5=0.8.
Detailed analysis and simulation (shown in Section 6.2.1 below) of the PPHY's PCS_RX state diagram, the essence of which is depicted in
It is worth noting that another cyclic sequence of states exists in the PCS_RX that may also allow locking the receiver. This sequence, the WAIT_SYNC→(SYNCING→(COMMIT→(WAIT_SSD→)))WAIT_SYNC→ . . . , is highlighted by the blue dotted area in
As explained in Section 2.1 a PPHY frame is terminated by ESD. In a noisy environment special care must be taken to maintain error resilience not only for the payload, but also for this component of the packet. To be able to signal end of frame—and possibly additional side-information—with error resilience that is at least as good as that of the payload, an additional (4th) 5B symbol is reserved from the set of those 5B symbols without a defined mapping in the PPHY. In this paper we will refer to this FECESD FS as ‘X’, forming the 4th element of the FS set we build on. For the reasons explained in Section 5.1, ‘X’ should be treated as an FS only among user data symbols (DS) of the codeword.
In short, an NPHY can remain compatible with the PPHY's PCS by using an encoding which excludes a specific set of 5B symbols from its alphabet while in the DATA. This locks the PPHY receiver's PCS_RX in the DATA state and prevents the receiver form propagating the data to the MAC.
In addition to this, the received frame should be specifically marked as bad by the PPHY. This is achieved by ensuring a PPHY transitions from DATA to WAIT_SYNC through BAD_ESD, as that asserts the RX_ERR MII signal, and therefore rules out the possibility that the data may be erroneously received by the PPHY's MAC. This transition through BAD_ESD can be ensured by terminating the frame with a ‘T’ followed by a ‘K’ (where ‘K’ has the special function ESDERR and binary values 10001 assigned to by Table “147-1—4B/5B Encoding” in IEEE Std 802.3cg-2019).
To summarize the criteria for an NPHY's FEC-encoded transmission to be backward compatible with a PPHY, it has to use the no more redundancy than is present in PPHY's 4B/5B mapping and must avoid the appearance of FSs in the codewords. Assuming that |FS|=4, where the operator |S| denotes the cardinality of set S, the quantity of this unused information is log2(32−4)−4≈0.8 bit per 5B symbol.
The sensor and IoT applications desired for 10BASE-T1S require low-complexity implementations, and hence research has been driven towards known low-complexity coding techniques. Research within 802.3 has shown that linear block codes have considerable history in Ethernet. Therefore, a focus has been on ways to use coding structures familiar in industry that have existing, proven implementations.
A linear block code is characterized by an (n, k, dmin) triplet, where n denotes the number of codeword symbols, k stands for that of message symbols, and dmin represents the minimum distance of the code (see L. R. Vermani, Elements of Algebraic Coding Theory, Chapman Hall/CRC Mathematics Series, Jan. 1, 1996, which is incorporated herein by reference in its entirety).
As shown later in Section 3.2.3, short block-length is not only preferred to minimize encoding delay at the relatively slow line rate of 10 Mb/s, but is required by existence constraints for the coding scheme.
In order to enable the FS to be escaped before encoding, as described under Section 4, and to take advantage of code shortening, our work further focused on systematic codes.
Maximum Distance Separable (MDS) codes are linear block codes which guarantee that dmin=n−k+1 (see Ron Roth, Introduction to Coding Theory, Cambridge University Press, Feb. 23, 2006, which is incorporated herein by reference in its entirety). In other words MDS codes are (n, k, n−k+1), often referred to as (n, k), and t=└(n−k)/2┘, where t denotes the maximum number of correctable errors. As described in Section 2.4.3 the inherent and reusable redundancy present in the 4B/5B mapping used by the PPHY is relatively small, and therefore MDS codes are the preferred choice for establishing error resilience with low complexity.
Research within IEEE 802.3, and that involving vendors of FEC IP blocks, has shown that while there is a multitude of proven FEC implementations using linear codes and the industry has ample experience with them, these all work over binary (extended) fields. Practical implementations of FEC schemes using ternary or larger base fields are harder to find, and hence a focus has been placed on codes from binary (extended) fields.
However, it is known that the only MDS binary codes that exist are the trivial (n, n) codes, and the Single Parity Check (n, n−1). Therefore, research has focused on Reed-Solomon (RS) codes over extended binary fields.
A discussion of Reed-Solomon (RS) error correcting codes can be found in the following references, all of which are incorporated herein by reference in their entireties:
RS codes are a group of linear cyclic MDS codes over a finite field (GF) that can be used in systematic mode. They belong to the family of Bose-Chaudhuri-Hocquenghem (BCH) codes, and satisfy all the criteria listed in Section 3.1.
Moreover RS codeword shortening allows fine-grained adjustment of code performance. Additionally, encoders and decoders for known code parameters can be considerably optimized, and a multitude of efficient and proven silicon implementations exist for extended fields where the base prime is 2. For these reasons RS codes are a perfect fit for the problem at hand, subject to the constraint that a method can be found to avoid FS.
A key attribute of an RS code is the finite field (GF) over which it is defined. FEC IP blocks are commonly optimized to use pre-calculated lookup tables to speed up arithmetic operations between field elements (scalars) of, and polynomials over these. As the sizes of these lookup tables scale quadratically with the cardinality of the field, it is essential to keep the field size small to manage complexity. The reduction in burst-error correction capability may be offset by the well-known technique of interleaving. A lower bound on the field size is present if interleaving is used: if the number of bits necessary to represent all field elements is not divisible by log2(32)=5, interleaving does not achieve the increase in these capabilities. Therefore the smallest extended field for our FEC is GF(25), also referred to as GF(32).
Let [α, β] denote the closed integer interval with the minimum and maximum values of α and β (respectively). It is known that over GF(32) an (n, k) RS code exists, such that n≤32−1=31, and code shortening makes it possible to choose any integer in [1, n−dmin+1] as k. This is because the unused input symbols are replaced by a pre-agreed constant symbol pattern, and these can be omitted during the transmission of the codeword due to the fact that the code is systematic. In this paper we will refer to this RS code through its parameters (n, n−2t).
To summarize previous subsections, we can state that an (n, n−2t) RS code over GF(32) is applicable to the problem at hand. An encoding process would first receive 4B user data nibbles from the MII, concatenate them, apply the necessary technique to avoid the appearance of FS anywhere in the codeword, and finally feed the resulting block to the RS encoder. The encoded block is passed to the PMA for DME-encoded serial transmission over the wire.
Before going further with our observations, let us introduce two new parameters as follows:
There are 3 things worth noting here:
From hereon we will refer to such a construct as a (c, u) coding scheme. A summary of all the parameters and the encoding process described above is depicted in
Section 3.2.2 showed an encoding process that relies on an example selection of values for the coding parameters c and u, however it is apparent that these are not free variables. In this subsection, the three basic criteria or conditions that should be met for a coding scheme candidate to exist are explained below:
u≥c (1)
5(c−2t)≥4u+ (2)
≥log2(└4u/5┘+1) (3)
From (2) it follows that ≤5(c−2t)−4u and, if is maximized, then =5(c−2t)−4u.
For a discussion on the cases when t>1, see Section 5.4.
Section 3 described a set of basic existence criteria and construction techniques that allow creating different {c, u} coding schemes that meet the backward-compatibility requirements described in Section 2.4 with the exception of avoiding the FS. These are only referred to as candidates, since they are not yet complete solutions. In this section, a solution for avoiding the FS is discussed.
Referring to
This specification discloses a unique combination of three novel techniques, each handling one of the three areas, as described by the following subsections.
An implementation may choose an arbitrary ordering of DS, SB, and PS. However, the arrangement shown by
The 5B symbols comprising the user data are formed by the concatenation of the unconstrained (free) user input data from the MAC, as shown by
Because the encoding of the location of the FS must meet the rate requirement, something more efficient than a simple bitmap encoding is needed. Thus, the combined application of the following two methods are proposed to eliminate FS among the DS:
A naïve approach to form the linked list would be as follows:
Because all FS are transcoded by the linked list, and all the transcoded fs-δ pairs must be represented only by admissible symbols, no FS appear in the output of this iterative process.
However, this naïve approach is not yet complete. The following observations are made:
From these observations it follows that the naive method does not allow δ to be larger than δmax=└(32−4)/4┘−1=6. For example if D5 and D12 were FS, the δ part of the 5B symbol value transcoding D5 would be unable to represent the distance of δ=7 between these.
This problem is resolved by the application of the special constellation-ID mentioned above, which carries additional information with respect to the position of all FS before transcoding is carried out. The special constellation-ID indicates either:
Now, if SB is made to encode the index of the first FS among the DS as well as this special constellation-ID, this method provides a complete solution capable of eliminating all FS among the DS, irrespective of their actual values and locations. In the later part of our paper, we refer to this construct encoded by the SB as an FS Transcoding Recipe (FTR).
This subsection will discuss how many signaling bits (referred to as SB) are needed to represent all necessary FTRs, while also making sure no new FS are created by the SB during the process.
As explained, SB are bits in the codeword, from among which ( mod 5) bits form a mixed DS, in which data form the MS and SB coexist, while the remaining └/5┘ 5B symbols are formed by purely SB, as shown by
In Table 3, it is shown show how many signaling values can be encoded by a 5B symbol with any SB in it. Table 3 also explains what these values are rooted in. From this, for example, it is visible, that a {19, 19} coding scheme, where =4+5=9, can encode 13×29=377 FTRs, so that 9 SB (bits) can carry log2(377)≈8.6 bits of information, while avoiding the appearance of FS among the 5B symbols.
As discussed in Section 4.2, one of the main roles of SB is to encode the FTR required by the coding scheme to avoid FS among the DS. It is obvious however that the number of FTRs needed by the scheme to operate scales with the number of complete DS in it. This relationship is depicted in
Note that some of the information available in the SB will have to be used to avoid FS appearing among the PS. This role is assigned to the terminal 5B symbol that comprises of SB. In short, non-terminal 5B symbol encoding SB represent only the FTR, while the terminal one supports this, and contributes to avoiding FS appearing among the PS, the details of which is explained in Section 4.4.
These 2t 5B symbols are the direct product of the RS encoding of the data bits. Because the data bits are unconstrained and the RS code is MDS, there is no mapping that would avoid the appearance of FS among the PS in all cases. As a result, some additional—yet unused—free bits in the encoder's input must be reserved to influence its output.
This allows the normal RS encoding process to be modified so that when a and b become available during the execution of the polynomial division, s would be selected from the set of admissible 5B symbol values, so that neither P1 nor P2 would end up being FS. The direct application of this method uses the space in s efficiently, but it requires a large lookup table that selects s based on exact values of both a and b. While this process may be implementable, it may not be feasible for low-complexity systems. This lookup considerably simpler can be made considerably simpler by relying on the following two observations:
Given these observations,
P1=j+iλ
P2=iω
i=l+kλ
j=kω
k=b+aλ
l=s+aω (4)
The straightforward simplification of (4) leads to the following results:
What is worth noting here is that P1 is fully determined by sλ, and the same holds for P2's relationship with sω. Therefore, to avoid FS among the PAS, the {c, u} coding scheme may proceed as follows:
=GF(32)∛{‘T’,‘R’,‘I’}, and ν∈{0,1},
1(ν)={x∈|LSB_of(xλ)=ν} (7)
2(ν)={x∈|LSB_of(xω)=ν} (8)
s∈1(LSB_of(P1left))∩2(LSB_of(P2left)). (9)
As this method guarantees that both LSB_of (P1left+sλ) and LSB_of (P2left+sω) will always be 0, it follows that neither P1, nor P2 may turn out to be any of the three applicable FS.
It is worth mentioning, however, that the cardinalities of the four sets (|1(0)|, |1(1)|, |2(0)|, and |2(1)|) depend on the actual values for λ and ω. The cardinalities of these sets may each be anywhere in the interval [5, 7], depending on where the three FS fall in these four sets for the given A and co. As per
It is well worth mentioning that the relationship shown by
The number of FTRs required by a {c, u} coding scheme directly influences its complexity, and as shown in
Earlier
Similar analysis can be performed on candidates of increasing complexity, and as shown in Table 4, the simplest {c, u} coding scheme that exists is {19, 19}. It is worth noting that the calculations under column “FTR possible” of this table follow the explanation in, and the values listed under, column “Number of signaling values” of Table 3, as well as the reasoning in Section 4.4. For example the number of possible FTRs for a {19, 19} coding scheme is listed as 13×7=91. In this calculation the value of 13 stems from the fact that the four bits referred to as S1-4 in
From these it follows, that under the assumptions and using the techniques presented in this paper a {19, 19} coding scheme is optimal both from practical (engineering) and theoretical perspectives.
For other reasons one might choose to use a more complex implementable coding scheme. While these clearly diverge from the above-mentioned optimality, in return a more complex scheme would allow additional information to be encoded into the SB. For example, a {20, 20} coding scheme, would allow up to 29×7=203 (as per Table 3) possible FTRs, while only 69 of those would be required to avoid FS anywhere in the codeword. This allows └log2(203/69)┘=1 free extra bit to be available to represent arbitrary information for every RS codeword, at a cost of decreasing the relative error correcting capability to one 5B symbol per twenty 5B symbols.
Following this thought pattern, it is apparent that using a {21, 21} coding scheme would make little sense, as the number of possible FTRs would still be 1×29×7=203 with an inferior relative error correcting capability compared to that of a {20, 20} coding scheme. Using the method described here, the relevant parameters of any arbitrary {c, u} coding scheme may be analyzed similarly.
Previous sections showed the theoretical constructs behind {c, u} coding scheme. In this subsection we present the full details of an example {19, 19} coding scheme based on those, covering both encoding and decoding, by the direct application of all the methods described in Section 4.
For this example the field and code generator polynomials have been chosen according to Section 6.2.2, thus λ=3 and ω=2. The FS ‘X’ is selected to be represented by the decimal value 0, LSB is used to avoid FS among the PS, and the bits in the codeword are laid out according to
A {19, 19} coding scheme incorporates 15 complete DS, which requires being able to encode 54 FTRs, as per
Under these conditions, it is clear that (5) and (6) simplify to P1=15a+7b+3s and P2=14a+6b+2s (respectively), from which it follows that:
P1left=15a+7b
P2left=14a+6b
1(0)={2,4,6,8,10,12,14,17,19,21,23,25,27,29}
1(1)={1,3,5,9,11,15,16,18,20,22,24,26,28,30}
2(0)={1-6,8-12,14,15}
2(1)={16-30}
Now, the lookup tables that map the admissible symbols can be laid out in the desired manner. In this example we do it using the most natural—incremental—approach, as follows:
The example encoding shown by
The output codeword of this process can either be fed directly to the channel, or to the L-interleaver, to produce a superblock, which is then conveyed to the channel.
The example decoding shown by
This process is able to correct burst errors consisting of any combination of up to L consecutive 5B symbols.
As presented in Sec. 2.4.1, an additional 5B symbol value is reserved to allow reliable signaling of the end of frame. In the scope of this research, when the PCS Transmit function (PCS_TX) detects end of frame, it inserts this reserved symbol followed by an additional symbol indicating success or failure of frame transmission, analogous to the way a PPHY makes either BAD_ESD or GOOD_ESD follow DATA state (see
As the proposed FEC relies on per-frame fixed size superblocks, codeword padding is applied after the symbol that follows FECESD. Given that the symbol following FECESD may have 28 different values, this technique allows the transmission of └log2(2B/2)┘=3 additional bits of information, out of which one bit is used to indicate presence of symbol padding in the last 5B symbol, and every frame is terminated as follows:
For the reasons explained above, FECESD needs to be treated as an FS only when it appears among 5B symbols that form a complete DS. It may indeed appear among 5B symbols formed by SB, or those encoding PS.
With the channel model introduced in Section 1.2, the well-known technique of interleaving can be used to improve the burst error correction capabilities of the code according to known results (see, e.g., Pete Anslow, “RS(544,514) FEC performance with 4:1 interleaving,” August 2018, which is incorporated herein by reference in its entirety). When used with interleaving of depth L, the RS codeword of length=combines with the other interleaved RS codewords to form a superblock of length nL.
Erasure detection can rely on optional side-channel information provided by the receiver, whenever certain parameters of the received digital or analog signals are outside of the valid range. For example erasure may be assumed when the signal's swing, or DME timing is/are beyond a specified range (see Figure “147-13—DME encoding scheme” and Table “147-2—DME timings” in IEEE Std 802.3cg-2019), including tunable tolerances and margins.
Until this subsection, we have discussed applicability of {c, u} coding schemes over GF(32) under the assumption that t=1, despite the fact that should any t>1 schemes exist, those may provide improvement to the relative error correcting capabilities. This subsection focuses on this undiscussed area of the solution candidate space, and shows that no {c, u} coding schemes exist beyond t=1.
To achieve this, the system of three inequalities presented in Section 3.2.3 for t>1, the output of which is visualized by
As explained in Section 3.2.3, =5(c−2t)−4u represents the number of bits available among the SB to encode FTR and to avoid FS among the PS. This is the factor that essentially decides whether a solution candidate may lead to an actual solution.
In each {c, u} coding scheme, the number of PS is 2t, thus for t=2 the scheme has to avoid FS for 4 PS. This will require 4 bits, and therefore a complete 5B symbol, as shown in Table 3, to encode four parametric partitionings. (1-4). This is an extension of the 2 parametric partitionings for t=2 discussed in Section 4.4. Moreover, an additional bit is needed to avoid D25 from being an FS. This leaves 11−5−1=5 bits among the SB available to encode the 494 FTRs necessitated by the 24 complete DS in this scheme, as shown in
In this section, an analysis is conducted of the applicability, some of the characteristics, and the performance of the disclosed scheme.
In general, systematic error correcting codes have the advantage of being encodable “on-the-fly”: when the data arrives, the encoder can already start forming the codewords, producing output without delay. However in the case proposed herein, this does not stand. The reason for this is three-fold:
An upper bound on the total delay caused by these factors is 5cL+ϵ, bit times, where ϵ denotes the implementation-dependent encoding and decoding delays in the silicon, and 5cL is the size of the superblock in time domain
In contrast, for a PPHY that works without FEC and relies on retransmissions, the lower bound for these delays is the total transmission time for the packet. In the case of Ethernet this is 512 bit times, in addition to the delays imposed by the higher layers carrying out the retransmissions. The packet retransmission delays are—typically several magnitudes—larger than the delays attributed to the scheme proposed herein with any reasonable value for L, irrespective of whether the higher layers use a positive or a negative acknowledgement scheme for triggering a retransmission.
Additionally, actual implementations hiding or incorporating the MII interface may partially or completely eliminate encoding and decoding delay, benefitting the proposed scheme.
To verify the performance of the proposed FEC scheme claimed in this application, this research has implemented the complete encoding and decoding scheme over configurable field- and code-generator polynomials. An exhaustive test over the extended field GF(32) defined by the field generator polynomial of p(x)=x5+x2+1, and the code generator polynomial of g(x)=(x+ac(x+ac+1)=x2+3x+2 (for c=0) has been performed using the {19, 19} coding scheme over a (19, 17) systematic RS code, based on the algorithm presented in this specification, while the choice of actual 5B symbol values was done according to Section 4.7.
These exhaustive simulations have run without errors, showing that scheme proposed in this paper is both implementable and working as theory suggests.
In the presented pseudo-code, a set of specific functions are used, as shown herein:
Based on this, the algorithm used for the end-to-end verification of the proposed novel scheme is as follows:
As visible, this will result in 515≈3×1010 encoding and 515×20≈6.1×1011 decoding cycles. This simulation has run without errors, ending in stop(SUCCESS), showing the scheme proposed in this specification to be implementable and working as theory suggests.
This specification has shown that it is possible to design and implement low-complexity, backward compatible FEC using the novel combination of an RS FEC scheme, a linked-list-based technique to skip forbidden symbols in the MII data part of the codeword, and a lightweight linear coding technique that guarantees the same for the signaling and parity symbols.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
This application is a Continuation of PCT International Application No. PCT/IB2021/057420, filed on Aug. 11, 2021, which claims priority under 35 U.S.C. 119(e) to U.S. Provisional Application No. 63/064,822, filed on Aug. 12, 2020, all of which are hereby expressly incorporated by reference into the present application.
Number | Date | Country | |
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63064822 | Aug 2020 | US |
Number | Date | Country | |
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Parent | PCT/IB2021/057420 | Aug 2021 | US |
Child | 18108306 | US |