Patent Application
20170111011
This application claims priority of Taiwanese Application No. 104133852, filed on Oct. 15, 2015.
The disclosure relates to a mixer, and more particularly to a balanced up-conversion mixer.
Referring to
The mixing circuit 12 includes a current source 121, a transduction unit 122 and a mixing unit 123.
The current source 121 receives a bias voltage (Vb), and is use to modulate a total bias current flowing therethrough. The transduction unit 122 is coupled between the current source 121 and the mixing unit 123, and is used to receive a differential intermediate frequency (IF) voltage signal pair that consists of positive-phase and negative-phase IF voltage signals. The transduction unit 122 is operative to allow a differential IF current signal pair to flow into the current source 121 therethrough based on the differential IF voltage signal pair. The differential IF current signal pair constitutes the total bias current, and consists of positive-phase and negative-phase IF current signals (I11, I12). The mixing unit 123 is coupled between the transduction unit 122 and the load circuit 11, and is used to receive a differential oscillating voltage (OV) signal pair that consists of positive-phase and negative-phase OV signals. The mixing unit 123 is operative to allow, based on the differential OV signal pair, a differential radio frequency (RF) current signal pair flowing through the load circuit 11 to flow therethrough and into the transduction unit 122. The differential RF current signal pair consists of positive-phase and negative-phase RF current signals (I21, I22), and serves as the differential IF current signal pair.
The load circuit 11 outputs a differential RF voltage signal pair based on its impedance and on the positive-phase and negative-phase RF current signals (I21, I22). The signal amplifier circuit 13 is coupled to the load circuit 11 for receiving the differential RF voltage signal pair therefrom. The signal amplifier circuit 13 amplifies the differential RF voltage signal pair so as to generate a positive-phase output voltage signal and a negative-phase output voltage signal.
In such a configuration, upon DC analysis, since the current flowing into the transduction unit 122 flows entirely through the load circuit 11, power consumed by the load circuit 11 is relatively high. In addition, the conventional balanced up-conversion mixer typically improves its self-conversion gain by increasing its power requirements. As a result, the conventional balanced up-conversion mixer may have a further increased power consumption. In other words, the conventional balanced up-conversion mixer cannot obtain a high conversion gain at low power consumption.
Therefore, an object of the disclosure is to provide a balanced up-conversion mixer that can overcome the drawbacks of the prior art.
According to the disclosure, the balanced up-conversion mixer includes a single-ended to differential conversion circuit, a negative resistance compensation circuit, a load circuit, a mixing circuit and a signal amplifier circuit.
The single-ended to differential conversion circuit is used to receive an oscillating voltage signal, and is configured to generate a differential oscillating voltage signal pair based on the oscillating voltage signal.
The negative resistance compensation circuit is used to receive a direct current (DC) bias voltage, and is configured to generate and output a first current and a second current based on the DC bias voltage.
The load circuit is used to receive the DC bias voltage, and is configured to permit a differential radio frequency (RF) current signal pair to flow out of the load circuit and to output a differential RF voltage signal pair based on an impedance thereof, the DC bias voltage and the differential RF current signal pair.
The mixing circuit is used to receive a differential intermediate frequency (IF) voltage signal pair, and is coupled to the single-ended to differential conversion circuit for receiving the differential oscillating voltage signal pair therefrom, to the negative resistance compensation circuit for receiving the first and second currents therefrom and to the load circuit for receiving the differential RF current signal pair therefrom. The mixing circuit is configured to allow the RF current signal pair to flow thereinto based on the differential IF voltage signal pair, the differential oscillating voltage signal pair and the first and second currents.
The signal amplifier circuit is used to receive the DC bias voltage, and is coupled to the load circuit for receiving the differential RF voltage signal pair therefrom. The signal amplifier circuit is configured to amplify the differential RF voltage signal pair so as to generate a differential output voltage signal pair.
The differential RF voltage signal pair has a frequency associated with those of the differential oscillating voltage signal pair and the differential IF voltage signal pair.
Other features and advantages of the disclosure will become apparent in the following detailed description of the embodiment with reference to the accompanying drawings, of which:
Before the disclosure is described in greater detail, it should be noted that where considered appropriate, reference numerals or terminal portions of reference numerals have been repeated among the figures to indicate corresponding or analogous elements, which may optionally have similar characteristics.
In addition, when two elements are described as being “coupled in series,” “connected in series” or the like, it is merely intended to portray a serial connection between the two elements without necessarily implying that the currents flowing through the two elements are identical to each other and without limiting whether or not an additional element is coupled to a common node between the two elements. Essentially, “a series connection of elements,” “a series coupling of elements” or the like as used throughout this disclosure should be interpreted as being such when looking at those elements alone.
Referring to
The single-ended to differential conversion circuit 2 is used to receive an oscillating voltage (OV) signal, and is configured to generate a differential oscillating voltage (DOV) signal pair based on the OV signal. In this embodiment, the DOV signal pair consists of positive-phase and negative-phase OV signals (Vos1, Vos2).
The negative resistance compensation circuit 3 is used to receive a direct current (DC) bias voltage (VDD), and is configured to generate and output first and second currents (I1, I2) based on the DC bias voltage (VDD). In this embodiment, the negative resistance compensation circuit 3 includes a first transistor 31 and a second transistor 32.
Each of the first and second transistors 31, 32 has a first terminal, a second terminal and a control terminal. The first terminals of the first and second transistors 31, 32 are coupled with each other to receive the DC bias voltage (VDD). The control terminals of the first and second transistors 31, 32 are coupled respectively to the second terminals of the second and first transistors 32, 31. The first and second currents (I1, I2) flow out of the negative resistance compensation circuit 3 respectively through a common node (N1) between the second terminal of the first transistor 31 and the control terminal of the second transistor 32, and a common node (N2) between the control terminal of the first transistor 31 and the second terminal of the second transistor 32. It should be noted that each of the first and second transistors 31, 32 is, for example, a P-type metal-oxide-semiconductor field effect transistor (MOSFET), which has a source, a drain and a gate serving respectively as the first, second and control terminals thereof.
The mixing circuit 4 is coupled to the single-ended to differential conversion circuit 2 for receiving the DOV signal pair therefrom, and to the negative resistance compensation circuit 3 for receiving the first and second currents (I1, I2) therefrom. The mixing circuit 4 is used to further receive a differential intermediate frequency voltage (DIFV) signal pair. The mixing circuit 4 is configured to allow, based on the DIFV signal pair, on the DOV signal pair and on the first and second currents (I1, I2), a differential radio frequency current (DRFC) signal pair (Ir) flowing through the load circuit 5 to flow thereinto. It should be noted that the DIFV signal pair used in this embodiment may be generated in a known manner. The DIFV signal pair consists of positive-phase and negative-phase IFV signals (Vi1, Vi2). The DRFC signal pair (Ir) consists of positive-phase and negative-phase radio frequency current (RFC) signals (Ir1, Ir2).
In this embodiment, the mixing circuit 4 includes a current source 41, a transduction unit 42 and a mixing unit 43.
The current source 41 is configured to modulate a total bias current flowing therethrough. The transduction unit 42 is coupled between the current source 41 and the negative resistance compensation circuit 3. The transduction unit 42 is used to receive the DIFV signal pair, and is configured to allow, based on the DIFV signal pair, a differential intermediate frequency current (DIFC) signal pair to flow therethrough and into the current source 41. In this case, the DIFC signal pair serves as the total bias current, and includes the first and second currents (I1, I2) from the negative resistance compensation circuit 3. The DIFC signal pair consists of positive-phase and negative-phase intermediate frequency current (IFC) signals (Ii1, Ii2). In this embodiment, the transduction unit 42 includes first and second input nodes (P1, P2), an output node (P3), first to fourth transistors 421, 422, 423, 424 and a resistor 425.
The first and second input nodes (P1, P2) are coupled respectively to the common nodes (N1, N2) of the negative resistance compensation circuit 3. The positive-phase and negative-phase IFC signals (Ii1, Ii2) flow into the transduction unit 42 respectively through the first and second input nodes (P1, P2). The output node (P3) is coupled to the current source 41. The DIFC signal pair flows out of the transduction unit 42 through the output node (P3) and flows into the current source 41. Each of the first and second transistors 421, 422 has a first terminal that is coupled to the first input node (P1), a second terminal that is coupled to the output node (P3), and a control terminal that is used to receive the positive-phase IFV signal (Vi1) such that the first and second transistors 421, 422 are operable to be conducting or non-conducting in response to the positive-phase IFV signal (Vi1). The third transistor 423 has a first terminal that is coupled to the second input node (P2), and a second terminal that is coupled to the output node (P3). The fourth transistor 424 and the resistor 425 are coupled in series between the second input node (P2) and the output node (P3). The fourth transistor 424 has a first terminal that is coupled to the resistor 425, a second terminal that is coupled to the output terminal (P3). Each of the third and fourth transistors 423, 424 further has a control terminal that is used to receive the negative-phase IFV signal (Vi2) such that the third and fourth transistors 423, 424 are operable to be conducting or non-conducting in response to the negative-phase IFV signal (Vi2). It should be noted that the first transistor 421 is, for example, a P-type MOSFET, which has a source, a drain and a gate serving respectively as the first, second and control terminals thereof. Each of the second to fourth transistors 422, 423, 424 is, for example, an N-type MOSFET, which has a drain, a source and a gate serving respectively as the first, second and control terminals thereof.
The mixing unit 43 is coupled to the transduction unit 42, the load circuit 5 and the single-ended to differential conversion circuit 2. The mixing unit 43 receives the DOV signal pair from the single-ended to differential conversion circuit 2. The mixing unit 43 is configured to allow, based on the DOV signal pair, the DRFC signal pair (Ir) from the load circuit 5 to flow therethrough and into the transduction unit 42. In this embodiment, the mixing unit 43 includes first and second input nodes (Q1, Q2), first and second output nodes (Q3, Q4), and first to fourth transistors 431, 432, 433, 434.
The first and second input nodes (Q1, Q2) are coupled to the load circuit 5. The positive-phase and negative-phase RFC signals (Ir1, Ir2) flow into the mixing unit 43 respectively through the first and second input nodes (Q1, Q2). The first and second output nodes (Q3, Q4) are coupled respectively to the first and second input nodes (P1, P2) of the transduction unit 42. The first transistor 431 is coupled between the first input node (Q1) and the first output node (Q3). The second transistor 432 is coupled between the second input node (Q2) and the second output node (Q4). Each of the first and second transistors 431, 432 has a control terminal that is used to receive the positive-phase OV signal (Vos1) such that the first and second transistors 431, 432 are operable to be conducting or non-conducting in response to the positive-phase OV signal (Vos1). The third transistor 433 is coupled between the second input node (Q2) and the first output node (Q3). The fourth transistor 434 is coupled between the first input node (Q1) and the second output node (Q4). Each of the third and fourth transistors 433, 434 has a control terminal that is used to receive the negative-phase OV signal (Vos2) such that the third and fourth transistors 433, 434 are operable to be conducting or non-conducting in response to the negative-phase OV signal (Vos2). It should be noted that each of the first to fourth transistors 431, 432, 433, 434 further has a first terminal and a second terminal. The first and second terminals of the first transistor 431 are coupled respectively to the first input node (Q1) and the first output node (Q3). The first and second terminals of the second transistor 432 are coupled respectively to the second input node (Q2) and the second output node (Q4). The first and second terminals of the third transistor 433 are coupled respectively to the second input node (Q2) and the first output node (Q3). The first and second terminals of the fourth transistor 434 are coupled respectively to the first input node (Q1) and the second output node (Q4). In this embodiment, each of the first to fourth transistors 431, 432, 433, 434 is, for example, an N-type MOSFET, which has a drain, a source and a gate serving respectively as the first, second and control terminals thereof.
When the first and second transistors 431, 432 conduct in response to the positive-phase OV signal (Vos1) while the third and fourth transistors 433, 434 do not conduct in response to the negative-phase OV signal (Vos2), the positive-phase and negative-phase RFC signals (Ir1, Ir2) flow out of the mixing unit 43 respectively through the first and second output nodes (Q3, Q4) and flow into the transduction unit 42. In this case, the positive-phase RFC signal (Ir1) and the first current (I1) cooperatively constitute the positive-phase IFC signal (Ii1), and the negative-phase RFC signal (Ir2) and the second current (I2) cooperatively constitute the negative-phase IFC signal (Ii2). When the first and second transistors 431, 432 do not conduct in response to the positive-phase OV signal (Vos1) while the third and fourth transistors 433, 434 conduct in response to the negative-phase OV signal (Vos2), the positive-phase and negative-phase RFC signals (Ir1, Ir2) flow out of the mixing unit 43 respectively through the second and first output nodes (Q4, Q3) and flow into the transduction unit 42. In this case, the negative-phase RFC signal (Ir2) and the first current (I1) cooperatively constitute the positive-phase IFC signal (Ii1), and the positive-phase RFC signal (Ir1) and the second current (I2) cooperatively constitute the negative-phase IFC signal (Ii2).
The load circuit 5 is used to receive the DC bias voltage (VDD), and is configured to permit the DRFC signal pair (Ir) to flow out of the load circuit 5 and to output a differential radio frequency voltage (DRFV) signal pair based on its impedance, the DC bias voltage (VDD) and the DRFC signal pair (Ir). The DRFV signal pair has a frequency associated with a frequency of the DOV signal pair and a frequency of the DIFV signal pair. It is noted that the frequency of the DRFV signal pair is, but not limited to, a sum of the frequencies of the DOV and DIFV signal pairs. For example, if the frequency of the DOV signal pair is 93.9 GHz and the frequency of the DIFV signal pair is 0.1 GHz, then the frequency of the DRFV signal pair would be 94 GHz (=93.9 GHz+0.1 GHz).
In this embodiment, the DRFV signal pair consists of positive-phase and negative-phase radio frequency voltage (RFV) signals (Vr1, Vr2). The load circuit 5 includes first and second inductors 51, 52. Each of the first and second inductors 51, 52 has opposite first and second terminals. The first terminals of the first and second inductors 51, 52 are coupled with each other to receive the DC bias voltage (VDD). The second terminals of the first and second inductors 51, 52 are coupled respectively to the first and second input nodes (Q1, Q2) of the mixing unit 43. The load circuit 5 outputs the positive-phase and negative-phase RFV signals (Vr1, Vr2) respectively at the second terminals of the first and second inductors 51, 52. It is noted that each of the first and second inductors 51, 52 is, for example, a transmission line inductor.
The signal amplifier circuit 6 is used to receive the DC bias voltage (VDD), and is coupled to the load circuit 5 for receiving the positive-phase and negative-phase RFV signals (Vr1, Vr2) therefrom. The signal amplifier circuit 6 is configured to amplify the positive-phase and negative-phase RFV signals (Vr1, Vr2) so as to generate a differential output voltage signal pair. In this embodiment, the differential output voltage signal pair consists of positive-phase and negative-phase output voltage signals (Vo1, Vo2). The signal amplifier circuit 6 includes first and second inductors 60, 61, first to sixth transistors 62-67 and first and second resistors 68, 69.
The first inductor 60, the first to third transistors 62, 63, 64 and the first resistor 68 are coupled in series. The first inductor 60 is used to receive the DC bias voltage (VDD). The first transistor 62 is coupled between the first inductor 60 and the second transistor 63. The first transistor 62 has a control terminal that is coupled to the load circuit 5 for receiving the positive-phase RFV signal (Vr1) therefrom such that the first transistor 62 is operable to be conducting or non-conducting in response to the positive-phase RFV signal (Vr1). The third transistor 64 is coupled between the second transistor 63 and the first resistor 68. Each of the second and third transistors 63, 64 has a control terminal that is used to receive a control signal (VG) such that the second and third transistors 63, 64 are operable to be conducting or non-conducting in response to the control signal (VG). The first resistor 68 is coupled between the third transistor 64 and ground. The positive-phase output voltage signal (Vo1) is outputted at a first common node (C1) between the first transistor 62 and the second transistor 63. The second inductor 61, the fourth to sixth transistors 65, 66, 67 and the second resistor 69 are coupled in series. The second inductor 61 is used to receive the DC bias voltage (VDD). The fourth transistor 65 is coupled between the second inductor 61 and the fifth transistor 66. The fourth transistor 65 has a control terminal that is coupled to the load circuit 5 for receiving the negative-phase RFV signal (Vr2) therefrom such that the fourth transistor 65 is operable to be conducting or non-conducting in response to the negative-phase RFV signal (Vr2). The sixth transistor 67 is coupled between the fifth transistor 66 and the second resistor 69. Each of the fifth and sixth transistors 66, 67 has a control terminal that is used to receive the control signal (VG) such that the fifth and sixth transistors 66, 67 are operable to be conducting or non-conducting in response to the control signal (VG). The second resistor 69 is coupled between the sixth transistor 67 and ground. The negative-phase output voltage signal (Vo2) is outputted at a second common node (C2) between the fourth transistor 65 and the fifth transistor 66.
The differential to single-ended conversion circuit 7 is coupled to the signal amplifier circuit 6 for receiving the positive-phase and negative-phase output voltage signals (Vo1, Vo2) therefrom, and is configured to generate an output voltage signal based on the positive-phase and negative-phase output voltage signals (Vo1, Vo2).
A conversion gain of the balanced up-conversion mixer can be expressed by the following equation:
where CG represents the conversion gain, Gm,Lo represents an equivalent input transconductance of the first and third transistors 431, 433 at the first output node (Q3) or an equivalent input transconductance of the second and fourth transistors 432, 434 at the second output node (Q4), gm31,32 is an equivalent input transconductance of the first and second transistors 31, 32, gm421,422,423,424 is an equivalent input transconductance of the first to fourth transistors 421-424, ωRF is an operating frequency of the balanced up-conversion mixer (i.e., the frequency of the DRFV signal pair of, for example, 94 GHz), L is an inductance of one of the first and second inductors 51, 52.
It is known from the equation that the conversion gain (CG) increases with increase of at least one of the transconductance (gm31,32), which is smaller than the equivalent input transconductance (Gm,Lo), and the transconductance (gm421,422,423,424).
It should be noted that since the thickness of each of the bottom metals 81, 91, 92, 93 is thinner, each of the bottom metals 81, 91, 92, 93 has a higher power loss. Therefore, by reducing the number of the bottom metals, the power loss of the single-ended to differential conversion circuit 2 and/or the differential to single-ended conversion circuit 7 can be reduced. When the single-ended to differential conversion circuit 2 and the differential to single-ended conversion circuit 7 are implemented by 1-underneath metal Marchand baluns 8 each only having one bottom metal 81, the balanced up-conversion mixer may have a smaller power loss as compared to when the single-ended to differential conversion circuit 2 and the differential to single-ended conversion circuit 7 are implemented using 3-underneath metal Marchand baluns 9.
Measurement results of the balanced up-conversion mixer of this disclosure with the single-ended to differential conversion circuit 2 and the differential to single-ended conversion circuit 7 implemented using 1-underneath metal Marchand baluns 8 and of the conventional balanced up-conversion mixer depicted in
To sum up, upon DC analysis, since the DIFC signal pair consists of the DRFC signal pair (Ir) and the first and second currents (I1, I2), the load circuit 5 of this disclosure consumes relatively low power as compared to the load circuit 11 of
In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiment(s). It will be apparent, however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. It should also be appreciated that reference throughout this specification to “one embodiment,” “an embodiment,” an embodiment with an indication of an ordinal number and so forth means that a particular feature, structure, or characteristic may be included in the practice of the disclosure. It should be further appreciated that in the description, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects.
While the disclosure has been described in connection with what is considered the exemplary embodiment, it is understood that this disclosure is not limited to the disclosed embodiment but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 104133852 | Oct 2015 | TW | national |
