Patent Application
20130049778
1. Technical Field
The exemplary disclosure generally relates to balancing resistor testing apparatuses, particularly to a balancing resistor testing apparatus for testing a resistance of a balancing resistor electronically connected to a series supercapacitor assembly.
2. Description of Related Art
A series supercapacitor assembly is generally composed of two or more supercapacitors connected in series. Since each of the supercapacitors have different internal resistances, voltage of each supercapacitor is different from each other, which will affect a capability of the series supercapacitor assembly.
One way to decrease the differences in the voltages between the supercapacitors is by connecting a balancing resistor to each supercapacitor in parallel. The balancing resistor acts like a big voltage divider and counteracts the effects of variance in internal resistances of the supercapacitors to help the supercapacitors to approximately have a same voltage. One way to choose an appropriate resistance of each balancing resistor is by connecting a resistor to each supercapacitor on a printed circuit board (PCB), and detecting the voltage of each supercapacitor. If there is a difference between the respective voltages of the supercapacitors, then removing the resistor from the PCB and connecting another resistor having a different resistance on the PCB until the supercapacitors share an equal voltage. However, the aforementioned method requires replacing the resistors many times which will increase a testing time and may destroy the supercapacitors.
Therefore, there is room for improvement within the art.
Many aspects of the embodiments can be better understood with reference to the drawings. In the drawings, the emphasis is placed upon clearly illustrating the principles of the disclosure.
Referring to
Referring to
The controller 10 includes a first voltage detecting pin P1, a second voltage detecting pin P2, a first controlling pin P3 and a second controlling pin P4. The controller 10 detects the voltages across the first supercapacitor C1 and the second supercapacitor C2 via the first voltage detecting pin P1 and the second voltage detecting pin P2 respectively. The controller 10 controls the charging circuit 20 to charge the series supercapacitor 200 via the first controlling pin P3, and controls the discharging circuit 30 to discharge the series supercapacitor 200 via the second controlling pin P4.
The charging circuit 20 includes a charging chip 21 and a first filter circuit 23 and a second filter circuit. The charging chip 21 includes a power input pin VIN, a charging current output pin COUT and an enable pin SHDN. The power input pin VIN is electrically connected to a power supply V-IN. In one embodiment, the power supply V-IN can be a 5 volt power supply, and the power input pin VIN is electrically connected to the 5 volt power supply via the first filter circuit 23. The charging current output pin COUT is electrically connected to the series supercapacitor assembly 200 and ground in series, that is, the first supercapacitor C1 and the second supercapacitor C2 are connected between the charging current output pin COUT and ground in series. The enable pin SHDN is electronically connected to the first controlling pin P3. When the controller 10 outputs a first voltage signal, e.g. a low level voltage signal (e.g. logic 0) to the enable pin SHDN via the first controlling pin P3 to activate the charging chip 21, the charging chip 21 converts a current outputted from the power supply V-IN to a charging current, which is then forward to the series supercapacitor assembly 200 to charge the series supercapacitor assembly 200. When the controller 10 outputs a second voltage signal, e.g. a high level voltage signal (e.g. logic 1) to the enable pin SHDN via the first controlling pin P3 to deactivate the charging chip 21, the charging chip 21 stops charging the series supercapacitor assembly 200. In one embodiment, the charging chip 21 can be a programmable supercapacitor charger LTC3225 made by Linear Technology Corporation, and the charging chip 21 is activated when the enable pin SHDN is at a low level voltage (e.g. logic 0).
The first filter circuit 23 reduces noise induced at the power input pin VIN. The filter circuit 23 includes an inductor L1, a first filter capacitor C3, and a second filter capacitor C4. The inductor L1 is electronically connected between the power supply V-IN and the power input pin VIN in series, a node between the inductor L1 and the power supply V-IN is grounded via the first filter capacitor C3, and a node between the inductor L1 and the power input pin VIN is grounded via the second filter capacitor C4. The second filter circuit is substantially third filter capacitor C5, in one example. The third capacitor C5 is electronically connected between the charging current output pin COUT and the ground in series to reduce noise induced at the charging current output pin COUT.
The discharging circuit 30 is an electronic switch connected between the ground and a node between the charging current output pin COUT and the series supercapacitor assembly 200. The electronic switch is further electronically connected to the controller 10. When the charging circuit 20 charges the series supercapacitor assembly 200, the controller 10 controls the electronic switch to turn off. When the charging circuit 20 stops charging the series supercapacitor assembly 200, the controller 10 controls the electronic switch to turn on, thereby the series supercapacitor assembly 200 can discharge to ground via the electronic switch.
In the exemplary embodiment, the electronic switch is a N channel Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). A drain D of the N channel MOSFET is electronically connected to a node between the charging current output pin COUT and the series supercapacitor assembly 200 via a discharging resistor R0, a gate G of the N channel MOSFET is electronically connected to the second controlling pin P4, and a source S of the N channel MOSFET is grounded. When the controller 10 outputs a low level voltage signal (logic 0) to the gate G via the second controlling pin P4, the N channel MOSFET is turned off. When the controller 10 outputs a high level voltage signal (logic 1) to the gate G via the second controlling pin P4, the N channel MOSFET is turned on. The electronic switch can be a NPN type bipolar junction transistor (BJT), of which the base, the emitter and the collector have electronic connections to peripheral circuits respectively corresponding to the gate G, the source S and the drain D of the N channel MOSFET.
Referring to
The first wiper pin VW1 and the second connecting pin VL1 are respectively connected to a positive terminal and negative terminal of the first supercapacitor C1, the first connecting pin VH1 is not connected. An effective resistance of the first variable resistor connected to the first supercapacitor C1 in parallel is labeled as a first effective resistor R1, the effective resistance of the second variable resistor connected to the second supercapacitor C2 in parallel is labeled as a second effective resistor R2. The digital potentiometer 40 adjusts the resistance of the first and second effective resistors R1, R2 according to the control of the controller 10. In the exemplary embodiment, the first and second effective resistors R1, R2 have the same resistance.
When the resistances of the first and second effective resistors R1, R2 change, the voltages across the first and second supercapacitors C1, C2 correspondingly change. The resistances of the first and second effective resistors R1, R2, are changed until the voltages across the first and second supercapacitors C1, C2 are the same, or any difference between the voltages across the first and second supercapacitors C1, C2 is within a predetermined difference range. At this time, the resistance of the first effective resistor R1 is equivalent to the resistance of a balancing resistor of the first supercapacitor C1, and the resistance of the second effective resistor R2 is equivalent to the resistance of a balancing resistor of the second supercapacitor C2.
The display 50 displays the resistance values of the first and second effective resistors R1, R2. In the exemplary embodiment, since the first and second effective resistors R1 and R1 have the same resistance, the display 50 only shows one resistance. When the controller 10 detects that the voltages across the first and second supercapacitors C1, C2 are the same, or any difference between the voltages across the first and second supercapacitors C1, C2 is within a predetermined difference range, the controller 10 records the resistances of the first and the second effective resistors R1, R2, which is then forwarded to the display 50. Thus, a tester can easily know the resistances of the balancing resistors of the first and second supercapacitors C1, C2 from the display 50.
The working process of the balancing resistor testing apparatus 100 can be carried out by, but is not limited to, the following steps. The first and second voltage detecting pins P1 and P2 of the controller 10 are connected to the positive terminals of the first and second supercapacitors C1, C2. The controller 10 sets the resistances of the first and second effective resistors R1, R2 via the digital potentiometer 40, at this time, the first and second effective resistors R1, R2 preferably have a small resistance. The controller 10 then controls the charging circuit 20 to charge the series supercapacitor 200. After charging, the voltage of the positive terminal of the first supercapacitor C1 is labeled as Vc, the voltage of the positive terminal of the second supercapacitor C2 is labeled as Vm, and the ratio of the voltage Vc and the voltage Vm (Vc/Vm) is labeled as A. Controller 10 detects the voltages Vc and Vm via the first and second voltage detecting pins P1 and P2, and computes and records the ratio A. After that, the controller 10 controls the discharging circuit 30 to discharge the series supercapacitor 200. After discharging, the controller 10 controls the charging circuit 20 to charge the series supercapacitor 200 again, and detects the voltages Vc and Vm and computes the ratio A. The balancing resistor testing apparatus 100 repeats the above process N (e.g. N=10) times, the controller 10 can then compute the average value of N number of ratio A, if the average value equals 2 or the difference between the average value and 2 is within a determined difference range, the voltage across the first supercapacitor C1 can be considered equal to the voltage across the second supercapacitor C2, at this time, the resistance of the first effective resistor R1 is equivalent to the resistance of the balancing resistor of the first supercapacitor C1, and the resistance of the second effective resistor R2 is equivalent to the resistance of the balancing resistor of the second supercapacitor C2. The controller 10 then controls the display 50 to display the resistances of the first and second effective resistors R1, R2.
If the difference between the average value and 2 is outside the determined difference range, the controller 10 controls the digital potentiometer 40 to increase by equal increments the resistances of the first and second effective resistors R1, R2,. The balancing resistor testing apparatus 100 then repeats the aforesaid process to detect the voltages cross the first and second supercapacitors C1, C2, until the voltages across the first and second supercapacitors C1, C2 are the same.
The controller 10 controls the digital potentiometer 40 to adjust each potentiometer connected to a supercapacitor, until voltages across the supercapacitors are the same, at this time, the effective value of the variable resistor is equivalent to the resistance of a balancing resistor required for the supercapacitor. Hence, a tester can easily know the resistance of the balancing resistors of each supercapacitor of the series supercapacitor assembly 200, and does not need to keep changing the resistors connected to the supercapacitors in parallel on a PCB, which will save testing time.
It is believed that the exemplary embodiments and their advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the disclosure or sacrificing all of its material advantages, the examples hereinbefore described merely being preferred or exemplary embodiments of the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201110254648.8 | Aug 2011 | CN | national |
