Bandgap circuit with temperature correction

Abstract
A temperature corrected voltage bandgap circuit is provided. The circuit includes first and second diode connected transistors. A first switched current source is coupled to the one transistor to inject or remove a first current into or from the emitter of that transistor. The first current is selected to correct for curvature in the output voltage of the bandgap circuit at one of hotter or colder temperatures.
Description

BRIEF DESCRIPTION OF THE DRAWING

The invention will be better understood from a reading of the following detailed description in conjunction with the drawing figures in which like reference designators identify like elements, and in which:



FIG. 1 illustrates a prior art CMOS N-well substrate having a bipolar transistor structure of a type that may be utilized in a bandgap circuit;



FIG. 2 is a schematic of the prior art bipolar structure of FIG. 1;



FIG. 3 is a schematic of a prior art bandgap circuit;



FIG. 4 is a typical plot of bandgap circuit voltage versus temperature for the prior art circuit of FIG. 4;



FIG. 5 is a schematic of a circuit in accordance with the principles of the invention;



FIG. 6 is a plot of bandgap circuit voltage versus temperature with high temperature compensation in accordance with the principles of the invention;



FIG. 7 is a plot of bandgap circuit voltage versus temperature with low temperature compensation in accordance with the principles of the invention;



FIG. 8 is a plot of bandgap circuit voltage versus temperature with high and low temperature compensation in accordance with the principles of the invention; and



FIG. 9 is a schematic of a bandgap circuit in accordance with the principles of the invention.





DETAILED DESCRIPTION

For a bipolar transistor the first order equation for collector current related to Vbe is:






I
c
=AI
s(e(Vbe·q)/kT−1)


where:


T is temperature in Kelvin;
A is an area scale;
Is is dark current for a unit area device (process dependent);

q is charge on the electron; and


K is Boltzman's constant.

In the forward direction, even at very low bias, the (e(Vbe·q)/kT) term over-powers the −1 term. Therefore in the forward direction:






I
c
=I
s(e(Vbe·q)/kT)





, and






V
be=(kT/q)·ln(Ic/AIs)


Two junctions operating at different current densities will have a different Vbe related by the natural logs of their current densities.


From this it can be shown that the slope of Vbe vs. temperature must depend on current density. Vbe has a negative temperature coefficient. However, the difference in Vbe, called the ΔVbe, has a positive temperature coefficient.





ΔVbe=Vbe|1−Vbe|A=(kT/q)·[ln(I1/IS)−ln(I2/AIS)]


For I1=I2 and an area scale of A





ΔVbe=(kT/q)ln A


In the illustrative embodiment of the invention, a bandgap circuit is formed as part of a CMOS device of the type utilizing CMOS N-well process technology.


The most usable bipolar transistors available in the CMOS N-well process is the substrate PNP as shown in FIG. 1 in which a single transistor Q1 is formed by transistors Q1′, Q1″ which has an area ratio, A, that is twice that of the transistor Q2. The structure is shown in schematic form in FIG. 2. All the collectors of transistors Q1′, Q1″, Q2 are connected to the chip substrate 101, i.e., ground. There is direct electrical access to the base and emitter of each transistor Q1′, Q1″, Q2 to measure or control Vbe but there is no separate access to the collectors of the transistors Q1′, Q1″, Q2 to monitor or control collector current.


There are several general topologies based on the standard CMOS process and its substrate PNP that can be used to create a bandgap circuit.



FIG. 3 illustrates a prior art bandgap circuit 301 architecture. Bandgap circuit 301 comprises transistor Q1 and transistor Q2. The area of transistor Q1 is selected to be a predetermined multiple A of the area of transistor Q2. First and second serially connected resistors R1, R2 are connected between an output node Vbandgap and the emitter of transistor Q2. A third resistor is connected in series between output node Vref and the emitter of transistor Q1. A differential input amplifier AMP has a first input coupled to a first circuit node disposed between resistors R1, R2; and a second input coupled to a second node disposed between resistor R3 and the emitter of transistor Q1. Amplifier AMP has its output coupled to the output node bandgap.


Bandgap voltage and slope with respect to temperature or temperature coefficient, TC, are sensitive to certain process and design variables.


With the foregoing in mind, considering all the variables, and making specific assumptions, a closed form for the bandgap voltage is:






Vbandgap=(kT/q)·{ln[((kT/q)·ln A/Rt)/Is]}+(1+R2/R1)(kT/q)·ln A


This is of the form Vref=Vbe+mΔVbe

When m is correctly set, the temperature coefficient of Vref will be near zero. The resulting value of Vref will be near the bandgap voltage of silicon at 0° K., thus the name “bandgap circuit.”


However, Vbe for a bipolar transistor operating at constant current has a slight bow over temperature. The net result is that a plot of bandgap voltage Vref against temperature has a bow as shown by curve 401 in FIG. 4.


In accordance with one aspect of the invention, a simple differential amplifier formed by transistors M1, M2 as shown in FIG. 5 is used and a comparison is made between a near zero temperature coefficient voltage from the bandgap to the negative temperature coefficient of the bandgap Vbe. By providing proper scaling to add or subtract a controlled current to the bandgap at hot and cold temperatures the bandgap curve is flattened.



FIG. 5 illustrates a portion of a simplified curvature corrected bandgap circuit in accordance with the principles of the invention.


Transistor M1 and transistor M2 compare the nearly zero temperature coefficient, TC, voltage V1 (derived from the bandgap) to the Vbe voltage of the unit size bipolar transistor Q2 in the bandgap. By adjusting the value of V1 the threshold temperature where the differential pair M1, M2 begins to switch and steer current provided by transistor M3 into the bandgap is moved. Voltage V1 is selected to begin adding current at the temperature where the bandgap begins to dip, e.g., 40° C. The width/length W/L ratio of transistors M1, M2 will define the amount of differential voltage necessary to switch all of the current from transistor M2 to transistor M1. The current I sets the maximum amount of current that can or will be added to the bandgap.


In accordance with the principles of the invention, by utilizing 3 transistors and 2 resistors the correction threshold, rate (vs. temperature) and amount of curvature (current) correction on the high temperature side can be corrected. The effect of this current injection is shown by curve 601 in FIG. 6


The comparator/current injection structure can be mirrored for curvature correction of the cold temperature side of the bandgap by providing current removal from the larger or A sized transistor Q1 of the bandgap circuit. The effect of such curvature correction on the cold side is shown by curve 701 in FIG. 7.


A fully compensated bandgap circuit in accordance with the principles of the invention that provides both hot and cold temperature compensation is shown in FIG. 9.


The circuit of FIG. 9 shows substantial improvement in performance over a temperature range of interest is −40 to 125° C. A plot of Vref versus temperature is shown in FIG. 8 as curve 801.


The compensated circuit of FIG. 9 includes bandgap circuit 1001, current injection circuit 1003 and current injection circuit 1005.


Bandgap circuit 1001 comprising a transistor Q2 and a transistor Q1. The area of transistor Q1 is selected to be a predetermined multiple A of the area of transistor Q2. First and second serially connected resistors R1, R2 are connected between an output node Vbandgap and the emitter of transistor Q2. A third resistor is connected in series between output node Vref and the emitter of transistor Q1. A differential input amplifier AMP has a first input coupled to a first circuit node disposed between resistors R1, R2; and a second input coupled to a second node disposed between resistor R3 and the emitter of transistor Q1. Amplifier AMP has its output coupled to the output node Vbandgap.


A first switchable current source 1003 is coupled to said transistor Q2 to inject a first current into the emitter of transistor Q2. The current Iinj1 is selected to correct for one of hotter or colder temperatures, more specifically, in the illustrative embodiment, the current Iinj1 is injected at higher temperatures when the base emitter voltage across transistor Q2 to a first predetermined voltage Vset. The voltage Vset is determined by a resistance network formed by resistors R4, R5, R6.


A second switchable current source 1005 is coupled to transistor Q1 to remove a second current Iinj2 into the emitter of transistor Q1. The second current Iinj2 is selected to correct for the other of the hotter or colder temperatures, and more specifically for colder temperatures.


Bandgap circuit 1001, and switchable current injection circuits 1003, 1005 are formed on a single common substrate 1007.


The resistors R4, R5, and R6 are trimmable resistors and are utilized to select the voltages at which the current sources inject current from switchable current injection circuits 1003, 1005 into bandgap circuit 1001.


The invention has been described in terms of illustrative embodiments. It is not intended that the scope of the invention be limited in any way to the specific embodiments shown and described. It is intended that the invention be limited in scope only by the claims appended hereto, giving such claims the broadest interpretation and scope that they are entitled to under the law. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit or scope of the invention. It is intended that all such changes and modifications are encompassed in the invention as claimed.

Claims
  • 1. A bandgap circuit comprising: a diode connected first transistor and a diode connected second transistor, said first transistor and said second transistor each having a plurality of terminals and each being connected in a bandgap circuit;a first switchable current source coupled to said second transistor to inject a first predetermined current into said second transistor when the voltage between two of said second transistor terminals has a predetermined relationship to a first voltage, whereby first temperature compensation is provided to said bandgap circuit.
  • 2. A bandgap circuit in accordance with claim 1, comprising: a second switchable current source coupled to said first transistor to remove a second predetermined current from said first transistor when the voltage between two of said first transistor terminals has a predetermined relationship to a second voltage, whereby second temperature compensation is provided to said bandgap circuit.
  • 3. A bandgap circuit in accordance with claim 2, comprising: a single substrate having said first and second transistors, said first switchable current source and said second switchable current source formed thereon.
  • 4. A bandgap circuit in accordance with claim 3, wherein: said first transistor is a bipolar transistor, and said second transistor is a bipolar transistor.
  • 5. A bandgap circuit in accordance with claim 4, wherein: said first switchable current source and said second switchable current source each comprise MOS transistors.
  • 6. A bandgap circuit in accordance with claim 3, wherein: said substrate is of a type utilizing CMOS N-well process technology.
  • 7. A bandgap circuit in accordance with claim 6, wherein: each of said first transistor and said second transistor comprises a substrate PNP transistor.
  • 8. A bandgap circuit in accordance with claim 7, wherein: said first switchable current source and said second switchable current source comprise CMOS transistors.
  • 9. A bandgap circuit in accordance with claim 1, comprising: a single substrate having said first and second transistors, and said first switchable current source formed thereon.
  • 10. A bandgap circuit in accordance with claim 9, wherein: said first transistor is a bipolar transistor, and said second transistor is a bipolar transistor.
  • 11. A bandgap circuit in accordance with claim 10, wherein: said first switchable current source comprises MOS transistors.
  • 12. A bandgap circuit in accordance with claim 9, wherein: said substrate is of a type utilizing CMOS N-well process technology.
  • 13. A bandgap circuit in accordance with claim 12, wherein: each of said first transistor and said second transistor comprises a substrate PNP transistor.
  • 14. A bandgap circuit in accordance with claim 13, wherein: said first switchable current source comprises CMOS transistors.
  • 15. A bandgap circuit in accordance with claim 1, wherein: one of said first transistor or said second transistor has an area that is a multiple, A, times the area of the other of said first transistor or said second transistor.
  • 16. A bandgap circuit in accordance with claim 2, wherein: one of said first transistor or said second transistor has an area that is a multiple, A, times the area of the other of said first transistor or said second transistor and said first temperature compensation compensates for effects of temperatures above a predetermined temperature of said substrate, and said second temperature compensation compensates for effects of temperatures below a predetermined temperature.
  • 17. A temperature corrected bandgap circuit, comprising: a first transistor and a second transistor, the area of said first transistor selected to be a predetermined multiple of the area of said second transistor; first and second serially connected resistors connected between an output node and the emitter of said first transistor; a first circuit node disposed between said first and second serially connected resistors; a third resistor connected in series between said output node and the emitter of said second transistor; a second node disposed between said third resistor and said second transistor emitter; a differential input amplifier having a first input coupled to said first node and a second input coupled to said second node; said amplifier having its output coupled to said output nodea first switched current source, comprising: a voltage responsive switch coupled to said first transistor to inject or remove a first current into or from said first transistor when the output voltage at said output node is at a first predetermined level, said first current being selected to provide temperature correction in said output voltage for one of hotter or colder temperatures;
  • 18. A bandgap circuit in accordance with claim 17, comprising: a second switched current source, comprising: a second voltage responsive switch coupled to said second transistor to remove or inject a second current from or into said second transistor when the output voltage at said output node is at a second predetermined level, said second current being selected to provide temperature correaction in said output voltage for the other of said hotter or colder temperatures.
  • 19. A bandgap circuit in accordance with claim 18, wherein: said first transistor is a bipolar transistor, and said second transistor is a bipolar transistor.
  • 20. A bandgap circuit in accordance with claim 19, wherein: said first switched current source and said second switched current source each comprise MOS transistors.
  • 21. A bandgap circuit in accordance with claim 20, wherein: said bandgap circuit is formed on a single substrate, and said substrate is of a type utilizing CMOS N-well process technology.
  • 22. A bandgap circuit in accordance with claim 17, wherein: said first transistor is a bipolar transistor, and said second transistor is a bipolar transistor.
  • 23. A bandgap circuit in accordance with claim 22, wherein: said first switched current source comprises MOS transistors.
  • 24. A bandgap circuit in accordance with claim 23, wherein: said bandgap circuit is formed on a single substrate, and said substrate is of a type utilizing CMOS N-well process technology.