Patent Application
20230409058
The present invention relates to a bandgap module and a linear regulator, and more particularly to a bandgap module and a linear regulator consuming a low quiescent current, having low noise, and having a short start-up time.
Portable electronic devices are widely used, and a battery is necessary for portable electronic devices. The battery provides a supply voltage Vdd to a load circuit for operation. However, the supply voltage Vdd is not constant, and a linear regulator has been adopted to provide a stable regulated voltage Vreg to the load circuit.
The linear regulator is connected to the output of the battery, and the linear regulator regulates the supply voltage Vdd to generate the regulated voltage Vreg. In portable electronic devices such as Internet of things (hereinafter, IoT) devices, the battery is always equipped. As time passes, the waveform WF1 (supply voltage Vdd) continuously decreases, but the waveform WF2 (regulated voltage Vreg) maintains a certain value. Thus, the use of the linear regulator becomes a stable and consistent voltage source, and the linear regulator is critical in portable electronic devices.
The linear regulator 13 is a low-dropout (hereinafter, LDO) linear regulator including a bandgap circuit 131, an error amplifier 133, a PMOS transistor Men, and branch resistors Ra, Rb. The source terminal and the gate terminal of the PMOS transistor Men are respectively electrically connected to the battery 11 and an output terminal of the error amplifier 33. The non-inverting input terminal (+) and the inverting input terminal (−) of the error amplifier 133 are respectively electrically connected to the bandgap circuit 131 and the branch resistors Ra, Rb. The branch resistors Ra, Rb are serially connected between the drain terminal of the PMOS transistor Men and a ground terminal Gnd. For the sake of representation, both the ground voltage and the ground terminal are represented as Gnd in the specification. The error amplifier 133 receives a reference voltage Vref from the bandgap circuit 131.
Based on the reference voltage Vref and the branch resistors Ra, Rb, the regulated voltage Vreg can be represented as
Therefore, precision, stability, and start-up speed of the reference voltage Vref influence the behavior of the regulated voltage Vreg.
Therefore, the present invention relates to a bandgap module and a linear regulator having a low quiescent current, low noise, and short start-up time.
An embodiment of the present invention provides a bandgap module. The bandgap module includes a bandgap circuit, a start-up module, and a lowpass filter. The bandgap circuit includes an operational amplifier, a current mirror, a first loading branch, a second loading branch, and a bandgap branch. The operational amplifier includes a first input terminal, a second input terminal, and a current control terminal. The current mirror is electrically connected to the first input terminal, the second input terminal, and the current control terminal. The current mirror generates a first loading current, a second loading current, and a mirrored current. The first loading, the second loading current, and the mirrored current are generated based on a signal at the current control terminal. The first loading current, the second loading current, and the mirrored current are equivalent. The first loading branch is electrically connected to the first input terminal, and the second loading branch is electrically connected to the second input terminal. The first loading branch receives the first loading current, and the second loading branch receives the second loading current. The bandgap branch is electrically connected to the current mirror. The bandgap branch receives the mirrored current and conducts a bandgap current. A bandgap voltage is generated based on the bandgap current. The start-up module includes a first start-up circuit and a second start-up circuit. The first start-up circuit is electrically connected to the bandgap circuit. The first start-up circuit accelerates the generation of the mirrored current so that the bandgap voltage is increased to a predefined value when the bandgap module operates in a first phase. The second start-up circuit is electrically connected to the bandgap circuit, the lowpass filter, and the first start-up circuit. The second start-up circuit conducts an additional current to the bandgap branch and maintains the bandgap voltage at the predefined value when the bandgap module operates in a second phase. The second phase is after the first phase. The lowpass filter is electrically connected to the bandgap circuit and the second start-up circuit. The lowpass filter filters the noise of the bandgap voltage and generates a reference voltage accordingly.
Another embodiment of the present invention provides a linear regulator. The linear regulator receives a supply voltage, and the linear regulator includes the bandgap module and an error amplifier. The error amplifier is electrically connected to the bandgap module. The error amplifier generates an error signal by comparing the reference voltage with a comparison voltage. A regulated voltage is generated based on the supply voltage and the error signal.
In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.
The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
For portable battery operated device applications such as IoT devices, the linear regular needs to have low-power, low-noise and short start-up time. In such devices, power consumption should be low to extend battery life, and the linear regulator needs low noise to ensure proper functionality of sensitive analog circuits. Usually IoT devices have to respond very fast to various events that the device is reporting and then transmit to the server, so the short start-up time is also an essential criteria.
The specification illustrates the embodiments of bandgap modules and LDO linear regulators with low quiescent current, low noise, and fast start-up time. The bandgap module receives the supply voltage Vdd and generates a constant reference voltage Vref accordingly. The reference voltage Vref is further utilized to generate a regulated voltage Vreg for the load circuit.
The bandgap circuit 211 provides a constant bandgap voltage Vbg at the bandgap terminal Nbg, and the lowpass filter 213 filters out the noise at the bandgap voltage Vbg and outputs the reference voltage Vref at a reference terminal Nref.
Please note that, in some applications, the bandgap circuit 211 may include a power-down transistor Mpd to save power and extend battery life. The power-down transistor Mpd is electrically connected to the supply voltage terminal (Vdd) and a current control terminal Nc. The power-down transistor Mpd is controlled by a power-down signal Spd. When the electronic device is in a power-down mode or a sleep mode, the power-down transistor Mpd is switched on, and the supply voltage Vdd is conducted to the current control terminal Nc to disable the loading transistors Mp1, Mp2, and the mirror transistor Mmir. On the other hand, when the electronic device operates in a normal operation mode, the power-down transistor Mpd is switched off, and the bandgap circuit 211 operates normally. In the specification, the power-down signal Spd is assumed to be set to the logic high (Spd=H).
The bandgap circuit 211 includes a current mirror 211e, an operational amplifier OP, loading branches 211a, 211c, and a bandgap branch 211g. The current mirror 211e and the bandgap branch 211g are electrically connected to the bandgap terminal Nbg. The current mirror 211e and the loading branch 211a are electrically connected to a terminal Na (that is, the inverting input terminal (−) of the operational amplifier OP), and the current mirror 211e and the loading branch 211c are electrically connected to a terminal Nb (that is, the non-inverting input terminal (+) of the operational amplifier OP).
The current mirror 211e includes loading transistors Mp1, Mp2, and a mirror transistor Mmir. In the current mirror 211e, the loading transistors Mp1, Mp2, and the mirror transistor Mmir are PMOS transistors. The currents flowing through the loading transistors Mp1, Mp2 are respectively defined as loading currents Ia, Ib, and the current flowing through the mirror transistor Mmir is defined as a mirrored current Imir. It is assumed that the loading transistor Mp1, Mp2, and the mirror transistor Mmir have the same aspect ratio, so the current values of the loading currents Ia, Ib, and the mirrored current Imir are equivalent (Ia=Ib=Imir).
The loading branch 211a includes a transistor Qa and a branch resistor Ra, and the loading branch 211c includes a transistor Qb and branch resistors Rb1, Rb2. In the loading branch 211a, a branch current Ia1 flows through the transistor Qa, a branch current Ia2 flows through the branch resistor Ra, and the summation of the branch currents Ia1, Ia2 is equivalent to the loading current Ia. In the loading branch 211c, a branch current Ib1 flows through the transistor Qa and the branch resistor Rb1, a branch current Ib2 flows through the branch resistor Rb2, and the summation of the branch currents Ib1, Ib2 is equivalent to the loading current Ib.
The resistance values of the branch resistors Ra, Rb2 are equivalent. It is assumed that the transistors Qa, Qb are PNP-type bipolar junction transistors (BJT). In practical applications, the transistors Qa, Qb can be replaced with diodes.
The bandgap branch 211g includes a bandgap resistor R3. The bandgap resistor R 3 is electrically connected to the bandgap terminal Nbg and the ground terminal Gnd, and a bandgap current Ibg flows through the bandgap resistor R3 to the ground terminal Gnd. In
The gate terminals of the loading transistors Mp1, Mp2, and the mirror transistor Mmir are jointly electrically connected to a current control terminal Nc (that is, the output terminal of the operational amplifier OP), and the source terminals of the loading transistors Mp1, Mp2, and the mirror transistor Mmir are electrically connected to the supply voltage terminal Nvdd. The drain terminals of loading transistors Mp1, MP2, and the mirror transistor Mmir are respectively electrically connected to the terminal Na, the terminal Nb, and the bandgap terminal Nbg.
In the loading branch 211a, the base terminal (B) and the collector terminal (C) of the transistor Qa are electrically connected to the ground terminal Gnd. The emitter terminal (E) of the transistor Qa is electrically connected to the terminal Na. The resistor Ra is electrically connected to the terminal Na and the ground terminal Gnd. In the loading branch 211c, the base terminal (B) and the collector terminal (C) of the transistor Qb are electrically connected to the ground terminal Gnd. The branch resistor Rb1 is electrically connected to the terminal Nb and the emitter terminal (E) of the transistor Qb. The branch resistor Rb2 is electrically connected to the terminal Nb and the ground terminal Gnd.
Please refer to the loading branch 211a. The terminal voltage Va is equivalent to the emitter-base voltage difference Veb_a of the transistor Qa, wherein the terminal voltage Va is complementary to absolute temperature (hereinafter, CTAT). According to the current equation of the transistor Qa, the branch current Ia1 can be represented by equation (1).
The variable Isa represents the saturation current of the transistor Qa, and the variable VT represents a thermal voltage. Through the conduction of equation (1), the emitter-base voltage difference Veb_a of the transistor Qa can be obtained by equation (2).
On the other hand, the branch current Ia2 can be represented as
Please refer to the loading branch 211c. Similarly, the branch current Ib1 can be represented by equation (3), and the emitter-base voltage difference Veb_b of the transistor Qb can be represented by equation (4).
In equations (3) and (4), the variable Isb represents the saturation current of the transistor Qb. As the terminal voltages Va, Vb are equivalent, and the branch resistors Ra, Rb2 are equivalent, the branch current Ib2 can be represented as
As the emitter-base voltage difference Veb_a of the transistor Qa is CTAT, the branch current Ib2 is a CTAT current.
In the specification, it is assumed that the transistor size of the transistor Qb is equivalent to N times of the transistor size of the transistor Qa. Therefore, the saturation current Isb of the transistor Qb and the saturation current Isa of the transistor Qa have the following relationship Isb=N*Isa.
In
ΔV=Veb_a−Veb_b=VT. ln(N) equation (5)
The voltage difference ΔV can be considered a product of the branch resistor Rb1 and the branch current Ib1 (ΔV=Ib1*Rb1), and the branch current Ib1 can be represented by equation (6).
In equation (6), the voltage difference ΔV is proportional to absolute temperature (hereinafter, PTAT), and the branch current Ib1 is a PTAT current.
As the loading current Ib is equivalent to the summation of the branch currents Ib1 , Ib2 (Ib=Ib1+Ib2), the loading current Ib includes a PTAT current (that is, Ib1) and a CTAT current (that is, Ib2).
The bandgap voltage Vbg can be considered as the voltage difference across the combination of the bandgap resistor R3. The bandgap voltage Vbg can thus be presented as the product of the bandgap current Ibg and the bandgap resistor R3 (that is, Vbg=Ibg*R3).
As the bandgap current Ibg, the loading current Ib, and the mirrored current Imir are equivalent (Ibg=Ib=Imir), the bandgap current Ibg can also be represented as the summation of the branch currents Ib1, Ib2 (Ibg=Ib1+Ib2). Accordingly, the bandgap voltage Vbg is generated by the summation of the two branch currents Ib1 and Ib2, multiplied by the bandgap resistor R3. The bandgap voltage Vbg can be represented by equation (7).
Consequentially, by choosing appropriate resistance values for the branch resistors Rb1, Rb2, and the bandgap resistor R3, a predefined value of the bandgap voltage Vbg, independent of temperature variation and equivalent to a scales sum of CTAT and PTAT voltages, can be obtained. As long as the bandgap voltage Vbg is precisely maintained at the predefined value, the precision of the reference voltage Vref can be guaranteed.
The bandgap module 21 can be a dominant noise contributor. To keep the noise low, the lowpass filter 213 is employed to lower the noise without a power penalty. The lowpass filter 213 includes a loading resistor Rld and a loading capacitor Cld, and both are electrically connected to the reference terminal Nref.
The loading resistor Rld is electrically connected to the bandgap terminal Nbg, and the loading capacitor Cld is electrically connected to the ground terminal Gnd. The loading resistor Rld conducts the bandgap voltage Vbg to the reference terminal Nref, and the loading capacitor Cld stabilizes the reference voltage Vref and filters out the noise in the bandgap voltage Vbg.
In
The bandgap circuit 311 and the lowpass filter 313 are similar to those in
The coarse start-up circuit 315 includes a coarse trigger circuit 3151 and a pull-down transistor Mdn. In the specification, it is assumed that the pull-down transistor Mdn is an NMOS transistor, and the coarse trigger circuit 3151 generates a coarse trigger signal Sc_trig to enable/disable the pull-down transistor Mdn. Whereas, in practical applications, the pull-down transistor Mdn can be a PMOS, and the design of the coarse trigger circuit 3151 may vary.
The coarse trigger circuit 3151 is electrically connected to the terminal Nb and the gate terminal of the pull-down transistor Mdn. The drain terminal and the source terminal of the pull-down transistor Mdn are respectively electrically connected to the current control terminal Nc and the ground terminal Gnd.
The coarse trigger signal Sc_trig is generated in response to the terminal voltage Vb. The coarse trigger signal Sc_trig switches on the pull-down transistor Mdn, so the gate terminal of the mirror transistor Mmir can be quickly dropped to the ground voltage Gnd. Thus, the mirror transistor Mmir is switched on faster, and the mirrored current Imir can be increased instantaneously.
Whenever the terminal voltage Vb is lower than a predefined threshold voltage Vth1, the coarse trigger circuit 3151 generates the coarse trigger signal Sc_trig to switch on the pull-down transistor Mdn. Consequentially, the current control voltage Vc is conducted to the ground terminal Gnd and the loading transistors Mp1, MP2 are completely switched on. Then, a larger terminal current Ia flows through the loading transistor Mp1, and a greater loading current Ib flows through the loading transistor Mp2.
When the electronic device switches from the power-off state to the power-on state, or switches from the power saving mode to the normal operation mode, the signal at supply voltage terminal Nvdd needs to take some time to change from the ground voltage Gnd to the supply voltage Vdd. During the ramping up of the supply voltage terminal Nvdd, the terminal voltage Vb should continuously increase from 0V to the predefined value. However, when the power is just turned on, it is possible that there is no loading current Ia, Ib, or both, or the loading current Ib is not enough to bring up the terminal voltage Vb. In consequence, the increment of the bandgap voltage Vbg is very slow. Thus, the coarse trigger circuit 3151a helps to inject current to the terminal voltage Va and the terminal voltage Vb to assist in quickly starting up the bandgap voltage Vbg.
According to the embodiment of the present disclosure, the coarse trigger circuit 3151 directly detects one of the terminal voltages Va, Vb and generates the coarse trigger signal Sc_trig in response. For the sake of illustration, detection of the terminal voltage Vb is described as an example. As long as the terminal voltage Vb is still below the threshold voltage Vth1 (Vb<Vth1), the coarse trigger circuit 3151a determines that the bandgap voltage Vbg is still not high enough and pulls up the coarse trigger signal Sc_trig to switch on the pull-down transistor Mdn. Once the pull-down transistor Mdn is switched on, the current control voltage Vc is pulled down, and currents conducted by the loading transistors Mp1, Mp2 become greater. Consequentially, the currents being injected to the terminals Na, Nb are increased, and the terminal voltages Va, Vb are increased accordingly.
With the gradual increment of the terminal voltage Vb, the coarse trigger circuit 3151a confirms that the relationship (VbVth1) becomes satisfied. Under such circumstances, the coarse trigger circuit 3151 generates the coarse trigger signal Sc_trig to switch off the pull-down transistor Mdn and to inform the fine trigger circuit 3171 to start to compare the reference voltage Vref with the threshold voltage Vth2. Then, the pull-down transistor Mdn stops affecting the current control voltage Vc, and the fine trigger circuit 3171 starts to operate.
The fine start-up circuit 317 includes a fine trigger circuit 3171 and switches sw1, sw2, sw3, sw4. The switch sw3 is a two-way switch. The common terminal of the switch sw3 is electrically connected to the gate terminal of the additional transistor Mx, and the switch terminals of the switch sw3 are respectively electrically connected to the voltage supply terminal Nvdd and the current control terminal Nc.
The fine trigger circuit 3171 receives the coarse trigger signal Sc_trig from the coarse trigger circuit 3151 and receives the reference voltage Vref from the lowpass filter 313. Based on the coarse trigger signal Sc_trig and the reference voltage Vref, the fine trigger circuit 3171 generates the fine trigger signal Sf_trig.
The switches sw1, sw2, sw3, sw4 are controlled by the fine trigger signal Sf_trig. For the sake of comparison, the relationships between the conduction states of switches sw1, sw2, sw3, sw4, and the fine trigger signal Sf_trig are summarized in Table 1. Details about how the logic level of the fine trigger signal Sf_trig is determined and its subsequent operations of the switches sw1, sw2, sw3, sw4 are described later.
When the fine trigger signal Sf_trig is set to the logic high (Sf_trig=H), the switches sw1, sw2, sw4 are switched on, and the switch sw3 connects the gate terminal of the additional transistor Mx to the current control terminal Nc. When the fine trigger signal Sf_trig is set to the logic low (Sf_trig=L), the switches sw1, sw2, sw4 are switched off, and the switch sw3 connects the gate terminal of the additional transistor Mx to the supply voltage terminal Nvdd.
The switch sw4 is electrically connected to the drain terminal of the additional transistor Mx and the bandgap terminal Nbg. Thus, the switch sw4 selectively conducts the bandgap voltage Vbg to the drain terminal of the additional transistor Mx.
The bandgap resistor R3b and the switch sw2 are connected in parallel. Thus, when the switch sw2 is switched on, a bandgap current Ibg flows through only the bandgap resistor R3 and the switch sw2, not through the bandgap resistor R3b.
Once the fine trigger circuit 3171 receives the coarse trigger signal Sc_trig representing that the terminal Vb is greater than or equivalent to the threshold voltage Vth1 (Vb≥Vth1), and the fine trigger circuit 3171 confirms that the reference voltage Vref is lower than the threshold voltage Vth2 (Vref<Vth2), the fine trigger circuit 3171 sets the fine trigger signal Sf_trig to the logic high (Sf_trig=H). Otherwise, the fine trigger signal Sf_trig is set to the logic low (Sf_trig=L).
The selections of the threshold voltages Vth1, Vth2 are freely set by the designer and independent to each other. The threshold voltage Vth1 is set for the terminal Vb, and the threshold voltage Vth2 is set for the reference voltage Vref node. The threshold voltage Vth2 is dependent on filter size (RC values) as well.
The fine trigger circuit 3171 can be, for example, a NOR gate logic. Whereas the design and the implementation of the fine trigger circuit 3171 should not be limited.
The lowpass filter 313 includes a loading resistor Rld and a loading capacitor Cld, and both are electrically connected to the reference terminal Nref. The loading resistor Rld and the switch sw1 are connected in parallel. Thus, when the switch sw1 is switched on, the loading capacitor Cld is charged by the bandgap voltage Vbg through the switch sw1, not through the loading resistor Rld.
Changes of the bandgap current Ibg, the bandgap voltage Vbg, and the resistance value of the bandgap branch in the coarse phase (PH1) and the fine phase (PH2) are compared in Table 2.
Please refer to
Please refer to
Please note that, in
Assuming that the additional current Ix is equivalent to the mirrored current Imir in the fine phase (PH2), the bandgap current Ibg in the fine phase (PH2) will be equivalent to two times of the bandgap current Ibg in the coarse phase (PH1). Based on the equivalences of the bandgap current Ibg (Ibg=Imir in the coarse phase (PH1), and Ibg=Imir+Ix=2*Imir in the fine phase (PH2)), and the feature that the bandgap voltage Vbg remains constant by the end of the coarse phase (PH1) and during the fine phase (PH2), it can be further concluded that the resistance values of the bandgap resistors R3a, R3b are equivalent. That is, R3a=R3b because Vbg=Ibg*Rbg=Imir*(R3a-FR3b).(Imir-Flx)*R3a=2*Imir*R3a.
The electronic device might proceed with a start-up procedure in different scenarios, for example, in a scenario where the electronic device is switched from a power-off state to a power-on state, or in a scenario where the electronic device switches from a power-saving state (for example, a power-down mode or a sleep mode) to an active state (for example, a normal operation mode).
The always-on battery-powered electronic device stays in the power-saving state most of the time (sleep duration Tsleep), but occasionally needs to wake up for a short period (active duration Tact). When the electronic device switches to be active, a start-up procedure is required before the electronic device actually enters the normal operation mode.
Before a power-on time point ton, the electronic device is in a power-saving state (or a power-off state). After the power-on time point ton, the electronic device starts its start-up procedure. The duration of the start-up procedure is defined as a start-up duration Tstart. By the end of the start-up procedure, the electronic device enters the normal operation mode at the stable time point tstable.
The bandgap module 31, according to the embodiment of the present disclosure, shortens the start-up duration Tstart by separating the start-up procedure into a coarse phase (PH1) and a fine phase (PH2). In the coarse phase (PH1), the bandgap voltage (Vbg) is quickly increased up to the predefined value, but the increasing speed of the reference voltage Vref is dragged by the lowpass filter 313. In the fine phase (PH2), the bandgap voltage (Vbg) is maintained at the predefined value, and the reference voltage (Vref) is quickly increased through the conduction of the switch sw1.
The embodiment in
While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
