Patent Application
20140015509
The present invention relates generally to voltage reference and voltage regulator circuits, and more particularly, to a bandgap voltage reference and regulator circuit with a common amplifier.
Voltage references and voltage regulators are electronic circuits that are coextensively used in electronic circuits. Bandgap based voltage references supply a constant and stable reference voltage, typically within the bandgap voltage operating point of 1.2V, to other devices in a circuit such as voltage regulators. Voltage regulators provide a constant voltage, independent of load current, for a predetermined range of load currents.
The bandgap voltage reference typically includes a bandgap core having multiple resistors in combination with multiple transistors and a gain stage to generate the reference voltage equal to the bandgap voltage of the semiconductor material. The voltage regulator receives an input reference voltage generated by the bandgap voltage reference. The voltage regulator typically includes multiple transistors with multiple output resistors in a voltage divider arrangement as load in combination with an error amplifier to regulate and maintain the output voltage. Bandgap voltage references together with voltage regulators are able to supply a voltage that is stable and self-regulated over time under varying load currents, voltage supplies and temperatures. However, the use of these two circuits in tandem as conventionally arranged is relatively expensive to implement from power and area considerations as the industry demands integrated circuit (IC) designs with ever decreasing power supplies and smaller footprints. Each circuit occupies valuable circuit area and requires significant power in space-limited and low power applications.
Accordingly, there is a need for addressing or at least alleviating some of the above limitations and problems.
The accompanying drawings incorporated herein and forming a part of the specification illustrate several aspects of the present invention and, together with the description, serve to explain the principles of the invention. While the invention will be described in connection with certain embodiments, there is no intent to limit the invention to those embodiments described. On the contrary, the intent is to cover all alternatives, modifications and equivalents as included within the scope of the invention as defined by the appended claims. In the drawings:
The present invention provides a bandgap voltage reference and voltage regulator system that includes a bandgap voltage reference circuit and a voltage regulator circuit that share a single, common amplifier. The amplifier acts as a gain stage for the bandgap voltage reference circuit and an error amplifier for a driver stage of the voltage regulator circuit. The voltage regulator circuit has an input reference generated by the bandgap voltage reference circuit. The bandgap circuit acts as a load to the driver stage of the regulator circuit, which obviates the need for a bias resistance network, which is typically needed in conventional linear regulators to support the no load condition. The system does not require a resistor network to bias the output driver transistor. Thus, without the need for a resistor network and using a shared amplifier, the area and overall quiescent current are less than those of conventional circuits.
In one embodiment, the present invention provides an operational amplifier shared by a bandgap voltage reference circuit and a voltage regulator circuit having a driver stage. The operational amplifier includes an inverted input, a non-inverted input, an output, a first stage, and a second stage. The first stage is connected to the inverted and non-inverted inputs, and the second stage generates the output. A current reference stage includes elements from the first stage of the operational amplifier. The operational amplifier provides a gain stage for the bandgap voltage reference circuit, and provides an error amplifier for the driver stage of the voltage regulator circuit.
Referring now to
In one embodiment, the driver stage 40 comprises a voltage driver transistor, such as metal oxide semiconductor field effect transistor (MOSFET), where the output of the op amp 30 is connected to the gate of the voltage driver transistor, a drain of the transistor is connected to the supply voltage (Vdd) 42, and the output voltage (Vout) 44 of the system 10 is derived at the source of voltage driver transistor. The output voltage Vout 44 is the main output of the system 10. Although the voltage driver transistor is shown as a NMOS transistor, it will be appreciated that the transistor can take other forms. For example, the transistor may be a PMOS transistor to form a PMOS driver to achieve a low dropout regulator (LDO). In such an LDO, the source of the PMOS transistor is connected to the supply voltage (Vdd), the drain is connected to the Vout 44, and the output of the operational amplifier 30 drives the gate of the PMOS transistor. Also, for a PMOS driver, the connections at the inputs of the op amp 30 are reversed.
Referring to
The first and second core transistors 66, 68 are connected together, each having its base and collector connected to the common ground (Vss). A ratio “M” between the emitter areas of the first and second core transistors 66, 68 may be substantially matched. In one embodiment, the area of the second core transistor 68 has an area that is M times larger than the area of the first core transistor 66.
A first end of the first core resistor 60 is connected to the emitter of the second core transistor 68, and a first end of the second core resistor 62 is connected to the emitter of the first core transistor 66. A first end of the third core resistor 64 is connected to a second end of the first core resistor 60 such that the first and third core resistors 60, 64 are connected in series. A second end of the second core resistor 62 and a second end of the third core resistor 64 are connected together and to the operating voltage (Vbgr) 22.
The inverted input 26 of the op amp 30 is connected to a node between the first and third core resistors 60, 64, and the non-inverted input 28 of the op amp 30 is connected to a node between the second core resistor 62 and the emitter of the first core transistor 66. In this embodiment, the first core transistor 66 and the second core transistor 68 are parasitic bipolar transistors. The output of the op amp 30 is connected to the driver stage 40.
A start-up circuit 70, in accordance with an embodiment of the invention, is connected to the inverted input 26 and non-inverted input 28 of the op amp 30. The start-up circuit 70 also is connected to the operating voltage (Vbgr) 22 and the second ends of the second and third core resistors 62, 64. The start-up circuit 70 further is connected to the output of the op amp 30, i.e. the voltage (Vdriver) 32 at a node between the output of the op amp 30 and an input of the driver stage 40. In this embodiment, the driver stage 40 comprises a transistor having a gate connected to the output of the op amp 30, and a drain connected to the supply voltage Vdd.
The system 50 also has a first capacitor 72 connected between an input of a second stage (Diff_out) of the op amp 30 and a source of the transistor of the driver stage 40. A second capacitor 74 is connected to the output of the op amp 30 and the source of the transistor of the driver stage 40. Also, the output voltage (Vout) 44 of the system 50 is provided at the source of the transistor of the driver stage 40. The first and second capacitors 72, 74 provide stability to the system 50 as well as ensure high unity-gain bandwidth. The first capacitor 72 introduces a local, small-signal feedback from the output voltage (Vout) 44 to the input of second stage (Diff_out) of the op amp 30, and significantly increases the unity-gain bandwidth (UGB) of the system 50, which in turn improves the transient behaviour of the system with respect to load current regulation. In one embodiment, the first capacitor 72 has a relatively higher capacitance value than the second capacitor 74. The first and second capacitors 72, 74 may comprise MOS capacitances that have a certain variation in capacitances across process-voltage-temperature (PVT) variations. The second capacitor 74 is placed to maintain a minimum phase-margin of 45° across PVT variations.
A switching load current 76 for the external circuitry that the system 50 is supplying is connected to the source of the transistor of the voltage driver 40. More particularly, the switching load current 76 is connected between the operating voltage Vbgr and the common ground Vss, and the connection between the operating voltage Vbgr and the load current 76 also is connected to the start-up circuit 70 and the source of the transistor of the driver stage 40 (i.e., the voltage Vout). It will be appreciated that any number of circuits could be supplied, such as for example a real time clock (RTC) module until the current supply capability limit of the system 50 is reached. It will be appreciated that the driver stage 50 can be made using a PMOS transistor.
The start-up circuit 70 operates during the supply ramp up and sets the bias currents in the op amp 30. The start-up circuit 70 pushes the system 50 towards a desirable operating point (Vbgr≈1.22V). Once the system 50 has started working such that regulation has started, the start-up circuit 70 automatically shuts off by detecting the level of the regulator output voltage (Vout). Compensation also has been implemented in order to achieve stability as well as to obtain a higher UGB. As a result of this design, the system 50 is able to provide fast transient response during load regulation.
Referring to
The first stage 102 comprises an input differential section 110, shown in this embodiment as an input differential pair. The input differential section 110 comprises a first input differential section transistor 112 and a second input differential section transistor 114. The first and second input differential section transistors 112, 114 in this embodiment are both PMOS transistors with their sources connected together. The gate of the first input differential section transistor 112 comprises the inverted input 26 of the op amp 30 and the gate of the second input differential section transistor 114 comprises the non-inverted input 28 of the op amp 30.
The first stage 102 also comprises a load section 120, shown in this embodiment as a load pair including first and second load section transistors 122, 123. The first and second load section transistors 122, 124 in this embodiment are both NMOS transistors with the sources connected together and to common ground (Vss). The gate and drain of the first load section transistor 122 are connected to the drain of the first input differential section transistor 112, and the gate of the first load section transistor 122 is connected to the gate of the second load section transistor 124. The drain of the second load section transistor 124 is connected to the drain of the second input differential section transistor 114.
The first stage 102 also has a tail current source section 126, shown in this embodiment as a tail current source transistor 128 for the input differential pair of the input differential section 110. The tail current source transistor 128 in this embodiment is a PMOS transistor having a drain connected to the sources of the first and second input differential section transistors 112, 114 of the input differential pair. The source of the tail current source transistor 128 is connected to the supply voltage (Vdd) 42.
The second stage 104 of the op amp 30 comprises a first second-stage transistor 130 and a second second-stage transistor 132. The first second-stage transistor 130 in this embodiment is a PMOS transistor, and the second second-stage transistor 132 in this embodiment is a NMOS transistor. The drains of the first and second second-stage transistors 130, 132 are connected together. The source of the first second-stage transistor 130 is connected to the supply voltage (Vdd) 42, and the source of the second second-stage transistor 132 is connected to the common ground (Vss) 24. The output voltage (Vdriver) 32 is derived at a node between the drains of the first and second second-stage transistors 130, 132. The gate of the first second-stage transistor 130 is connected to the gate of the tail current source transistor 128. The gate of the second second-stage transistor 132 is connected to the drain of the second input differential section transistor 114 of the input differential pair and the drain of the second load section transistor 124 of the load section 120.
The current reference stage 106 of the op amp 30 comprises the first input differential section transistor 112 of the input differential section 110, the first load section transistor 122 of the load section 120, the tail current source transistor 128 of the tail current source section 126, a first current reference stage transistor 140, a second current reference stage transistor 142, and a current reference stage resistor 144. In the embodiment shown, the first current reference stage transistor 140 is a NMOS transistor and the second current reference stage transistor 142 is a PMOS transistor. The drain of the first current reference stage transistor 140 is connected to the drain and gate of the second current reference stage transistor 142; the gate of the first current reference stage transistor 140 is connected to the drain and gate of the first load section transistor 122 and the drain of the first input differential section transistor 112; and the source of the first current reference stage transistor 140 is connected to one end of the current reference stage resistor 144, with the other end of the current reference stage resistor 144 connected to the common ground (Vss) 24. The drain and gate of the second current reference stage transistor 142, in addition to being connected to the drain of the first current reference stage transistor 140, are connected to the gate of the first second-stage transistor 130 and the gate of the tail current source transistor 128. The source of the second current reference stage transistor 142 is connected to the supply voltage (Vdd) 42.
The op amp 30 is a two stage operational amplifier in which self-current biasing is implemented to save bias-current. The self-bias operational amplifier is arranged with the current reference structure with stabilization of transconductance (Gm) or constant Gm for all transistors. It will be appreciated that the elements of the first stage 102 are shared with the current reference stage 106 to save bias current. In this embodiment shown, the first load section transistor 122 and the tail current source transistor 128 are used in both the first stage 102 and the current reference stage 106. Such a configuration contributes to limit bias current. The tail current source transistor 128, the first load section transistor 122, the first current reference stage transistor 140, the second current reference stage transistor 142, and the current reference stage resistor 144 form a ΔVgs/R current reference circuit. The current flowing through the tail current source transistor 128 is I=ΔVgs/R, where ΔVgs is the voltage difference across current reference stage resistor 144. A ΔVgs voltage difference is created across the current reference stage resistor 144 because the size of the first current reference stage transistor 140 is “n” times the size of the first load section transistor 122. Self-biasing eliminates the need of a separate current reference circuit to bias the amplifier or very large area resistance used in place of the tail current source transistor 128.
Referring to
A comparator 160 has a non-inverted input connected to a node between the source of the second diode connected transistor 156 and the drain of the third diode connected transistor 158, and a voltage (Vdd/3) 164 is provided to the non-inverting input of the comparator 160. An inverting input of the comparator 160 receives the output voltage (Vout) 44. A capacitor 170 is connected between an output of the comparator 160 and the supply voltage Vdd 42. In one embodiment, the capacitor 170 is a PMOS capacitor. The capacitor 170 pulls up the output of the comparator 160 when the supply voltage (Vdd) 42 ramps up during start-up. The output of the comparator 160 also is connected to an input of a first inverter 172, and the output of the first inverter 172 is connected to an input of a second inverter 174. The output of the second inverter 174 is connected to a gate of a first start-up circuit transistor 190.
The output of the second inverter 174 also is connected to gates of second and third start-up circuit transistors 180, 182. The gates of the second and third start-up circuit transistors 180, 182 are connected together and sources of the second and third start-up circuit transistors 180, 182 are connected to the common ground (Vss). Each of the transistors 180, 182 also has a bulk or body connected to its source. The drain of the second start-up transistor 180 is connected to the inverted input 26 of the op amp 30 (see
As mentioned above, the first start-up circuit transistor 190 has a gate connected to the output of the second inverter 174; further, the supply voltage (Vdd) 42 is provided to the drain of first start-up circuit transistor 190, the driver voltage (Vdriver) 32 is provided to the source, and the bulk or body of the first start-up circuit transistor 190 is connected to the common ground (Vss).
A fourth start-up circuit transistor 192 has a gate connected to the output of the second inverter 174 and receives the comparator voltage (Vcomp) 188, a source connected to the inverted input of the comparator 160 and the output voltage (Vout) 44, and a drain that receives the operating voltage (Vbgr) 22.
As will be apparent to those of skill in the art, the transistors may take different forms than shown. For example, the transistors 154, 156, 158, 180, 182, 190 are enhancement mode NMOS transistors, and transistor 192 is an enhancement mode PMOS transistor, but these transistors could be formed as PMOS and NMOS respectively. In this embodiment, the voltage divider 152 comprises transistors instead of poly resistors to allow for a low area implementation.
It will be appreciated that except for the comparator voltage (Vcomp) 188, all other voltages (Vout 44, Vdriver 32, operational amplifier inverted input 26, operational amplifier non-inverted input 28, and Vbgr 22) are present in the system 10 shown in
In one embodiment, during start-up, the inverted and non-inverted inputs 26, 28 are pulled towards the common ground (Vss) so that the self-biased current reference 76 can start. Accordingly, the fourth start-up circuit transistor 192 cuts the feedback path from Vout 44 to the operating voltage of the bandgap voltage reference (Vbgr) 22 such that during start-up, the bandgap circuit 20 does not draw any current and the output voltage Vout 44 can rise towards the desired voltage level.
Referring to
In operation, at start up, the supply voltage (Vdd) ramps up from 0V, node 210 (
One embodiment of the bandgap voltage reference and voltage regulator system 50 has been simulated with Vdd variations and load current variations from 2.7V to 3.6V, and from 10 μA to 1 mA, respectively. The target Vbgr value is 1.22V across a temperature range of −40° C. to 125° C. The simulated quiescent current consumption is 10.5 μA at 3.3V.
In the simulation Vbgr was typically 1.222V with a minimum of 1.204V and a maximum of 1.236V. The quiescent current was typically 10.92 μA with a minimum of 10.65 μA and a maximum 13.17 μA. The phase margin in the simulation was a minimum of 40 degrees. The unity gain bandwidth (UGB) at no load current was 5 MHz and at max load current of 1 mA was 66 MHz. The graph 220 shows settling behaviour of the bandgap voltage reference and voltage regulator system 50 with supply ramp up. The dashed circle 226 identifies a portion of the Vout curve 224 shown in more detail in
Referring to
As industry demands ever decreasing system power supplies and space limited footprints and the demand for scaling down of integrated circuits is being realized, efficient circuit designs conserving die space and power consumption are sought. The bandgap voltage reference and voltage regulator system described above comprises a bandgap voltage reference circuit and a voltage regulator circuit that share a single, common amplifier. The bandgap voltage reference and voltage regulator system is a self-starting bandgap-cum-regulator circuit having a single amplifier for the gain stage of the bandgap reference and an error amplifier for the driver stage of the voltage regulator. It will be appreciated that the system may comprise a linear or switching regulator, however, a linear regulator is frequently chosen for low current consumption and due to its simplicity. By sharing the amplifier, the overall area and overall quiescent current of the circuit is reduced. By reducing the overall quiescent current consumption and circuit foot print, overall die-size may be reduced and circuit efficiency improved. For example, in embodiments the quiescent current is in the range of 10 μA. As no resister network is used to bias the driver transistor stage, no bias current is required to flow through such a resistor divider or network. Thus, less die space is required. The system and circuits disclosed regulate from no load to full load conditions, with a maximum of 1 mA current capability. Accordingly, the circuit is suited for low power applications, and is particularly useful in supplying modules, such as a real time clock (RTC) and the like, which have low power budgets because these modules are generally run on a coin cell, super capacitor, or the like.
As a common amplifier is shared between the bandgap voltage reference and the voltage regulator the overall offset voltage is low and limited to the common amplifier. Offset voltage is generated, for example due to input pair mismatch of the amplifier and is limited in the circuit disclosed to the input pair of the amplifier rather than the offset of the input pair in a gain-stage of a separate bandgap voltage reference and the offset of the input pair in an error amplifier for the driver stage of the voltage regulator of a separate voltage regulator. Simulation and silicon results show that the bandgap voltage reference and voltage regulator system and circuit in accordance with an embodiment of the invention has less than ˜2% variation across process, temperature, and supply voltage variation.
It will be appreciated that the circuit can be implemented in any number of ways including industry standard digital complementary metal-oxide semiconductor (CMOS) and/or BiCMOS technology.
Embodiments of the invention have been described herein, including the best mode known to the inventors for carrying out the invention. Variations of those preferred embodiments may become apparent to those of ordinary skill in the art upon reading the foregoing description. The inventors expect skilled artisans to employ such variations as appropriate, and the inventors intend for the invention to be practiced otherwise than as specifically described herein. Accordingly, this invention includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by the applicable law. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed by the invention unless otherwise indicated herein or otherwise clearly contradicted by context.
