Not applicable.
Not applicable.
This invention is in the field of voltage and current reference circuits as used in integrated circuits. Embodiments are directed to curvature compensation in reference circuits of the bandgap reference type.
The powerful computational and operation functionality provided by modern integrated circuits has enabled the more widespread distribution of computing power in larger-scale systems. One example of such distributed electronic functionality is the so-called “Internet of Things” (IoT) contemplates the widespread deployment of electronic devices as sensors and controllers, with networked communications among those devices. Modern smartphones and wearables also deploy computational and operational functionality into a large number of distributed nodes; implantable medical devices constitute another type of distributed functionality. Many of these applications necessitate the use of batteries or energy scavenging devices to power the integrated circuits. As such, many modern integrated circuits are called upon to be “power-aware”, designed to consume minimal power during operation and standby.
Voltage and current reference circuits are important functions in a wide range of modern analog, digital, and mixed-signal integrated circuits, in order to optimize the performance of such circuits as operational amplifiers, comparators, analog-to-digital and digital-to-analog converters, oscillators, phase-locked loops and other clock circuits, and the like. This optimization is especially important for power-aware applications in which power consumption can be a dominating factor in circuit and system design. As well known in the art, voltage and current reference circuits ideally generate their reference levels in a manner that are stable over variations in process parameters, power supply voltage levels, and operating temperature.
According to this construction, the output voltage AMPOUT from amplifier 15 is based on one parameter that varies in a manner complementary to absolute temperature (CTAT) combined with another parameter that varies proportionally with temperature (PTAT). The CTAT parameter in this circuit is the base-emitter voltage of transistor 8a, and the PTAT parameter is the difference in the base-emitter voltages of transistors 8a, 8b, which is reflected as the voltage drop across resistor 11. The sum of these two voltages is thus constant over variations in temperature, at least to a first approximation, and appears at the drain of transistor 6p as output voltage VBG. This output voltage VBG is typically at about the bandgap voltage of the semiconductor (e.g., 1.2 volts for silicon), and as such reference circuit 10 is thus commonly referred to in the art as a “bandgap reference circuit”. Additional transistors (not shown) are typically mirrored with PMOS transistor 6p to establish and provide output currents that are similarly stable over variations in temperature. Reference circuit 10 can be made “self-biased” by biasing amplifier 15 with a copy of the current conducted by transistor 6p, in which case the circuit will be relatively insensitive to variations in the Vdd power supply voltage.
However, the base-emitter voltages of bipolar transistors 8a, 8b are not exactly linear over temperature because of non-linear temperature behavior in the bipolar junction transistor (BJT) saturation current. The combination of the CTAT base-emitter voltage with the PTAT difference in base-emitter voltages is thus often insufficient to attain the desired temperature stability of the reference voltage. This variation of base-emitter voltage (Vbe) over temperature is generally referred to as the “curvature” of Vbe, referring to the curve in the Vbe vs. temperature characteristic from the linearly CTAT ideal.
Another conventional approach for curvature compensation involves the introduction of a non-linear bias current to cancel out the non-linearity of Vbe over temperature. Filanovsky et al., “BiCMOS Cascaded Bandgap Voltage Reference”, IEEE 39th Midwest symposium on Circuits and Systems, Vol. 2 (IEEE, 1996), pp.943-946describes this approach as carried out by a translinear current polynomial circuit to produce a current that is PTAT to the third degree (i.e., proportional to T3), and a current that is PTAT to the fourth degree. These currents are added with the collector current in the reference circuit to compensate for non-linearities. However, this approach necessitates the formation of cascaded bipolar transistors, and thus not conducive to implementation in CMOS technologies (in which the collectors of parasitic bipolar devices are all connected to the substrate).
Another approach to curvature compensation is described in U.S. Pat. No. 6,255,807, incorporated herein by reference. According to this technique, an additional amplifier gain stage is added to the reference circuit, and adds non-linearity into the feedback loop. While this technique provides good curvature compensation, the additional amplifier stage requires significant chip area to implement, and consumes additional power that renders it less than optimal for power-aware applications.
By way of further background, U.S. Pat. No. 9,104,217, issued Aug. 11, 2015, commonly assigned herewith and incorporated herein by reference, describes a reference circuit with curvature compensation implemented by way of a translinear circuit that draws a non-linear current from the bipolar collector currents, and that can be realized by MOS transistors.
Disclosed embodiments provide an efficient circuit to implement curvature compensation for a bandgap reference circuit implemented in complementary metal-oxide-semiconductor (CMOS) technology.
Disclosed embodiments provide such a circuit that is robust to variations in manufacturing process parameters.
Disclosed embodiments provide such a circuit that consumes relatively little power and as such is suitable for use in power-aware applications.
Disclosed embodiments provide such a circuit that accomplishes curvature correction with excellent power supply rejection and temperature drift stability.
Other objects and advantages of the disclosed embodiments will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
According to certain embodiments, a reference circuit with curvature compensation can be implemented by nested current mirrors. The first current mirror includes a first resistor that biases the gate-to-source voltage of a current control transistor in the bandgap reference core differently from that of a mirror transistor. The current conducted by the mirror transistor is forwarded to a reference transistor in the second current mirror, which is biased to have a gate-to-source voltage different from that of a second mirror transistor. This second mirror transistor draws a translinear current from the bandgap reference core, which varies non-linearly with temperature to provide the desired curvature compensation.
The one or more embodiments described in this specification are implemented into a bandgap reference circuit realized by way of a complementary metal-oxide-semiconductor (CMOS) technology, as it is contemplated that such implementation is particularly advantageous in that context. However, it is also contemplated that concepts of this invention may be beneficially applied to other applications, for example integrated circuits constructed by way of a bipolar-CMOS (BiCMOS) technology. Accordingly, it is to be understood that the following description is provided by way of example only, and is not intended to limit the true scope of this invention as claimed.
According to this embodiment, reference circuit 20 includes a conventional bandgap reference circuit core that is generally similar to the circuits described above relative to
Amplifier 35 in this embodiment is a differential operational transconductance amplifier (OTA), and has an input coupled to each of the two circuit branches. The positive (non-inverting) input of amplifier 35 is connected to the emitter of transistor 28a in one circuit branch, and the negative (inverting) input of amplifier 35 is connected to the emitter of transistors 28b via polysilicon resistor 31 in the other branch. Polysilicon resistors 29a, 29b couple these amplifier input nodes in the respective circuit branches together at a node that will be referred to in this specification as common node CN, as shown in
P-channel MOS (PMOS) transistor 26p has its drain coupled to common node CN via polysilicon resistor 27. The gate of transistor 26p receives the level AMPOUT from the output of amplifier 35, and the source of transistor 26p is biased to the Vdd power supply through polysilicon resistor 30 according to this embodiment. Transistor 26p thus controls the sum of the current in the two circuit branches (i.e., conducted by transistors 28a, 28b) in response to the voltage AMPOUT produced by amplifier 35. As known in the art and as shown in
In reference circuit 20 according to this embodiment, compensation for non-linear variations in the base-emitter voltages of transistors 28a, 28b is implemented by way of nested current mirrors 25, 35. Current mirror 25 operates to mirror the current IC conducted by transistor 26p, that current IC being the sum of the currents in the bipolar transistor branches, to produce mirror current IX conducted by mirror transistor 32p. In the embodiment of
Current IX is communicated to second current mirror 35 in this embodiment. Specifically, the drain of PMOS transistor 26p is connected to the drain and gate of re-channel MOS (NMOS) transistor 34a; the source of NMOS transistor 34a is coupled to ground (i.e., the Vss voltage) by polysilicon resistor 36. Current mirror 35 also includes mirror transistor 34b, which is an NMOS transistor with its source at Vss, its gate connected to the gate and drain of transistor 34a, and its drain connected to common node CN. If desired, the width-to-length ratio of NMOS mirror transistor 34b may be a multiple of that of transistor 34a. The current Ix conducted by transistor 34a is thus mirrored as current IPTATn conducted by transistor 34b, at a multiple corresponding to the relative width-to-length of transistors 34a, 34b. Similarly as in current mirror 25, the gate to source voltage of transistor 34a differs from that of transistor 36a, specifically by the voltage drop across resistor 36. As will be discussed below, this differential in gate-to-source voltages assists in providing curvature compensation for reference circuit 20.
It is contemplated that the particular construction of reference circuit 20 may vary from that described above and illustrated in
The bandgap reference core of reference circuit 20 operates in the conventional manner for self-biased circuits of this type, with the circuit branches of bipolar transistors 28a, 28b dividing the current IC conducted by transistor 26p according to their relative device strengths and series resistances. Amplifier 35 operates to control the voltage AMOUT at the gate of transistor 26p, and thus the level of this current IC. Specifically, as known in the art, the voltage level AMPOUT at the output of amplifier 35 is based on the combination of a CTAT (complementary to absolute temperature) voltage, namely the base-emitter voltage of transistor 28a, and a PTAT (proportionally to absolute temperature) voltage, namely the voltage drop across resistor 31 corresponding to the difference in base-emitter voltages of transistors 28a and 28b. Because these voltages vary over in temperature in opposition with one another, this combination is relatively insensitive to temperature, at least to a first order approximation. However, non-linearity in the variation of bipolar saturation current with temperature is reflected in curvature of the CTAT voltage of base-emitter voltage of transistor 28a from its linear ideal. Nested current mirrors 25, 35 compensate for this curvature, as will now be described.
As described above, resistor 30 in current mirror 25 causes the gate-to-source voltage Vgs of PMOS transistor 26p to differ from that of PMOS mirror transistor 32p. More specifically, the gate-to-source voltage Vgs32 of mirror transistor 32p, in terms of the gate-to-source voltage Vgs26 of current control transistor 26p, is:
Vgs32=Vgs26+IC·R30
where R30 is the resistance of resistor 30, and the current IX conducted by mirror transistor 32p being:)
IX˜m·(Vgs26+(IC·R30)−VT32)2
where m is the scaling ratio (e.g., ratio of the W/L ratios) of mirror transistor 32p relative to transistor 26p, and VT32 is the threshold voltage of transistor 32p. This difference in gate-to-source voltage between transistors 26p and 32p results in distortion in the variation of the mirrored current IX over temperature relative to the temperature variation of current IC on which it is based. This distortion is illustrated in
Current mirror 35 operates in a similar fashion to further distort the temperature behavior in mirrored current IPTATn as compared with mirrored current IX. If the transistor strength (W/L ratio) of transistor 34b is ratioed relative to that of transistor 34a, current IPTATn will be similarly ratioed relative to current IX. As described above, the gate-to-source voltage Vgs34b of mirror transistor 34b differs from the gate-to-source voltage Vgs34a of reference transistor 34a that conducts current IX:
Vgs34b=Vgs34a+IX·R36
where R36 is the resistance of resistor 36 connected between the source of reference transistor 34a and ground in the embodiment of
In any case, the difference in gate-to-source voltage between transistors 34a and 34b distorts the temperature variation of the mirrored current IPTATn over temperature relative to the temperature variation of current Ix, which itself exhibits a distorted temperature variation relative to reference current IC in the bandgap core. As a result, the temperature variation of mirrored current IPTATn is even more distorted from linear than is current IX, as shown by its stronger curvature in the current-temperature plane as shown in
As described above and as shown in
In particular, it is contemplated that improved stability of output bandgap voltage VBG over temperature will be attained by reference circuit 20 according to this embodiment. As known in the art, the curvature in the CTAT current due to base-emitter voltage nonlinearity over temperature typically appears as a parabolic relationship of the output bandgap voltage with temperature. In contrast, it is contemplated that the output bandgap voltage VBG of reference circuit 20, compensated according to this embodiment, will exhibit second order correction behavior over temperature, such as illustrated by way of example in
Variations and alternatives to the implementation of reference circuit shown in
The implementation of curvature correction for a voltage reference circuit according to these embodiments provides important benefits and advantages. One such advantage provided by this approach is its provision of a translinear current mode circuit (e.g., current mirrors 25, 35) into the reference circuit so as to be self-biased. More specifically, no external bias current is required in reference circuit 20 of
In addition, curvature compensation according to these embodiments may be implemented in a simple and efficient manner. Implementation of the additional current mirrors in this arrangement requires a relatively small number of additional transistors and other devices, and as such can be realized efficiently from the standpoint of chip area. This construction also permits application of curvature correction in a wide range of self-biased bandgap reference circuit designs. In addition, variations in transistor parameters or polysilicon sheet resistance in the bandgap circuit core will be tracked in devices in the nested current mirrors, resulting in a reference circuit design that is quite robust over variations in temperature, process parameters, and power supply voltage, with good temperature drift stability. Furthermore, the additional power consumed by the curvature compensation function according to these embodiments is extremely low, enabling this approach to be used in power-aware applications.
While one or more embodiments have been described in this specification, it is of course contemplated that modifications of, and alternatives to, these embodiments, such modifications and alternatives capable of obtaining one or more the advantages and benefits of this invention, will be apparent to those of ordinary skill in the art having reference to this specification and its drawings. It is contemplated that such modifications and alternatives are within the scope of this invention as subsequently claimed herein.
Number | Name | Date | Kind |
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6255807 | Doorenbos et al. | Jul 2001 | B1 |
7808305 | Kim | Oct 2010 | B2 |
9104217 | Arnold | Aug 2015 | B2 |
20130265083 | Lin | Oct 2013 | A1 |
20140077789 | Hu | Mar 2014 | A1 |
20160077540 | Ye | Mar 2016 | A1 |
Entry |
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Filanovsky et al., “BiCMOS Cascaded Bandgap Voltage Reference”, 39th Midwest symposium on Circuits and Systems, vol. 2 (IEEE, 1996), pp. 943-946. |
Tsividis et al., “Accurate Analysis of Temperature Effects in Ic-Vbe Characteristics with Application to Bandgap Reference Sources”, J. Solid State Circ., vol. SC-15, No. 6 (IEEE, 1980), pp. 1076-1084. |
Pertijs et al., “Precision Interface Electronics for a CMOS Smart Temperature Sensor”, 4th IEEE Conference on Sensors (IEEE, 2005), pp. 943-946. |
U.S. Appl. No. 14/854,600, filed Sep. 15, 2015. |
Sansen, “Bandgap and current reference circuits”, lecture handout (KULeuven, 2005), pp. 161-169, 1610-1653, available at http://iroi.seu.edu.cn/teachers/chym/analog/16.pdf. |