Patent Grant
9110486
1. Field
This disclosure relates generally to a bandgap reference circuit, and more specifically, to a bandgap reference circuit with a startup circuit.
2. Related Art
Bandgap reference circuits are commonly used in integrated circuits to provide a temperature independent bandgap voltage. However, bandgap reference circuits may be unpredictable upon power up. Once powered up, bandgap reference circuits operate at a stable operating point to provide the desired bandgap voltage. However, bandgap reference circuits also typically have a second stable operating point when the current is close to zero which provides an undesirable bandgap voltage (i.e. an erroneous bandgap voltage). Therefore, many bandgap reference circuits include a startup circuit which forces current to start flowing during power-up in order to prevent stabilizing at the undesirable bandgap voltage. However, in order to ensure proper operation of the bandgap reference circuit, the startup circuit needs to be disabled appropriately over a wide range of supply voltages.
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
Systems which use a bandgap reference circuit to provide a reliable reference voltage may be powered by a supply voltage, VDD, whose full operating value may be anywhere within a range of full operating values. However, a bandgap reference circuit designed to operate properly assuming that the supply voltage ramps up to the full operating value at the bottom end of the range may not allow for proper operation when the supply voltage ramps up to the top end of the range. Likewise, a bandgap reference circuit designed to operate properly assuming that the supply voltage ramps up to the full operating value at the top end of the range may not allow for proper operation when the supply voltage ramps up to only the bottom end of the range. Therefore, in one embodiment, a bandgap reference circuit is provided which is capable of producing the desired stable reference voltage over a large range of allowable full operating voltages of VDD. In one embodiment, a startup circuit is used to control current to the bandgap reference circuit during the initial ramping up of VDD, but is then disabled after VDD reaches a particular voltage level. This enabling/disabling of the startup circuit may be controlled by one or more series-connected inverters. In one embodiment, the body of a transistor in each of the inverters is biased by a voltage which is a fraction of VDD and varies with VDD. This biasing allows the trip point of each inverter of the one or more inverters to be appropriately varied as VDD varies so as to appropriately enable/disable the startup circuit, regardless of the full operating value reached by VDD. In this manner, the bandgap reference circuit may stabilize at the desired reference voltage over the entire range of full operating values of VDD.
Startup circuit 12 includes a turnoff circuit 37, an N-channel transistor 38, and body bias circuits 40, 42, and 44. Turnoff circuit 37 includes inverters 32, 34, and 36. Inverter 32 has a signal input coupled to node 30 and a signal output coupled to node 48. Inverter 32 is coupled between VDD and ground and is also coupled to body bias circuit 40. Inverter 34 has a signal input coupled to node 48 and a signal output coupled to node 50. Inverter 34 is coupled between VDD and ground and is also coupled to body bias circuit 42. Inverter 36 has a signal input coupled to node 50 and a signal output coupled to a control electrode (i.e. gate) of transistor 38. Inverter 36 is coupled between VDD and ground and is also coupled to body bias circuit 44. A first current electrode of transistor 38 is coupled to the control electrodes of each of transistors 46, 16, and 14, and a second current electrode of transistor 38 is coupled to ground.
During normal operation, upon reaching a stable operating point, bandgap reference circuit 10 provides a desired reference voltage at Vout 30. Opamp 18 attempts to maintain equal voltages at circuit nodes 15 and 17. In doing so, the output of opamp 18, which detects a voltage differential between nodes 15 and 17, control the gates of transistors 14 and 16 to provide the appropriate currents through transistors 14 and 16 to nodes 15 and 17. These currents flow through resistor 28 of branch 21, resistor 22 and bipolar transistor 20 of branch 23, through resistor 26 of branch 25, and through bipolar transistor 24 of branch 27. During operation at the desirable stable operating point in which opamp 18 maintains equal voltages at 15 and 17, the output of opamp 18 remains stable such that Vout 30 reliably outputs the desired reference voltage. The physical characteristics of the circuit elements within reference generator 11, such as the bandgap of bipolar transistors 20 and 24, determine the value of the reference voltage upon stable operation. In one embodiment, the circuit elements of reference generator 11 are selected such that the value of the desired reference voltage at the stable operating point is 0.95V.
However, as described above, bandgap reference circuit 10 has a second (undesirable) stable operating point which produces an undesired reference voltage which is less than the desired value of 0.95V. For example, this may occur during power up when sufficient voltage has not yet been developed at nodes 15 and 17 such that current only flows through resistors 28 and 26 of branches 21 and 25 and not through branches 23 and 27. Therefore, at this point, no current flows through bipolar transistors 20 and 24. In this case, opamp 18 also attempts to maintain equal voltage at nodes 15 and 17, however, in doing so, the output of opamp 18 remains at an undesirable stable voltage which is lower than the desired stable voltage. This in turn results in Vout being reliably held at a lower voltage value than the desired voltage value. In one embodiment, the undesirable stable value of the reference voltage is 0.7V. This lower undesirable stable value will result in incorrect or unstable of operation of those circuits which receive Vout.
Therefore, during power up, startup circuit 12 may be enabled in which transistor 38 is turned on (by the output of inverter 36), thus pulling the gates of transistors 14 and 16 low. In this manner, transistors 14 and 16 are fully turned on in order to develop sufficient voltage at nodes 15 and 17 to inject current into bipolar transistors 20 and 24. Therefore, when startup circuit 12 is enabled during this first portion of starting up, it controls the current provided from VDD to nodes 15 and 17. However, once sufficient voltage is developed at nodes 15 and 17, startup circuit 12 is disabled (in which transistor 38 is turned off by the output of inverter 36) such that opamp 18 controls transistors 14 and 16 while startup circuit 12 is isolated from transistors 14 and 16. The disabling (or turning off) of transistor 38, and thus the disabling of startup circuit 12, is controlled by inverters 32, 34, and 36 which are coupled between node 30 and the gate of transistor 38. When Vout 30 has hit a level which has surpassed the lower undesirable reference voltage at the second stable operating point (such as 0.7 in the current example), startup circuit 12 may be disabled so that opamp 18 may take control of reaching the desired stable operating point. Therefore, the trip point (i.e. the point at which an inverter changes states) of inverter 32 should be at a level which allows the output of inverter 32 to be low when Vout reaches 0.7 or greater. Similarly, the trip point of inverter 34 should be at a level which allows the output of inverter 34 to be high, and the trip point of inverter 36 should be at a level which allows the output of inverter 36 to be high. In this manner, when the output of inverter 36 goes to its high state, transistor 38 is turned off, thus turning off startup circuit 12 and isolating startup circuit 12 from bandgap generator 11. When startup circuit 12 is disabled, it no longer controls the current provided from VDD to nodes 15 and 17. Instead, the current is controlled by opamp 18. Therefore, startup circuit 12 may initially be activated to prevent bandgap generator 11 from stabilizing at the undesired reference voltage, and upon Vout passing the undesirable reference voltage, startup circuit 12 is deactivated, in which, upon deactivation, the voltages at nodes 15 and 17 are sufficient such that bandgap generator 11 is able to stabilize at the desired reference voltage.
Furthermore, once Vout reaches the desired reference voltage, startup circuit 12 should be maintained deactivated. Therefore, while the trip point of inverter 32 needs to be greater than 0.7 to allow sufficient voltage to develop on nodes 15 and 17, the trip point of inverter needs to be less than the desired reference voltage. If the trip point of inverter 32 is greater than the desired reference voltage, the startup circuit 12 may be reactivated while opamp 18 is stable at the desired reference voltage.
Therefore, it is desirable to set the trip point of inverter 32 to be between the undesired stable reference voltage and the desired stable reference voltage. However, during powerup, the supply voltage, VDD, ramps from 0V to its final operating voltage. However, this final operating voltage may vary in value from system to system. In one embodiment, the final operating voltage may vary between 1.25V and 1.65V. However, in an inverter, such as inverter 32, the P/N ratio may be such that a trip voltage of between 0.7V and 0.95V cannot be achieved at VDD of both 1.25V and 1.65V. For example, the devices of inverter 32 may be sized such that the P/N ratio of the devices at a VDD of 1.25V allows the trip point to appropriately remain between 0.7V and 0.95V; however, these same device sizes will not also allow for an appropriate trip point in the case of VDD being 1.65V. Similarly, the devices of inverter 32 may be sized such that the P/N ratio of the devices at a VDD of 1.65V allows the trip point to be appropriately remain between 0.7V and 0.95V; however, these same device sizes will not also allow for an appropriate trip point when VDD is only 1.25V. Furthermore, from system to system, it is not known a priori to which voltage value within the range of 1.25V and 1.65V that VDD will reach.
As an example, it will be assumed, due to margin considerations, that the trip point of inverter 32 should be between 0.75V and 0.9V (which is more conservative than the exemplary range described above of 0.7V and 0.95V in order to account for the margin considerations). However, as VDD changes, the threshold voltage (VT) of a transistor also changes. Therefore, as VDD changes, the trip point of inverter 32 (which is determined by the threshold voltage) changes. In order to ensure proper operation, though, the trip point of inverter 32 needs to remain between 0.75V and 0.9V. That is, as described above, for proper operation, the trip point of inverter 32 needs to remain between 0.75V and 0.9V regardless of whether VDD ramps to only 1.25V or to 1.65V (or to any value in between). In one embodiment, startup circuit 12 includes a body bias circuit 40 (which may also be referred to as a trip point set circuit) which applies a voltage that is dependent on VDD to the body of the N-channel transistor of inverter 32. This biasing increases as VDD increases which results in lowering the VT of the N-channel transistor as VDD increases. Therefore, as VDD increases, the trip point of inverter 32 also decreases. In this manner, as VDD changes, the trip point of inverter 32 is maintained within the necessary range to ensure proper operation of startup circuit 12 (by properly controlling transistor 38).
In the illustrated example, turnoff circuit 37 includes an odd number of series-connected inverters, including inverters 32, 34, and 36, that are used to control the enabling/disabling of transistor 38 and thus of startup circuit 12. Therefore, inverter 34 may also have a corresponding body bias circuit 42 and inverter 36 may also have a corresponding body bias circuit 44, as will be described below. The body bias circuits (which may also be referred to as trip point set circuits) are connected to bias the body of one of the devices of the corresponding inverter in order to affect the threshold voltage (VT) of that device based on the voltage of VDD, and thus the trip point of the corresponding inverter based on the voltage of VDD. That is, the body bias changes as VDD changes. In one embodiment, body bias circuits 40, 42, and 44 may collectively be referred to as a body bias circuit of startup circuit 12. Furthermore, in the illustrated embodiment, 3 series-connected inverters between node 30 and the gate of transistor 38 are used to control the turning off/on of transistor 38. However, in alternate embodiments, any odd number of inverters may be used (each with a corresponding body bias circuit), including only one inverter, such as only inverter 32 with body bias circuit 40 (in this case, the output of inverter 32 would be coupled to the control electrode of transistor 38). By controlling the turning on/off of transistor 38, turnoff circuit 37 controls activating/deactivating, respectively, of startup circuit 12.
Referring to
In operation of either embodiment of
Referring to
In operation, body bias circuit 42 provides a voltage to the body of transistor 66 based on VDD. That is, the voltage on the body of transistor 66 is a fraction of VDD. In one embodiment, the voltage on the body of transistor 66 is in a range of 10 to 90 percent of VDD, or, alternatively, in range of 50 to 90 percent of VDD. Body bias circuit 42 biases the body of transistor 66 to be lower than VDD during startup operation of bandgap reference circuit 10. That is, body bias circuit 42 results in a voltage differential between the body and source of transistor 66. Furthermore, the body of transistor 68 is connected to the source of transistor 68. Therefore, body bias circuit 42 biases the body of transistor 68 to be different in voltage than the body of transistor 66. By applying a fraction of VDD to the body of transistor 66, the biasing of the body of transistor 66 decreases as VDD increases. This results in reducing the VT of transistor 66 as VDD increases, thus raising the trip point of inverter 34 as VDD increases. This ensures that the trip point of inverter 34 is maintained in the desirable range which is compatible with the output of inverter 32 to appropriately control inverter 36 so that transistor 38 can be enabled/disabled appropriately. Therefore, during startup, as VDD ramps up from 0V to its final full operating voltage, the trip point of inverter 36 changes as VDD changes. The values of resistors 70 and 72 can be selected such that the voltage at node 71 (and thus on the body of transistor 66) is at the appropriate fraction of VDD, such as in a range of 10 to 90 percent of VDD, or alternatively, in a range of 50 to 90 percent of VDD. Therefore, note that a variety of different circuit configurations may be used. Furthermore, as described in reference to
Alternate embodiments of body bias circuits 40 and 42 can have different combinations of resistive elements and diodes to achieve the proper biasing to ensure that the trip point of the corresponding inverter varies appropriately with VDD in order to stay within the allowable range of trip points for proper disabling/enabling of startup circuit 12. Furthermore, the resistive elements and diodes can each be implemented in a variety of different ways. For example, the resistive elements may be implemented as resistors. Also, a MOSFET can be used as a resistive element or a diode, based on how it is configured. Also, in alternate embodiments, only one inverter, such as inverter 32, has a corresponding body bias circuit.
In the embodiments of
By now it should be appreciated that there has been provided a bandgap reference circuit which is capable of producing the desired stable reference voltage over a large range of allowable full operating voltages of VDD. By biasing the body of a transistor of an inverter in the turnoff circuit (which operates to enable/disable the startup circuit) with a voltage that is a fraction of VDD and that varies with VDD, the trip point of the inverter can be ensured to remain within an allowable range of trip point voltages. This ensures the proper turning on and off of the startup circuit so as to prevent the bandgap circuit from stabilizing at the undesirable stable value, regardless of the final operating voltage of VDD.
Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.
Although the invention has been described with respect to specific conductivity types or polarity of potentials, skilled artisans appreciate that conductivity types and polarities of potentials may be reversed.
Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, turnoff circuit 37 may include any odd number of inverters, and each inverter may have a corresponding body bias circuit. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
The term “coupled,” as used herein, is not intended to be limited to a direct coupling or a mechanical coupling.
Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
The following are various embodiments of the present invention.
Item 1 includes a band gap reference circuit including a band gap reference generator including an output for providing a reference voltage; a startup circuit for controlling current provided to the band gap reference generator when activated, wherein the startup circuit includes: a turnoff circuit having an output to deactivate the startup circuit to not control current to the band gap reference generator based on a voltage of the output of the band gap reference generator, the turnoff circuit including an inverter having a first transistor of a first conductivity type in series with a second transistor of a second conductivity type opposite the first conductivity type; and a body bias circuit connected to a body of the first transistor to provide a voltage differential between the body of the first transistor and a source terminal of the first transistor. Item 2 includes the circuit of item 1 wherein the first transistor is an N-channel transistor having its source coupled to a ground terminal, wherein the body bias circuit is configured to bias the body of the first transistor to be higher than ground during a startup operation of the band gap reference circuit. Item 3 includes the circuit of item 1 wherein the first transistor is a P-channel transistor having its source coupled to a power supply voltage terminal, wherein the body bias circuit is configured to bias the body of the first transistor to be lower than the power supply voltage terminal during a startup operation of the band gap reference circuit. Item 4 includes the circuit of item 1 wherein the body bias circuit biases the body of the first transistor to be different in voltage than a body of the second transistor. Item 5 includes the circuit of item 1 wherein the body bias circuit includes a voltage divider coupled between a power supply voltage terminal and a ground terminal, the voltage divider includes a divided voltage node coupled to the body of the first transistor. Item 6 includes the circuit of item 5 wherein the voltage divider includes a diode coupled between the divided voltage node and one of the power supply terminal and ground terminal. Item 7 includes the circuit of item 1 wherein a body of the second transistor is connected to a source of the second transistor. Item 8 includes the circuit of item 1 wherein the first transistor and a second transistor are coupled in series between a power supply terminal and a ground terminal, wherein the body bias circuit is configured to bias the body of the first transistor to be in a range of 10-90% of a voltage of the power supply terminal. Item 9 includes the circuit of item 1 wherein the first transistor and a second transistor are coupled in series between a power supply terminal and a ground terminal, wherein the body bias circuit is configured to bias the body of the first transistor to be in a range of 10-50% of the voltage of the power supply terminal. Item 10 includes the circuit of item 1 wherein the turnoff circuit includes a second inverter and a third inverter connected in series with the inverter, wherein an output of a last of the inverter, the second inverter, and the third inverter connected in the series is connected to the output of the turnoff circuit. Item 11 includes the circuit of item 10 wherein the body bias circuit is connected to a body of a third transistor of the second inverter to provide a voltage differential between the body of the third transistor and a source terminal of the third transistor. Item 12 includes the circuit of item 11 wherein the first transistor is an N-channel transistor and the third transistor is a P-channel transistor. Item 13 includes the circuit of item 12 wherein a body of the second transistor is connected to a source of the second transistor and a body of a fourth transistor of the second inverter is connected to a source of the fourth transistor, the fourth transistor is coupled in series with the third transistor. Item 14 includes the circuit of item 1 wherein the startup circuit, when activated, controls current provided to the band gap reference generator from a power supply terminal; the startup circuit is configured for the band gap reference circuit to be operable over a range of power supply terminal voltages of the power supply terminal; and for each power supply terminal voltage within the range of power supply terminal voltages, the band gap reference generator is configured to provide at its output a stable reference voltage at a first voltage and at a second voltage greater than the first voltage, wherein the body bias circuit is configured to bias the body of the first transistor such that the startup circuit remains activated during a startup of the band gap reference circuit as the voltage of the output of the band gap reference generator rises through the first voltage and the start up circuit deactivates after the voltage of the output of the band gap reference generator is greater than the first voltage and remains deactivated as the voltage of the output reaches the second voltage. Item 15 includes the circuit of item 14 wherein a higher voltage of the range is 25 percent greater than a lower voltage of the range.
Item 16 includes a method of operating a band gap reference circuit including starting up the band gap reference circuit by providing current from a power supply to the band gap reference circuit, wherein during a first portion of the starting up, a startup circuit of the band gap reference circuit controls current from the power supply and an output of a band gap reference generator of the band gap reference circuit provides a voltage at its output; wherein the startup circuit does not control the current provided from the power supply after the voltage of the output rises above a first level during the starting up; during the starting up, providing a voltage differential between a body of a transistor of an inverter of the startup circuit and a source terminal of the transistor, wherein the inverter has an output used to deactivate the startup circuit from controlling the current from the power supply; and after the starting up, proving a reference voltage at the output. Item 17 includes the method of item 16 wherein the transistor is an N-channel transistor. Item 18 includes the method of item 17 wherein the inverter includes a second transistor connected in series with the transistor and being of an opposite conductivity type to the transistor, the transistor and the second transistor are coupled in series between a power supply terminal and ground, wherein a body of the second transistor is connected to a source of the second transistor. Item 19 includes the method of item 18 wherein during the starting up, the body of the transistor is biased to be in a range of 10-50% of a voltage of the power supply terminal. Item 20 includes the method of item 16 wherein the startup circuit includes a second inverter and a third inverter, wherein the inverter, the second inverter, and the third inverter are connected in series, wherein an input of a inverter located at the front of the series is coupled to the output of the band gap reference circuit.
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