The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
If the base current is neglected, the emitter-base voltage VEB of a forward active operation diode can be expressed as:
Wherein k is Boltzmannis constant (1.38×10−23 J/K), q is the electronic charge (1.6×10−29 C), T is temperature, Ic is the collator current, and IS is the saturation current.
When the input voltages V1 and V2 of the operational amplifier OP are matched and the size of the transistor Q2 is N times that of the transistor Q1, the emitter-base voltage difference between the transistors Q1 and Q2, ΔVEB, becomes:
Wherein VEB1 is the emitter-base voltage of the transistor Q1, and VEB2 is the emitter-base voltage of the transistor Q2.
Because the input voltages V1 and V2 are matched by the operational amplifier OP, the voltages V1 and V2 can be expressed as:
Thus, the current I2 through the resistors R2 and R3 can be expressed as:
wherein thermal voltage
Because the resistors R1 and R2 are identical and the input voltages V1 and V2 are matched by the operational amplifier OP, the current I2 can be the same as the current I1.
Accordingly,
since the thermal voltage VT has a positive temperature coefficient of 0.085 mV/° C., the currents I1 and I2 have positive temperature coefficient.
Thus, the voltage Vbg can be expressed as:
Because the emitter-base voltage VEB of transistors has a negative temperature coefficient of −2 mV/° C., the voltage Vbg will have a nearly-zero temperature coefficient and low sensitivity to temperature if a proper ratio of resistances of the resistors R1˜R3 is selected.
In some embodiments, the resistor R3, for example, can be implemented by a resistor ladder.
Because the switches SW10˜SW1A are disposed in the path of the current I2, such that the non-ideal switch effects, such as, temperature coefficient and finite turn-on resistance, influence bandgap reference circuit parameters. For example, when the switch SW10 is turned on, the current I2 flows through resistor R31, switch SW10 and resistors R33˜R3N. Hence, non-ideal effects on the switch SW10 influence the bandgap reference circuit parameters. Further, if switches SW10˜SW1N are implemented by PMOS transistors, the N-well connected to the power voltage (not shown) also degrades bandgap reference circuit power supply rejection ration (PSRR) performance. After the optimal settings of switch array (SW10˜SW1M) are derived, the switches are replaced with hard-wiring if the PSRR is considered. Due to different characteristics of the switches and wires, the parameters of the bandgap reference circuit will drift.
The best way to prevent finite turn-on resistance and temperature coefficient of the switches is to put them on a high-impedance path, and in an operational amplifier-based bandgap reference circuit, the high-impedance path exists at the input terminals of the operational amplifier. Thus, the invention further provides a bandgap reference circuit which is not affected by the finite turn-on resistance and temperature coefficient of the switches.
The transistor Q1 comprises an emitter coupled to a positive input terminal of the operational amplifier OP, and a base and a collector both coupled to a ground voltage GND. The transistor Q2 comprises an emitter coupled to the resistor ladder 22, and a base and a collector both coupled to the ground voltage GND. Namely, the transistors Q1 and Q2 are diode-connected transistors. The resistor R1 is coupled between the positive input terminal and an output terminal of the operational amplifier OP. The resistor ladder 22 is coupled to the emitter of the transistor Q2, and the output terminal and a negative input terminal of the operational amplifier OP.
The resistor ladder 22 comprises a plurality of resistors RX1˜RXN connected in series and a plurality of switches SW21˜SW2M. The resistor RX1 is coupled between the output terminal of the operational amplifier OP and a node ND20, the resistor RX2 is coupled between the node ND20 and a node ND21, and so on, and the resistor RXN is coupled between the node ND2M and the emitter of the transistor Q2. Each switch SW20˜SW2M has a first terminal coupled to a corresponding node and a second terminal coupled to the negative input terminal of the operational amplifier OP. For example, the switch SW20 is coupled between the negative input terminal of the operational amplifier OP and the node ND20. The switch SW21 is coupled between the negative input terminal of the operational amplifier OP and the node ND21, and so on. The switch SW2M is coupled between the negative input terminal of the operational amplifier OP and the node ND2M.
The resistor string comprising resistors RX1˜RXN has a fixed total resistance, and resistances of the resistors R2 and R3 shown in
Thus, the output voltage Vbg′ of the bandgap reference circuit 20 also has a nearly-zero temperature coefficient and low sensitivity to temperature if a proper ratio of resistances of the resistors R1˜R3 is selected. In some embodiments, the transistors SW20˜SW2M are controlled by a set of control signals from an external control apparatus such that the resistors R2 and R3 can be adjusted to obtain a desired output voltage Vbg′.
For example, the switch SW30 is coupled between the output terminal and the node ND30. The switch SW31 is coupled between the output terminal and the node ND31, and so on. The switch SW3Z is coupled between the output terminal and the node ND3Z. The resistor ladder 24 performs a voltage division to the voltage Vbg′ by turning on one of the switches SW30˜SW3Z, such that the voltage Vbg′ can be lower than the voltage Vbg″ thereby operating in a low voltage environment. In some embodiments, the switches SW30˜SW3Z are controlled by another set of control signals from the external control apparatus such that the voltage Vbg″ can be operated in a low voltage environment.
As switches SW20˜SW2M each has one terminal coupled to one input terminal of the operational amplifier, i.e., a high-impedance path, there is no current flowing through any of the transistors SW20˜SW2M to the operational amplifier OP, and thus, non-ideal effects on the transistors SW20˜SW2M (switches) do not influence parameters of the bandgap reference circuit. Because there is no current flowing through the transistors (switches), the parameters of the bandgap reference circuit will not drift due to different characteristics of the switches and wires even if the PSRR is considered and the switches are replaced with hard-wiring after the optimal setting of switches SW20˜SW2M is derived. Thus, the inventive bandgap reference circuit is not affected by the finite turn-on resistance and temperature coefficient of the switches.
The bandgap reference circuits 10, 20 and 30 can act as a functional block for the operation of mixed-mode and analog integrated circuits (ICs), such as data converters, phase lock-loop (PLL), oscillators, power management circuits, dynamic random access memory (DRAM), flash memory, and much more. For example, the bandgap reference circuit 20 provides the output voltage Vbg′ to a core circuit, and the core circuit executes functions thereof accordingly.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
This application claims the benefit of U.S. Provisional Application No. 60/805609, filed Jun. 23, 2006, and entitled “Linear Voltage Regulator With Undershoot Minimization”, incorporated herein by reference.
Number | Date | Country | |
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60805609 | Jun 2006 | US |