Bandgap voltage reference source

Abstract

A voltage reference source arrangement (10; 20) is disclosed. The arrangement includes a voltage reference source (2) for: providing a first reference voltage (VB) with a first temperature coefficient (α). The arrangement further includes a plurality (N) of second voltage reference sources (3i) for providing compensation reference voltages (Vc,i) with second temperature coefficients (βi), the sign of these second temperature coefficients (βi) being opposite to the sign of the first temperature coefficient (α). The arrangement further includes a plurality (N) of adders (5i) for adding the first reference voltage (VB) and the compensation reference voltages (Vc,i). Thus, the voltage reference source arrangement can be designed with high accuracy.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention.

The present invention relates in general to a voltage reference source arrangement based on a bandgap voltage reference source.

2. Description of the Related Art

Bandgap voltage reference sources are commonly known. Conventionally, a bandgap voltage reference source arrangement includes a basic reference source having a negative temperature coefficient-and a compensation reference source having a positive temperature coefficient. The voltage provided by the compensation reference source is amplified such that the positive temperature coefficient substantially compensates the negative temperature coefficient of the basic reference source, and a reference voltage is obtained with a zero temperature coefficient.

A problem with such conventional reference source arrangement is that the compensation reference source may suffer from an offset voltage due to mismatches. Any such offset voltage will be amplified in the conventional reference source arrangement, with the consequence that the accuracy is poor.

In the art, there is a need for precision voltage sources. For instance, in battery operated devices, it is important that a user is signalled when the battery voltage drops below a threshold value, indicating that the battery should be replaced or recharged. Further, almost all kinds of analog-to-digital conversion and/or digital-to-analog conversion require a precision voltage reference sources for operating correctly.

Further, in the art, there is a further need for a voltage reference source with very specific characteristics. Specifically, in a practical example, there is a need for a voltage reference source having an output voltage of exactly 1V at a temperature of 27° C. while delivering a current of 5 mA, whereas the temperature coefficient should be exactly −1 mV/° C. in a large temperature range.

BRIEF SUMMARY OF THE INVENTION

It is a general objective of the present invention to provide a bandgap reference source arrangement with improved accuracy. Further, it is an objective of the present invention to provide a bandgap reference source arrangement where improved accuracy is an inherent property of the circuit design, without the need of complicated operations such as laser trimming, as is necessary in the current state of the art.

A further objective of the present invention is to provide a bandgap reference source arrangement with a predetermined non-zero temperature coefficient.

The invention is based on the insight that the mismatch and consequent offset in a compensation reference source is substantially random, and that the offsets of different compensation reference sources are uncorrelated. Based on this insight, the present invention provides a voltage reference source arrangement having a plurality of compensation reference sources. The number of such plurality corresponds to the amplification factor applied to the conventional compensation reference source. However, instead of amplifying the output of one single compensation reference source, the outputs of said plurality of compensation reference sources are added together. Each of said compensation reference sources may suffer from an offset, but in view of the fact that those offsets are uncorrelated, they may statistically eliminate each other. Formulated more correctly, the offset in the sum is less than the sum of the same offsets.

These and other aspects, characteristics and advantages of the present invention will be further clarified by the following description of a preferred embodiment of a voltage reference source arrangement in accordance with the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating the principles of a conventional voltage reference source arrangement;

FIG. 2 is a circuit diagram illustrating the principles of a voltage reference source arrangement according to the present invention;

FIG. 3 is a circuit diagram illustrating a possible chip implementation of a voltage reference source arrangement according to the present invention;

FIG. 4 is a circuit diagram illustrating a possible chip implementation of a compensation reference source for use in the voltage reference source arrangement of FIG. 3 ;

FIG. 5A is a graph showing the temperature characteristics of the voltage at subsequent stages in a simulated voltage reference source arrangement according to FIG. 3 ; and

FIG. 5B is a graph showing the temperature characteristics of the output voltage of a simulated voltage reference source arrangement according to FIG. 3 for different values of the supply voltage.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates the principles of functioning of a conventional voltage reference source arrangement 1 . A PN-junction 2 , for instance a diode, provides a basic reference voltage V B . The PN-junction 2 has a temperature characteristic with an approximately constant, negative temperature coefficient α. This means that, in a first order approximation, the temperature dependent basic reference voltage V B can be written as formula (1):

V B ( T )= V B ( T ref )+α( T−T ref )  (1)

Herein,

V B (T) is the value of the basic reference voltage V B at a certain temperature T; and

V B (T ref ) is the value of the basic reference voltage V B at a reference temperature T ref .

The negative temperature coefficient α is compensated in a compensation stage 6 , which comprises a compensation reference source 3 based on the voltage difference between two PN-junctions (not shown) and providing a compensation reference voltage V C . This compensation reference source 3 has a temperature characteristic with a positive temperature coefficient β. This means that, theoretically, the temperature dependent compensation reference voltage V C can be ideally written as formula (2):

V C ( T )= V C ( T ref )+β( T−T ref )  (2)

herein,

V C (T) is the value of the compensation reference voltage V C at a certain temperature T; and

V C (T ref ) is the value of the compensation reference voltage V C at a reference temperature T ref .

The output voltage of compensation reference source 3 is amplified by an amplifier 4 with a voltage gain γ, which is chosen such that formula (3) is met:

γ=|α/β|  (3)

From the above, it follows that, when designing the amplifier 4 of the circuit 1 , the values of α and β must be known beforehand.

In an adder 5 , the output voltage of the amplifier 4 is added to the basic reference voltage V B of PN-junction 2 in order to provide the reference voltage V ref according to formula (4): $$ V ref ⁡ ( T ) =   ⁢ γ ⁢   ⁢ V C ⁡ ( T ) + V B ⁡ ( T ) =   ⁢ γ ⁡ [ V C ⁡ ( T ref ) + β ⁡ ( T - T ref ) ] + [ V B ⁡ ( T ref ) + α ⁡ ( T - T ref ) ] =   ⁢ γ ⁢   ⁢ V C ⁡ ( T ref ) + V B ⁡ ( T ref ) ( 4 )

Thus, the temperature coefficient of the reference voltage V ref will be zero when equation (3) applies, and consequently V ref will be equal to the bandgap voltage of the silicon.

The functioning of the compensation reference source 3 is based on the voltage difference between two PN-junctions, such as for instance two diodes, two bipolar transistors, or two MOS transistors operating in the weak inversion region with different area and/or with different current flowing into each. Due to mismatch in these two PN-junctions, and further due to imperfections in the amplifier 4 , the compensation reference source 3 will, in practice, have an offset voltage V off in addition to its designed compensation reference voltage V C . Consequently, formula (2) changes into formula (2′):

V C ( T )= V C ( T ref )+β( T−T ref )+ V off   (2′)

and formula (4) changes into formula (4′):

V ref ( T )=γ V C ( T ref )+γ V B ( T ref )+ V off   (4′)

Thus, the conventional design as illustrated in FIG. 1 has a drawback that any offset in compensation reference source 3 , together with the input offset voltage of amplifier 4 , is amplified by the gain γ of the amplifier 4 . In practice, γ may be in the range of 8-14, and the reference voltage V ref as produced by the voltage reference source arrangement 1 will have a relatively large offset voltage, which can be as high as 100 mV.

Further, when comparing a large number of identically designed voltage reference source arrangements 1 , they will produce reference voltages which will not be identical to each other but which will spread around a mean value V 0 equal to γ V C (T ref )+V B (T ref ), due to the fact that the offset voltages V off in the different compensation reference sources 3 will be random and uncorrelated.

FIG. 2 illustrates the principles of functioning of a voltage reference source arrangement 10 according to the present invention. Similar to the conventional arrangement, a basic reference voltage V B is provided by a PN-junction 2 , for instance a diode, having a temperature characteristic with a negative temperature coefficient α such that the temperature dependent basic reference voltage V B obeys formula (1):

V B ( T )= V B ( T ref )+α( T−T ref )  (1)

Compensation for the negative temperature coefficient α is, again, provided by a compensation stage 16 on the basis of adding a voltage with a positive temperature coefficient. However, the compensation stage 16 according to the present invention comprises a plurality of N compensation reference sources 3 1 , 3 2 , . . . 3 N , each of which may be identical to the conventional compensation reference source 3 described above. Each individual compensation reference source 3 i (i=1−N) provides a compensation reference voltage V C,i which is added to the basic reference voltage V B . In the example as illustrated, the compensation stage 16 according to the present invention comprises a plurality of N adders 5 i , each having two inputs and an output, each having one input connected to a corresponding individual compensation reference source 3 i to receive the corresponding compensation reference voltage V C,i . As an alternative, the compensation stage 16 might have one adder with N+1 inputs and one output, as will be clear to a person skilled in the art.

The temperature dependent compensation reference voltage V C,i of each individual compensation reference source 3 i can be ideally written as formula (5):

V C,i ( T )= V C,i ( T ref )+β i ( T−T ref )  (5)

herein,

V C,i (T) is the value of the compensation reference voltage V C,i at a certain temperature T;

V C,i (T ref ) is the value of the compensation reference voltage V C,i at a reference temperature T ref ; and

β i is the positive temperature coefficient of the compensation reference source 3 i .

The output reference voltage V ref of the voltage reference source arrangement 10 according to the present invention can be expressed as formula (6): $$ V ref ⁡ ( T ) =   ⁢ V B ⁡ ( T ) + ∑ { V C , i ⁡ ( T ) } =   ⁢ [ V B ⁡ ( T ref ) + α ⁡ ( T - T ref ) ] + ∑ { V C , i ⁡ ( T ref ) + β i ⁡ ( T - T ref ) } =   ⁢ V B ⁡ ( T ref ) + ∑ { V C , i ⁡ ( T ref ) } + { α + ∑ β i } ⁢ ( T - T ref ) ( 6 )

wherein Σ denotes summation from i=1 to N.

Thus, the temperature coefficient of the reference voltage V ref will be approximately zero when the absolute value of Σβ i is approximately equal to the absolute value of α.

If, for all compensation reference sources 3 i , the temperature coefficients are equal to each other, then Σβ i can be written as Nβ, wherein N is the number of compensation reference sources.

As in the conventional design, the functioning of the compensation reference sources 3 i is based on the voltage difference between two PN-junctions, and, due to mismatch in these two PN-junctions, the compensation reference sources 3 i may, in practice, each have an offset voltage V off,i in addition to their designed compensation reference voltage V C,i . Consequently, formula (5) changes into formula (5′):

V C,i ( T )= V C,i ( T ref )+β i ( T−T ref )+ V off,I   (5′)

and formula (6) changes into formula (6′):

V ref ( T )= V B ( T ref )+Σ{ V C,i ( T ref )}+{α+Σβ i }( T−T ref )+Σ V off,I   (6′)

Now, as mentioned above, the offset voltages V off,i of the compensation reference sources 3 i are random and uncorrelated. Therefore, the sum ΣV off,i of the offset voltages V off,i will, in the mean, be less than N times the offset voltage V off of one compensation reference source 3 . In other words, the accuracy of the voltage reference source arrangement 10 is improved with respect to the accuracy of the conventional voltage reference source arrangement 1 . Further, when comparing a large number of identically designed voltage reference source arrangements 10 , they will show some spread around a mean value, but the spread will be reduced in comparison to the conventional spread. More particularly, when replacing a conventional arrangement in which a gain factor γ equal to N is employed by an inventive arrangement with N reference sources, the spread of the resulting reference voltages is reduced by N. In practice, when N ranges from 8-14, the spread of the resulting reference voltages is reduced by 2.8-3.7.

If desired, a further improvement of the accuracy is possible by designing each compensation reference source 3 i such that β i is smaller, resulting in a larger value of N. However, since this would result in a more complex design, involving use of a larger silicon area and higher costs, a trade-off has to be found between desired accuracy and acceptable costs when determining N.

Thus, in one aspect, an important advantage of the invention is to be recognised in the fact that random offsets are handled by averaging obtained by summation instead of multiplication obtained by amplification.

Further, the fact that an amplifier, including an op-amp and at least one resistor, is no longer needed constitutes an important advantage. The offset of the op-amp constitutes an important contribution to the total offset, and eliminating this op-amp also eliminates this offset contribution, resulting in an important decrease of the total offset.

FIG. 3 is a circuit diagram illustrating a possible chip implementation of a voltage reference source arrangement 20 according to the present invention. The circuit comprises a bias source 40 , comprising a first P-transistor 41 and a second N-transistor 42 . The first P-transistor 41 has its source coupled to a supply voltage V DD , and has its drain coupled to ground GND through a first current source 43 . The second N-transistor 42 has its source coupled to ground GND, and has its drain coupled to said supply voltage V DD through a second current source 44 . The gate of the first P-transistor 41 is connected to the drain of this first P-transistor 41 , and constitutes a positive bias output 45 of the bias source 40 . The gate of the second P-transistor 42 is connected to the drain of this second P-transistor 42 , and constitutes a negative bias output 46 of the bias source 40 .

The circuit 20 comprises further a plurality (in this case: nine) of compensation cells 30 i , the implementation of which is illustrated more clearly in FIG. 4 . Each compensation cell 30 has a supply voltage input 31 , a second supply voltage input or ground input 32 , a positive bias input 33 , a negative bias input 34 , a cell input 35 and a cell output 36 . The supply voltage input 31 of each compensation cell 30 is connected to said supply voltage V DD . The ground input 32 of each compensation cell 30 is connected to said ground GND. The positive bias input 33 of each compensation cell 30 is connected to said positive bias output 45 of the bias source 40 . The negative bias input 34 of each compensation cell 30 is connected to said negative bias output 46 of the bias source 40 . The cell input 35 1 of the first compensation cell 30 1 is connected to PN-junction 2 for receiving the basic reference voltage V B . The cell input 35 i of next compensation cells 30 i is connected to the cell output 36 i−1 of the corresponding previous compensation cell 30 i−1 . The cell output 36 9 of the last compensation cell 30 9 is connected to an output terminal 22 of the voltage reference source arrangement 20 .

Each compensation cell 30 i produces at its output 36 i a cell output voltage V OUT,i equal to the cell input voltage V IN,i received at its input 35 i plus a compensation voltage contribution V C,i . Each compensation cell 30 comprises a first compensation N-transistor X 1 and a second compensation N-transistor X 2 , having their gates connected together. Each compensation cell 30 comprises further a first bias P-transistor 37 and a second bias N-transistor 38 , and a third bias P-transistor 39 . The first bias P-transistor 37 has its source connected to the supply voltage input 31 , has its gate connected to the positive bias input 33 , and has its drain connected to the drain and the gate of the first compensation N-transistor X 1 . The second bias N-transistor 38 has its source connected to the ground input 32 , has its gate connected to the negative bias input 34 , and has its drain connected to the source of the second compensation N-transistor X 2 . The third bias P-transistor 39 has its source connected to the supply voltage input 31 , has its gate connected to the gate node of the first and second compensation N-transistors X 1 and X 2 , and. has. its drain connected to the drain of the second compensation N-transistor X 2 . The source of the first compensation N-transistor X 1 is connected to the cell input 35 ; the source of the second compensation N-transistor X 2 is connected to the cell output 36 .

The two compensation transistors X 1 and X 2 are operating in the weak inversion. The first compensation N-transistor X 1 receives a first bias current from the first bias P-transistor 37 , and the second compensation N-transistor X 2 receives a second bias current from the second bias N-transistor 38 . In this design, the currents flowing through the two compensation transistors X 1 and X 2 are equal. However, the aspect ratio of the second compensation N-transistor X 2 is Z times as large as the aspect ratio of the first compensation N-transistor X 1 . Therefore, a voltage difference ΔV is developed between the sources of the two compensation transistors X 1 and X 2 , which implies that V OUT =V IN +ΔV.

Herein, ΔV=U T In(Z), wherein U T =25.9 mV at room temperature (300 K). It is noted that the DC-current flowing into the second P-transistor 42 is twice as large as the DC-current flowing into the first P-transistor 41 .

Further, it is noted that the same current as flowing into the first bias P-transistor 37 is also applied to the output of the compensation cell 30 . If the current flowing into the second bias N-transistor 38 9 of the last compensation cell 30 9 is reduced by 2 by halving its size, this additional current is no longer needed, leading to lower power dissipation.

The properties of the voltage reference source arrangement 20 shown in FIG. 3 have been examined in a simulation. The results are shown in FIG. 5 A. The horizontal axis shows the device temperature in degrees Centigrade. The vertical axis shows voltage in Volt. The graph shows nine lines V ref,1 -V ref,9 , being the output voltages of the nine compensation cells 30 i , respectively. The graph clearly shows that the output reference voltage V ref of the voltage reference source arrangement 20 , being equal to V ref,9 of FIG. 5A , is very stable with respect to temperature variations: over the range from −40° C. to +85° C., the temperature coefficient was as low as 46 ppm/° C. FIG. 5B , wherein the output reference voltage V ref,9 of FIG. 5A is shown for three different values of the supply voltage V DD (3.5 V for the top curve, 3 V for the middle curve, and 2.5 V for the lower curve), the scale of the vertical axis being enlarged, shows this even more clearly. Further, the simulation of this design showed a supply voltage coefficient of 0.7% and a total current drain as low as 0.9 μA.

By comparing the output voltages of the nine compensation cells 30 1 - 30 9 as shown in FIG. 5A , it is clearly demonstrated that, when going from stage to stage, the output voltage increases due to addition of compensation voltage V C , while further the temperature coefficient increases (from negative to approximately zero at room temperature) due to each compensation voltage V C having a positive temperature coefficient.

In the above, the invention has been explained in respect of the objective of providing a reference voltage source of which the output voltage is accurate and stable, meaning that its temperature coefficient is as low as possible, preferably zero; graph V ref,9 of FIG. 5A , and also FIG. 5B , has demonstrated that this objective is attained, indeed. However, in some applications there is a need for a voltage reference source of which the output voltage has a temperature coefficient with a specified non-zero value. For instance, in a radio receiver there is a need for a reference voltage source having an output voltage of 1V at a temperature of 27° C. with a temperature coefficient of −1 mV/° C. in a large temperature range in order to compensate for the temperature coefficient of a low-noise amplifier. In accordance with the invention, such reference voltage source can easily be provided by choosing the number of compensation cells 30 i in an appropriate way. For instance, with reference to FIG. 3 and FIG. 5A , more particularly graph V ref,4 , a voltage reference source arrangement 20 with four compensation cells would suffice to provide a temperature coefficient of approximately −1 mV/° C.

It should be clear to a person skilled in the art that the scope of the present invention is not limited to the examples discussed in the above, but that several amendments and modifications are possible without departing from the scope of the invention.

In the above, it is explained that the temperature coefficient of the reference voltage V ref will be zero when the absolute value of Σβi is equal to the absolute value of α. In other words, Σβi should ideally be equal to the absolute value of α; or, if all temperature coefficients are equal to each other, Nβ should ideally be equal to the absolute value of α, wherein N is the number of compensation reference sources. In practice, such will not always be possible. If the ratio |α/β| is not an integer, another compensation reference source can be added, including an attenuator, i.e. an amplifier with a gain g smaller than 1, between the compensation reference source and its corresponding adder, as will be explained in the following.

Assume that |α/β| can be written as M+R, wherein M is an integer and R has a value between 0 and 1. Consider a compensation stage 16 as illustrated in FIG. 2 , comprising N identical compensation reference sources 3 i , in which N−1=M. Further, consider an amplifier connected between the output of the N-th compensation reference source 3 N and its corresponding adder 5 N , the amplifier having a gain g=R. From equation (6), it will be clear that the temperature coefficient of the reference voltage V ref will be equal to zero:

{α+Σβ i }=α+( N −1)β+ g β=α+( M+R )β=0

Similar calculation applies if the compensation reference sources 3 i have mutually different values for β. Also, the attenuator need not necessarily be associated with the last compensation reference source 3 N and its corresponding adder 5 N . Also, it is possible to have such attenuators associated with more than one compensation reference source.

Claims

1. A voltage reference source arrangement, comprising:first voltage reference means (2) for providing a first reference voltage (VB) with a first temperature coefficient (α); a plurality (N) of at least two second voltage reference means (3i; 30i) for providing compensation reference voltages (VC,i) with second temperature coefficients (βi), a sign of the second temperature coefficients (βi) being opposite to a sign of the first temperature coefficient (α); and means (5i; 30i) for adding the first reference voltage (VB) and the compensation reference voltages (VC,i).

2. The voltage reference source arrangement according to claim 1, wherein the plurality (N) of second voltage reference means (3i; 30i) is in the range of 8-14.

3. A voltage reference source arrangement, comprising:first voltage reference means (2) for providing a first reference voltage (VB) with a first temperature coefficient (α); a plurality (N) of at least two second voltage reference means (3i; 30i) for providing compensation reference voltages (VC,i) with second temperature coefficients (βi), a sign of the second temperature coefficients (βi) being opposite to a sign of the first temperature coefficient (α); and a plurality (N) of adders (5i), wherein each adder (5i) includes two inputs and one output, wherein a first adder (51) has a corresponding first input coupled to receive the first reference voltage (VB), wherein for i>1, each adder (5i) has a corresponding first input connected to the output of a previous adder (5i−1), and wherein each adder (5i) has a corresponding second input coupled to receive the compensation reference voltages (VC,i) from an associated second voltage reference means (3i).

4. A voltage reference source arrangement, comprising:first voltage reference means (2) for providing a first reference voltage (VB) with a first temperature coefficient (α); a plurality (N) of at least two second voltage reference means (3i; 30i) for providing compensation reference voltages (VC,i) with second temperature coefficients (βi), a sign of the second temperature coefficients (βi) being opposite to a sign of the first temperature coefficient (α); and a plurality (N) of compensation cells (30i), wherein each compensation cell (30i) includes a cell input (35i), a cell output (36i), and voltage difference means (X1, X2) coupled between the cell input (35i) and the cell output (36i), said voltage difference means (X1, X2) being arranged for maintaining a voltage difference (VC,i) between the cell output (36i) and the cell input (35i), wherein a first compensation cell (30i) has a corresponding cell input (35i) coupled to receive the first reference voltage (VB), and wherein for i>1, each compensation cell (30i) has a corresponding cell input (35i) connected to the cell output (36i) of a previous compensation cell (30i−1).

5. The voltage reference source arrangement according to claim 4, wherein, for each compensation cell (30i):said voltage difference means (X1, X2) includes a first compensation transistor (X1) of a first conductivity type and a second compensation transistor (X2) of the same conductivity type; a first gate of the first compensation transistor (X1) is connected to a second gate of the second compensation transistor (X2); and a first source of the first compensation transistor (X1) is connected to the cell input (35) of the compensation cell (30i) and a second source of the second compensation transistor (X2) is connected to the cell output (36) of the compensation cell (30i).

6. The voltage reference source arrangement according to claim 5, wherein:each compensation cell (30i) further includes a first bias P-transistor (37) and a bias N-transistor (38); the first compensation transistor and the second compensation transistor (X1, X2) are N-type; a first drain of the first compensation transistor (X1) is coupled to a first supply voltage (VDD) by a first gate of the first bias P-transistor (37) being connected to a positive bias input (33) of the compensation cell (30i); and the second source of the second compensation transistor (X2) is further coupled to a second supply voltage (GND) by a second gate of the bias N-transistor (38) being connected to a negative bias input (34) of the compensation cell (30i).

7. The voltage reference source arrangement according to claim 6, wherein each compensation cell (30i) further includes a second bias P-transistor (39) having a third source connected to the first supply voltage (VDD), a second drain connected to the first drain of the second compensation N-transistor (X2), and a third gate connected to the first gate the first compensation transistor and the second gate of the second compensation transistor.

8. The voltage reference source arrangement according to claim 5, wherein the first compensation transistor and the second compensation transistor (X1, X2) are operating in the weak inversion region.

9. The voltage reference source arrangement according claim 5, wherein the aspect ratio of the second compensation transistor (X2) is larger than the aspect ratio of the first compensation transistor (X1).

10. The voltage reference source arrangement according to claim 1, wherein an attenuator is coupled between at least one of said second voltage reference means (3i; 30i) and a corresponding adding means (5i; 30i).

11. The voltage reference source arrangement according to claim 3, wherein an attenuator is coupled between at least one of said second voltage reference means (3i; 30i) and a corresponding adder (5i).

12. The voltage reference source arrangement according to claim 3, wherein an attenuator is coupled between at least one of said second voltage reference means (3i; 30i) and a corresponding compensation cell (30i).