Patent Application
20140176233
A portion of the disclosure of this patent document contains material, which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
The invention relates to calibration circuits in general and, more particularly, to calibration circuits for filters such as analogue filters for signal processing.
Analog filters are widely used in signal processing to pass desired signals and reject unwanted interference. However, analog filter operational bandwidth can vary from design specifications by ±30% due to various factors in filter processing, voltage, and operating temperature (“PVT”). Therefore, automatic bandwidth calibration is required to compensate for PVT variations in filters. Although various approaches have been made to calibrate filter bandwidth, conventional approaches typically consume large chip areas, require high supply voltages, and are easily degraded by noise, negatively impacting the bandwidth calibration. Further, high resolution bandwidth calibration often requires long calibration times. Thus there is a need in the art for improved calibration techniques, particularly calibration techniques consuming low power and small amounts of chip real estate.
It is an objective of the presently claimed invention to provide a low power, high accuracy calibration circuit for filter calibration. The calibration circuit includes a chargeable voltage storage element. A first measurement and adjustment circuit determines a charge time required for the voltage of the chargeable voltage storage element to substantially match a reference voltage. The circuit adjusts the voltage storage element to make the charge time approximately equal to a predetermined filter time constant value, the adjustment circuit updating the reference voltage to make the charge time substantially equal to the predetermined filter time constant value and iteratively updating the reference voltage to refine the charge time. A second circuit is configured to have substantially the predetermined filter time constant value based on the adjustment configuration determined by the adjustment of the voltage storage element and the reference voltage of the first circuit.
Embodiments of the invention are described in more detail hereinafter with reference to the drawings, in which
In the following description, circuits for analog filter bandwidth calibration and the like are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the invention. Specific details may be omitted so as not to obscure the invention; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.
In general, filter bandwidth is inversely proportional to the product of the resistance and capacitance, known at the RC time constant. To calibrate a filter, the RC time constant is measured to determine the variation from the design specification. Once the variation is known, the RC time constant can be altered to approximate the design specification, compensating for PVT variations. Turning to
However, for high resolution calibration, more control bits are required. This requires a large array of capacitors. This large capacitor array in the calibration circuit occupies a large chip area and consumes a large charging current. Further, noise from the power supply and ground affects comparator decision. Also, a mismatch in I1 and I2 can cause systemic error.
However, the novel approach of the present invention reduces the calibration capacitance, its associated chip area, and charging current by a reference adaptation scheme without sacrificing calibration accuracy. The approach of the present invention also improves immunity to noise from the supply and ground by performing multiple comparisons and then averaging. Further, current matching is improved through the use of a cascode current mirror.
As seen in the exemplary embodiment of the present invention schematically depicted in
To provide rapid and accurate calibration in the present invention, the calibration is divided into coarse and fine phases. To get m+n bits calibration accuracy, only m bits MSBs (Most-Significant-Bits) are settled in capacitor array. Advantageously, this reduces the size of the capacity array, saving valuable chip space and reducing power consumption. The remaining n LSBs (Least-Significant-Bits) are resolved in the inventive reference adaptation scheme. In determining −nth bit, V′ref is set to:
To perform this, an m+n−1 bits DAC (Digital-to-Analog Converter) is used for V′ref adaptation. A schematic depiction of the DAC implementation is shown in
For example, capacitor voltage (Vx) is easily affected by noise from power and ground. Thus for a single measurement at a period of high noise, the comparator will probably output wrong result. Therefore, the digital logic controls the comparator to compare M times between capacitor voltage and reference voltage. (M is decided by the maximum time allowed for the bandwidth calibration.) If a logic high from comparator output is obtained N times, the bandwidth calibration control code is considered to be correct (50%*M<N<M). As a result, one or more comparison errors will not cause an incorrect bandwidth calibration code. The values of M and N values are set to adjust for a predetermined level of error tolerance.
In more detail, referring to
Next, update V′ref:
If Vx>V′ref, S-1=“1”, otherwise, S-1=“0”.
The foregoing description of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to the practitioner skilled in the art.
While the invention has been described with respect to various exemplary features and advantages, it will be appreciated that the present invention is not limited to such features and that numerous other variations, alternatives, and modifications can be made without departed from the scope and spirit of the appended claims.
