Patent Application
20240136833
This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0138102 filed on Oct. 25, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in their entireties.
Embodiments of the present disclosure described herein relates to a semiconductor device, and more particularly, to a battery charger integrated circuit that adaptively limits an overcurrent, a mobile device including the same, and an operation method thereof.
Recently, various types of mobile devices for communication or information exchange have been spread. A mobile device uses a rechargeable battery as a power source in order to provide an advantage of mobility. In general, when a mobile device is connected to a charger (e.g., a Travel Adapter (TA)) that enables battery charging, it operates in a charging mode (or a buck mode) for battery charging. On the other hand, when external devices are connected through a port such as a USB terminal, the mobile device also supports On-The-Go (OTG) mode (or a boost mode) to provide power to external devices using an internal battery. To this end, a charger Integrated Circuit (IC) (hereinafter “a charger IC”) for managing a charging mode and an OTG mode of a battery is used in a mobile device.
In a battery charger IC of a switching method that manages a charging current of a battery by switching an inductor current, an inductor current level limit is required to protect circuit elements. By sensing the level of the inductor current, an overcurrent limit (OCL) operation was applied. In this case, it can be implemented with a simple structure, but the amount of energy that can be transferred through the inductor is limited due to an OCL. In addition, there is a problem in that ripple of a large inductor current generated according to a switching operation occurs. Accordingly, there is a need for a battery charger IC capable of reducing a ripple of an inductor current in an OCL operation and increasing the amount of supplied energy.
Embodiments of the present disclosure provide a charger IC, a mobile device, and an operating method thereof capable of reducing the ripple of an inductor current in an overcurrent limit (OCL) operation and increasing the amount of supplied energy.
According to an aspect of the present disclosure, a battery charger integrated circuit for charging a battery, includes: an overcurrent limiting detector configured to detect whether a level of an inductor current reaches an overcurrent limiting level and to generate an overcurrent limiting detection voltage; a control loop circuit configured to generate a reset voltage by comparing a ramp voltage reflecting the level of the inductor current with an error voltage generated based on an operating condition that is out of a preset operating condition; an adaptive overcurrent limiting controller configured to generate an overcurrent limiting control current by counting a number of pulses of the overcurrent limiting detection voltage and a number of pulses of the reset voltage; an oscillator configured to generate an oscillation voltage wherein a frequency of the oscillation voltage varies based on a magnitude of the overcurrent limit control current; and a switching transistor for switching the inductor current based on the oscillation voltage.
According to another aspect of the present disclosure, an electronic device includes: an inductor supplying a charging current supplied from a charging terminal to a battery and a load; switching transistors configured to switch the inductor current flowing through the inductor based on a duty voltage and configured to transfer the inductor current as a battery current for charging the battery or a load current supplied to the load; and a battery charger integrated circuit configured to monitor a change in the load current and varying a switching frequency of the inductor current. The battery charger integrated circuit is configured to increase the switching frequency by counting a number of times that a level of the inductor current reaches an overcurrent limit level.
According to another aspect of the present disclosure, a method performed by a battery charger integrated circuit, the method includes: detecting an increase in a load current; increasing a duty cycle of a duty voltage for switching an inductor current in response to detecting the increase in the load current; detecting whether a level of the inductor current reaches a predetermined overcurrent limit level; and increasing a switching frequency of the duty voltage based on a number of consecutively reaching the predetermined overcurrent limit level of the inductor current, which reaches a predetermined reference number of times.
The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and it is to be considered that an additional description of the claimed invention is provided. Reference signs are indicated in detail in preferred embodiments of the present disclosure, examples of which are indicated in the reference drawings. Wherever possible, the same reference numbers are used in the description and drawings to refer to the same or like parts.
The battery charger IC 1000 may operate in a buck mode or a boost mode according to a device connected to the charging terminal 130. For example, when a travel adapter 120 is connected to the charging terminal 130, the battery charger IC 1000 operates in a buck mode. That is, in the buck mode, the battery charger IC 1000 operates in a buck converter or charger mode in which the battery 1900 is charged by switching power provided through the travel adapter 120. On the other hand, when an On-The-Go (OTG) device 110 is connected to the charging terminal 130, the battery charger IC 1000 operates in a boost mode or OTG mode. That is, in the boost mode, the battery charger IC 1000 may switch power charged in the battery 1900 and provide the boosted voltage to the OTG device 110.
The battery charger IC 1000 may operate stably even in a charger mode or OTG mode under heavy load conditions. That is, the battery charger IC 1000 may stably supply load power to systems of the mobile device 100, such as an Application Processor (AP) memory, and storage, regardless of the operating mode. At this time, when the inductor current switched by the battery charger IC 1000 exceeds a saturation level, the battery charger IC 1000 may malfunction. Also, high inductor current may damage the battery charger IC 1000. Therefore, an overcurrent limit (OCL) operation is essential for the battery charger IC 1000 to prevent malfunction or damage.
The battery charger IC 1000 of the present disclosure includes an adaptive OCL controller 1300. The adaptive OCL controller 1300 may increase a switching frequency of the inductor current when the load current increases. At a fixed switching frequency, as in a related art, it is difficult to supply sufficient power to the required load. On the other hand, if the switching frequency of the inductor current is increased by the OCL controller 1300, maximum power transfer is possible within a range that does not violate the overcurrent limit. These advantages of the present disclosure will be explained in more detail through the drawings to be described later.
The control loop circuit 1100 generates a reset voltage VRST for maintaining a preset charging condition or a voltage output condition. For example, in a charger mode or a buck mode, a case in which at least one level of preset charging conditions (VBYP, VSYS, VBAT, ICHG, IBAT) exceeds a set range (or a predetermined range) may occur. At this time, the control loop circuit 1100 generates a reset voltage VRST as a control signal for reducing the inductor current IIND.
Reset voltage VRST drives the switching transistor 1800 to reduce inductor current IIND. That is, when the reset voltage VRST is provided at a high level, the duty voltage VDUT transitions to a low level, and as a result, the first switching transistor MH is turned off and the second switching transistor ML is turned on. Accordingly, a level of the inductor current IIND decreases.
In addition, in the OTG mode or the boost mode, when the level of the output voltage VCHG of the charging terminal 130 exceeds a set condition (or a predetermined condition), the control loop circuit 1100 generates the reset voltage VRST to reduce the inductor current IIND. A specific configuration or function of the control loop circuit 1100 will be described in more detail through the drawings to be described later.
The OCL detector 1200 determines whether the inductor current reaches the OCL level based on the inductor detection current ILSEN sensed by the current sensor 1050. The OCL detector 1200 generates an OCL detection voltage VOCL based on the determination result. The OCL detection voltage VOCL is delivered to the adaptive OCL controller 1300 and the OR gate 1500, respectively.
The adaptive OCL controller 1300 generates an OCL control current IOCL for adjusting the switching frequency fsw of the inductor current IIND based on the reset voltage VRST and the OCL detection voltage VOCL. For example, the adaptive OCL controller 1300 may increase the level of the OCL control current IOCL when the OCL detection voltage VOCL continuously occurs more than a reference number of times (select one (1) among above/below).
When the level of the OCL control current IOCL increases, the switching frequency fSW of the oscillation voltage VOSC generated by the oscillator 1400 increases. As the frequency of the oscillation voltage VOSC increases, the switching frequency fSw or a switching speed of the switching transistor 1800 increases. When the switching frequency fSw of the switching transistor 1800 increases, the ripple of the inductor current IIND delivered to the system becomes relatively small, and the average inductor current Ism increases. Thus, the amount of energy provided to the system is relatively increased.
On the other hand, the adaptive OCL controller 1300 reduces the OCL control current IOCL when the continuously occurring reset voltage VRST is greater than or equal to a reference number of times (select one (1) among above/below). When the level of the OCL control current IOCL decreases, the frequency of the oscillation voltage VOSC generated by the oscillator 1400 decreases. As the frequency of the oscillation voltage VOSC decreases, the switching frequency fsw or the switching speed of the switching transistor 1800 slows down. When the switching frequency fsw of the switching transistor 1800 is lowered, the ripple of the inductor current IIND delivered to the system becomes relatively large, and the average inductor current IIND decreases.
The oscillator 1400 generates an oscillation voltage VOSC having a variable frequency according to the level of the OCL control current IOCL provided by the adaptive OCL controller 1300. The oscillator 1400 may determine the rising slope of the node voltage VSAW through the OCL control current IOCL. If the OCL control current IOCL is large, the node voltage VSAW increases rapidly.
Also, when the node voltage VSAW reaches the reference level, the oscillator 1400 generates a pulse-shaped oscillation voltage VOSC. Therefore, when the OCL control current IOCL is large, the generation frequency or frequency of the oscillation voltage VOSC increases. As a result, as the OCL control current IOCL increases, the switching frequency fsw of the duty voltage VDUT generated based on the oscillation voltage VOSC also increases. Then, the switching speed of the inductor current IIND is increased by the duty voltage VDUT. The structure of the oscillator 1400 will be described in more detail through drawings to be described later.
The OR gate 1500 resets the SR latch 1600 when any one of the reset voltage VRST and the OCL detection voltage VOCL is activated. That is, the OR gate 1500 resets the SR latch 1600 when any one of the reset voltage VRST and the OCL detection voltage VOCL becomes high, and as a result, the duty voltage VDUT can be transitioned to a low level. When the duty voltage VDUT transitions to a low level, the first switching transistor MH of the switching transistor 1800 is turned off and the second switching transistor ML is turned on. Accordingly, the OR gate 1500 determines a falling point or duty cycle of the duty voltage VDUT to reduce the inductor current IIND.
The SR latch 1600 generates a duty voltage VDUT for driving the gate driver 1700 or the switching transistor 1800. The duty voltage VDUT generates a duty voltage VDUT. A duty cycle of the duty voltage VDUT is determined by the oscillation voltage VOSC, the reset voltage VRST, and the OCL detection voltage VOCL. That is, the duty voltage VD U T transitions to a high level in synchronization with the oscillation voltage VOSC provided to the set input ‘S’ of the SR latch 1600. Also, the duty voltage VDUT transitions to a low level in synchronization with the reset voltage VRST or the OCL detection voltage VOCL.
The gate driver 1700 generates gate control signals VGH and VGL for driving the switching transistor 1800 including power switches, based on the duty voltage VDUT. The gate driver 1700 may generate gate control signals VGH and VGL having a sufficient level to drive the switching transistor 1800 operating at a relatively high voltage.
The switching transistor 1800 may include a first switching transistor MH and a second switching transistor ML. The first switching transistor MH supplies the charging current ICHG to the inductor L to increase the inductor current IIND supplied to the system through the inductor L. On the other hand, the second switching transistor ML connects or blocks one end of the inductor L and the ground in order to reduce the inductor current IIND supplied to the system through the inductor L. The first switching transistor MH and the second switching transistor ML may be implemented as a power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) usable as a switching element.
The battery 1900 may be built into the mobile device 100. In one embodiment, the battery 1900 may be detachable from the mobile device 100. The battery 1900 may include one or a plurality of battery cells. A plurality of battery cells may be connected in series or parallel. The battery switch Mbat constituting an input terminal or an output terminal of the battery 1900 is shown as a PMOS transistor, but the present disclosure is not limited thereto. For example, it will be appreciated that the battery switch Mbat may be implemented with an NMOS transistor or other type of switch element.
As described above, the battery charger IC 1000 according to an embodiment of the present disclosure counts the number of times that the magnitude of the inductor current IIND reaches the OCL level to determine the switching frequency fSW of the inductor current IIND. When the switching frequency fSW is fixed, the average value of the switched inductor current IIND cannot increase due to the OCL, making it difficult to supply sufficient power to the load. On the other hand, as the switching frequency fsw changes, the fluctuation of the switched inductor current IIND decreases, but the average value increases. Accordingly, it is possible to provide a relatively higher average value of inductor current IIND, so that sufficient power required can be supplied to the load even in the presence of an OCL.
The buck compensator 1110 generates an error voltage VERR_Buck by monitoring charging conditions (VBYP, VSYS, VBAT, ICHG and IBAT) when operating in a charging mode or a buck mode. For example, when the bypass voltage VBYP of the switching transistor 1800 rises beyond a reference value in the charging mode, this state is monitored by the error amplifier 1111 and an error voltage VERR_BYP is generated. Then, the output of the error amplifier 1111 is selected by the selector 1112 and transmitted to the multiplexer 1170. The multiplexer 1170 will select ‘0’ input and pass it to the comparator 1190 in the charging mode. As such, in the charging mode, the buck compensator 1110 selects one of the charging conditions (VBYP, VSYS, VBAT, ICHG and IBAT) that exceeds or falls short of the reference value to generate the error voltage VERR, and comparator 1190 to trigger the generation of the reset voltage VRST. When the reset voltage VRST is generated, the inductor current IIND is reduced by switching.
The boost compensator 1130 monitors the charging voltage VCHG generated at the charging terminal 130 in the boost mode. When the charging voltage VCHG rises excessively and exceeds the reference level VCHG,REF, the error amplifier E.A of the boost compensator 1130 generates an error voltage VERR_Boost. Then, the multiplexer 1170 selects the ‘1’ input and passes it to the comparator 1190 in the boost mode. The comparator 1190 compares the error voltage VERR_Boost with the ramp voltage VRMP to generate the reset voltage VRST. When the reset voltage VRST is generated, the inductor current IIND decreases due to switching, and the level of the charging voltage VCHG also decreases.
The ramp generator 1150 generates the ramp voltage VRMP for comparison with the error voltage VERR in the comparator 1190. To generate the ramp voltage VRMP, the ramp generator 1150 includes a ramp current source 1151, a capacitor CRMP, a resistor R, a multiplexer 1155, an inverter INV, and a switch transistor MS. The procedure for generating the ramp voltage VRMP is as follows.
First, the sensing current ILSEN provided as a result of sensing the magnitude of the inductor current END is fed back and transmitted to the ramp generator 1150. Then, the sensing current ILSEN is converted into the sensing voltage VLSEN by the resistor R. Subsequently, when the ramp capacitor CRMP is charged by the ramp current IRMP supplied from the ramp current source 1151, the ramp voltage VRMP is obtained by adding the sensing voltage VLSEN and the voltage formed in the ramp capacitor CRMP. In a period in which charges are charged by the ramp capacitor CRMP, the ramp voltage VRMP has a ramp waveform rising with a predetermined slope. The multiplexer 1155 selects the gate control signal VGL for controlling the second switching transistor ML provided to the ‘1’ input terminal in the boost mode. On the other hand, the multiplexer 1155 selects the gate control signal VGH that controls the first switching transistor MH provided to the ‘0’ input terminal in the buck (or charge) mode. Currently, when the ramp generator 1150 is operating in the buck mode, the gate control signal VGH is selected and inverted by the inverter INV to turn on the switch transistor Ms. When the gate control signal VGH falls, the ramp voltage VRMP stops rising and is discharged. The waveform of the ramp voltage VRMP provided by the ramp generator 1150 will be described in detail with reference to
The multiplexer 1170 selects the error voltage VERR according to the mode. In the boost mode, the multiplexer 1170 selects the error voltage VERR from the boost compensator 1130 provided to the ‘1’ input terminal and transfers it to the comparator 1190. On the other hand, in the buck (or charge) mode, the multiplexer 1170 selects the error voltage VERR from the buck compensator 1110 provided to the ‘0’ input terminal and transfers it to the comparator 1190.
The comparator 1190 compares the error voltage VERR with the ramp voltage Vin to generate the reset voltage VRST. At a point in time when the ramp voltage VRMP, which increases with the ramp waveform, becomes higher than the error voltage VERR, the comparator 1190 generates a pulse-shaped reset voltage VRST. Accordingly, when the ramp voltage VRMP does not reach the error voltage VERR within one cycle, there is a case in which the pulse of reset voltage VRST does not occur. For example, generation of the reset voltage VRST may be omitted in a period in which the inductor current IIND gradually increases. Instead, the drop of the duty voltage VDUT may be controlled by the OCL detection voltage VOCL generated according to the increase of the inductor current IIND.
In the above, an exemplary configuration of the control loop circuit 1100 of the present disclosure has been described. The ramp voltage VRMP and the error voltage VERR are provided by the control loop circuit 1100. The control loop circuit 1100 generates the reset voltage VRST using the ramp voltage VRMP and the error voltage VERR. The reset voltage VRST is provided to the adaptive OCL controller 1300 of the present disclosure and is also used as a source for controlling the frequency of the oscillation voltage VOSC.
Here, the sensing voltage VLSEN has a voltage level corresponding to the magnitude of the sensing current ILSEN generated from the sensing result of the inductor current IIND. Accordingly, by selecting appropriate OCL reference voltages VOCL,REF, the OCL detector 1200 may determine whether the magnitude of the inductor current IIND reaches the OCL level.
The adaptive OCL controller 1300 increases the size of the OCL control current IOCL of the variable current source 1360 when the number of consecutive occurrences of the OCL detection voltage VOCL exceeds the reference number. The adaptive OCL controller 1300 reduces the size of the OCL control current IOCL of the variable current source 1360 when the number of consecutive occurrences of the reset voltage VRST exceeds the reference number.
To this end, the 4-bit counter 1310 may count the number of consecutive occurrences of the OCL detection voltage VOCL. When the OCL detection voltage Vou continuously occurs 16 times, the 4-bit counter 1310 transitions the data input terminal ‘D’ of the D flip-flop 1320 to a high level. Then, the data output terminal ‘Q’ of the D flip-flop 1320 is output at a high level, and the up voltage VUP is provided at a high level to count up the up-and-down counter 1350. Subsequently, the 4-bit counter 1310 and the D flip-flop 1320 are reset by the delay 1325. Here, the 4-bit counter 1310 may be modified into various bit sizes as needed. For example, if the 4-bit counter 1310 is replaced with a 3-bit counter, the up-and-down counter 1350 will be counted up when the OCL detection voltage VOCL occurs 8 times consecutively.
Also, the 4-bit counter 1330 may count the number of consecutive occurrences of the reset voltage VRST. When the reset voltage VRST occurs 16 times consecutively, the 4-bit counter 1330 transitions the data input terminal ‘D’ of the D flip-flop 1340 to a high level. Then, the data output terminal ‘Q’ of the D flip-flop 1340 is output at a high level, and the up-and-down counter 1350 is counted down by the down voltage VDN of the high level. Subsequently, the 4-bit counter 1330 and the D flip-flop 1340 are reset by the delay 1345. Here, the 4-bit counter 1330 may also be changed to the same bit size as the 4-bit counter 1310.
The up-and-down counter 1350 counts up or down a predetermined bit value based on the up voltage VUP and the down voltage VDN. The size of the OCL control current IOCL generated by the variable current source 1360 may be increased or decreased according to the count value ‘n’ of the up-and-down counter 1350. As a result, when pulses of the OCL detection voltage VOCL are continuously generated 16 times, the magnitude of the OCL control current IOCL increases. On the other hand, when the reset voltage VRST is continuously generated 16 times, the size of the OCL control current IOCL decreases.
The oscillator 1400 generates an oscillation voltage VOSC. A frequency of the oscillation voltage VOSC varies based on the magnitude of the OCL control current IOCL. The oscillation current source 1410 provides an oscillation current IOSC for charging the oscillation capacitor COSC. As the oscillation capacitor COSC is charged by the oscillation current IOSC, the node voltage VSAW formed across the oscillation capacitor COSC is generated as a ramp waveform or a sawtooth waveform with a constant slope.
When the node voltage VSAW rises and reaches the oscillation reference voltage VOSC,REF, the oscillation voltage VOSC is generated by the comparator 1420. The oscillation voltage VOSC is formed as a pulse voltage by the SR latch 1430, the delay 1440, and the discharge switch MR. That is, when the oscillation voltage VOSC is output to a high level, the reset input terminal of the SR latch 1430 is set to a high level, and the inverted output terminal ‘/Q’ also transitions to a high level. Then, the discharge switch MR is turned on and the node voltage VSAW formed across both ends of the oscillation capacitor COSC is lowered to the ground level by discharging. The delay 1440 delays the inverting output terminal ‘/Q’ to transition the SR latch 1430 to the set state. Then, the discharge switch MR is turned off again, and the node voltage VSAW starts to rise.
The switching frequency fSW of the inductor current Ism can be varied by the adaptive OCL controller 1300 and the oscillator 1400 of the present disclosure. Through the adjustment of the switching frequency fSW, it is possible to supply a sufficient amount of energy to the load despite the limitation of the OCL level. Therefore, it is possible to provide a load current supply capability that cannot be achieved only by adjusting the duty cycle of the duty voltage VDUT driving the switching transistors 1800 (see
At time T0, as the level of the inductor current IIND increases to reach the OCL level, the OCL detection voltage VOCL starts to be generated. However, the count of the 4-bit counter 1310 of the adaptive OCL controller 1300 has only started, and the value of the up-and-down counter 1350 has not changed. Accordingly, the OCL control current IOCL generated by the variable current source 1360 maintains the initial value ‘I0’. The OCL detection voltage VOCL continuously occurs 16 times until the time point T1.
At time T1, the count value of the 4-bit counter 1310 reaches ‘1111’ according to 16 consecutive occurrences of the OCL detection voltage VOCL from time TO. Then, a pulse of the up voltage VUP is generated by the first D flip-flop 1320. Synchronized with the generation of the up voltage VUP, the up-and-down counter 1350 counts up. According to the count-up of the up-and-down counter 1350, the OCL control current IOCL generated from the variable current source 1360 is generated with a size increased by a predetermined step ‘A’ from the initial value ‘I0’.
At time T2, the count value of the 4-bit counter 1310 is counted up from ‘0000’ to ‘1111’ as the OCL detection voltage VOCL additionally occurs continuously 16 times from time T1 to time T2. Then, a pulse of the second up voltage VUP is generated by the first D flip-flop 1320. Synchronized with the generation of the up voltage VUP, the up-and-down counter 1350 is counted up again. As the up-and-down counter 1350 counts up, the OCL control current IOCL generated from the variable current source 1360 increases to ‘I0+2Δ’.
From time T2 to time T3, as the reset voltage VRST occurs 16 times in succession, the count value of the 4-bit counter 1330 counts up from ‘0000’ to ‘1111’. Then, the first down voltage VDN pulse is generated by the D flip-flop 1340. Synchronized with the occurrence of the first down voltage VDN, the up-and-down counter 1350 counts down from the previous count value. As the up-and-down counter 1350 counts down, the magnitude of the OCL control current IOCL generated from the variable current source 1360 decreases to ‘I0+Δ’.
From time T3 to time T4, as the reset voltage VRST occurs again 16 times in succession, the count value of the 4-bit counter 1330 counts up from ‘0000’ to ‘1111’. Then, a second down voltage VDN pulse is generated by the D flip-flop 1340 at the time T4. Synchronized with the generation of the second down voltage VDN, the up-and-down counter 1350 counts down from the previous count value. As the up-and-down counter 1350 counts down, the magnitude of the OCL control current IOCL generated from the variable current source 1360 decreases to ‘I0’.
In the above descriptions, the method of generating the OCL control current IOCL of the adaptive OCL controller 1300 has been described as an example. The adaptive OCL controller 1300 generates an OCL control current IOCL having a variable level based on the number of consecutive occurrences of the OCL detection voltage VOCL or the reset voltage VRST. The frequency of the oscillation voltage VOSC or the switching frequency fSW may be adjusted according to the increase or decrease of the OCL control current IOCL.
Before time t1, the battery charger IC 1000 is in a light load current condition. In addition, the load current ISYS required by the system of the mobile device 100 rises at the time point t1. That is, the battery charger IC 1000 is in a heavy load current condition after time t1.
Under light load current conditions, the magnitude of the inductor current IIND will not reach the OCL level even though there is ripple due to switching. At this time, although ripples exist in the inductor current IIND due to switching, the average inductor current IIND,AVG maintains a low state ‘IIA0’. Accordingly, the reset voltage VRST of the control loop circuit 1100 is generated according to a comparison result between the error voltage VERR and the ramp voltage VRMP. That is, whenever the ramp voltage VRMP reaches the error voltage VERR, a reset voltage VRST pulse is generated.
The number of pulses of the reset voltage VRST may be accumulated and counted by the adaptive OCL controller 1300. Also, since there is no increase or decrease in the OCL control current IOCL before the time t1, the slope of the node voltage VSAW of the oscillator 1400 will maintain the ‘a’ value. The slope of the node voltage VSAW ‘α’ may be expressed by Equation 1 below.
Here, ‘IOSC’ represents the magnitude of the oscillation current that sets the basic slope, and ‘COSC’ represents the capacity of the oscillation capacitor for charging the current (see
At the time t1, the load current ISYS required by the system increases. As a result, when more power delivery to the load is required, the magnitude of the inductor current END increases and reaches to the OCL level. Then, the error voltage VERR in the control loop circuit 1100 increases. The reset voltage VRST of the control loop circuit 1100 is generated according to a comparison result between the error voltage VERR and the ramp voltage VRMP. Therefore, as the error voltage VERR becomes higher than the ramp voltage VRMP, the reset voltage VRST cannot be generated.
Instead, an OCL detection voltage VOCL pulse generated when the magnitude of the inductor current IIND reaches the OCL level in the OCL detector 1200 is generated. The OCL detection voltage VOCL pulse starts to occur at time t2. The number of continuously occurring OCL detection voltage VOCL pulses may be accumulated and counted by the adaptive OCL controller 1300. The number of OCL detection voltage VOCL pulses has not yet reached the count value that increases the OCL control current IOCL. Accordingly, the slope of the node voltage VSAW for generating the sawtooth wave of the oscillator 1400 will maintain the ‘a’ value. In this state, the frequency of the oscillation voltage VOSC generated by the oscillator 1400 may still maintain the first switching frequency ‘fSW1’. However, the number of counted OCL detection voltage VOCL pulses gradually increases, and a count value that increases the OCL control current IOCL will be reached.
After the time point t3, waveforms after the number of OCL detection voltage VOCL pulses reach a count value (e.g., 16) for increasing the OCL control current IOCL are shown. When the number of OCL detection voltage VOCL pulses reaches the count value (e.g., 16) that increases the OCL control current IOCL, the slope of the node voltage VSAW for generating the sawtooth wave of the oscillator 1400 is ‘β (>α)’. The slope of the node voltage VSAW ‘β’ may be expressed by Equation 2 below.
Here, ‘IOSC’ represents the size of the oscillation current that sets the basic slope, ‘COSC’ represents the capacity of the oscillation capacitor for charging the current, and ‘IOCL’ represents the size of the OCL control current (see
In addition, the OCL detection voltage VOCL pulse by the OCL detector 1200 is also generated by the increase of the switching frequency and the increased average inductor current That is, the OCL detection voltage VOCL pulse generated when the inductor current IIND reaches the OCL level is alternately generated with the reset voltage VRST pulse. In this case, the number of counts of each of the reset voltage VRST and the OCL detection voltage VOCL in the adaptive OCL controller 1300 cannot reach a level at which the OCL control current IOCL is varied. That is, the frequency of the oscillation voltage VOSC generated by the oscillator 1400 is locked to the switching frequency ‘fSW2’ formed at the time t3.
As the switching frequency ‘fSW2’ is fixed at a higher value, the size of ripple due to switching of the inductor current IIND decreases. In addition, the level of the average inductor current ‘IIA2’ is also increased than before the time point t1 to approach the overcurrent limit level. This may indicate that more power can be delivered by increasing the amount of current delivered to the system or load.
In operation S110, the OCL detector 1200 senses the inductor current IIND. Detection of the magnitude of the inductor current IIND by the OCL detector 1200 may be performed using separate devices such as, for example, the current sensor 1050 (see
In operation S120, an operation branch occurs according to a comparison result between the magnitude of the detected inductor current IIND peak and the OCL level. If the magnitude of the inductor current IIND peak is greater than the OCL level (‘Yes’ direction), the procedure moves to operation S130. On the other hand, if the magnitude of the detected inductor current IIND peak is not greater than the OCL level (‘No’ direction), the procedure moves to operation S160.
In operation S130, when the peak level of the sensed inductor current IIND is greater than the OCL level, the OCL detector 1200 generates an OCL detection voltage VOCL pulse.
In operation S140, it is checked whether OCL detection voltage VOCL pulses are continuously generated. If OCL detection voltage VOCL pulses continuously occur (‘Yes’ direction), the process moves to operation S145. On the other hand, when OCL detection voltage VOCL pulses are not continuously generated (No′ direction), the procedure returns to operation S120.
In operation S145, the number of consecutive OCL detection voltage VOCL pulses is counted. For example, a 4-bit counter may be used as an element for counting the number of consecutive OCL detection voltage VOCL pulses.
In operation S150, it is checked whether the number of consecutive OCL detection voltage VOCL pulses reaches the maximum value ‘nUP’. When counting the number of OCL detection voltage VOCL pulses using a 4-bit counter, the maximum value ‘nUP’ may be 16 (=24). If the number of OCL detection voltage VOCL pulses reaches the maximum value ‘nUP’ (‘Yes’ direction), the process moves to operation S152. On the other hand, if the number of OCL detection voltage VOCL pulses does not reach the maximum value ‘nUP’ (direction ‘No’), the process returns to operation S120.
In operation S152, the up-and-down counter 1350 of the adaptive OCL controller 1300 is counted up.
In operation S154, when the up-and-down counter 1350 of the adaptive OCL controller 1300 counts up, the up-and-down counter 1350 increases the size of the OCL control current IOCL of the variable current source 1360.
In operation S156, the OCL pulse counter is reset and the procedure returns to operation S120.
In operation S160, since the magnitude of the inductor current Iii does not reach the OCL level, a reset voltage VRST pulse is generated by the control loop circuit 1100. The reset voltage VRST of the control loop circuit 1100 is generated according to a comparison result between the error voltage VERR and the ramp voltage VRMP. That is, whenever the ramp voltage VRMP reaches the error voltage VERR, a reset voltage VRST pulse is generated.
In operation S170, it is checked whether reset voltage VRST pulses are continuously generated. If the reset voltage VRST pulses are continuously generated (‘Yes’ direction), the process moves to operation S175. On the other hand, if the reset voltage VRST pulses are not continuously generated (‘No’ direction), the process returns to operation S120.
In operation S175, the number of consecutive reset voltage VRST pulses is counted. For example, a 4-bit counter may be used as a means to count the number of reset voltage VRST pulses.
In operation S180, it is checked whether the number of consecutive reset voltage VRST pulses reaches the maximum value ‘nDN’. When counting the number of reset voltage VRST pulses using a 4-bit counter, the maximum value ‘nDN’ may be 16 (=24). If the number of reset voltage VRST pulses reaches the maximum value ‘nDN’ (‘Yes’ direction), the process moves to operation S182. On the other hand, if the number of reset voltage VRST pulses does not reach the maximum value ‘nDN’ (direction ‘No’), the process returns to operation S120.
In operation S182, the up-and-down counter 1350 of the adaptive OCL controller 1300 is counted down.
In operation S184, when the up-and-down counter 1350 of the adaptive OCL controller 1300 counts down, the up-and-down counter 1350 reduces the size of the OCL control current IOCL of the variable current source 1360.
At operation S186, the reset voltage pulse counter is reset and the procedure returns to operation S120.
In the above, the process of increasing or decreasing the OCL control current IOCL by counting the number of reset voltage VRST and OCL detection voltage VOCL pulses of the adaptive OCL controller 1300 has been described. The oscillator 1400 may generate an oscillation voltage VOSC having a variable switching frequency fsw according to the increasing or decreasing OCL control current IOCL.
At time T0, the load current ISYS required by the system of the mobile device 100 (see
From the time point T1, the level of the inductor current IIND starts to reach the OCL level. Then, the error voltage VERR in the control loop circuit 1100 increases. The reset voltage VRST of the control loop circuit 1100 is generated according to a comparison result between the error voltage VERR and the ramp voltage VRMP. As the error voltage VERR becomes higher than the ramp voltage VRMP, generation of the reset voltage VRST is stopped. Instead, the OCL detection voltage VOCL pulse generated when the magnitude of the inductor current IIND reaches the OCL level in the OCL detector (1200, see
And, the number of OCL detection voltage VOCL pulses continuously occurring will be accumulated and counted by the adaptive OCL controller (1300, see
At time T2, the error voltage VERR starts to decrease again as the switching frequency fSW increases. Generation of the reset voltage VRST starts again by the lowered error voltage VERR. That is, from the time T2, the OCL detection voltage VOCL and the reset voltage VRST are alternately generated. That is, neither the OCL detection voltage VOCL pulse nor the reset voltage VRST pulse is continuously generated. Accordingly, as the magnitude of the OCL control current IOCL is fixed, locking of the switching frequency fSW occurs from time T2 to time T3 as a result. In addition, the magnitude of the charging current IBAT is also restored to a level similar to that before the rise of the load current ISYS.
At time T3, a generation of the OCL detection voltage VOCL pulse stops as the load current ISYS decreases, and only the reset voltage VRST pulse is generated. Then, as the count number of reset voltage VRST pulses increases, the magnitude of the OCL control current IOCL decreases. As a result, the switching frequency fSW of the inductor current film) will start to decrease from the time point T3.
Because the switching frequency fSW of the inductor current IIND can be increased as the load current ISYS increases, the size of the average inductor current that is switched can be increased. Accordingly, the battery charger IC 1000 of the present disclosure can deliver a lot of energy to the load despite the overcurrent limit for protection.
The power system 2000 may be used to supply power to a mobile device or to supply power to an OTG device. In the power system 2000, when a travel adapter is connected to the charging terminal 2050, the battery charger IC 2100 operates in a buck mode. That is, in the buck mode, the battery charger IC 2100 operates in a buck converter or charger mode in which the battery 2300 is charged by switching power provided through the travel adapter.
On the other hand, when an OTG device is connected to the charging terminal 2050, the battery charger IC 2100 operates in a boost mode or OTG mode. That is, in the boost mode, the battery charger IC 2100 may switch power charged in the battery 2300 to provide the boosted voltage to the OTG device. Configuration and operations of the battery charger IC 2100 according to an embodiment of the present disclosure may operate as described in
The power management IC 2200 may receive power from the battery charger IC 2100. For example, the power management IC 2200 may convert a voltage provided from the battery charger IC 2100 into a stable voltage. The power management IC 2200 may provide a stable voltage to other components of the mobile electronic device. Each of the processor 2400, the input/output interface 2500, the buffer memory 2600, the storage 2700, the display 2800, and the communication module 2900 included in the mobile electronic device are supplied from the power management IC 2200. It can operate using a stable voltage.
As an example, each of the battery charger IC 2100 or the power management IC 2200 may be implemented as an integrated circuit chip. Each of the battery charger IC 2100 or the power management IC 2200 may be mounted using various types of semiconductor packages. As an example, the battery charger IC 2100 or the power management IC 2200 may include Package on Package (PoP), Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), Plastic Leaded Chip Carrier (PLCO), and Plastic Leaded Chip Carrier (PDIP). Dual In-line Package), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-line Package (CERDIP), Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP).
The above are specific embodiments for carrying out the present disclosure. In addition to the above-described embodiments, the present disclosure may include simple design changes or easily changeable embodiments. In addition, the present disclosure will include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, and should be defined by the claims and equivalents of the claims of the present disclosure as well as the claims to be described later.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0138102 | Oct 2022 | KR | national |
