Patent Application
20240178558
The present disclosure relates to a beamforming antenna device, and more particularly, to a beamforming antenna device having a distributed sub-array network.
In modern wireless communication technologies, satellite communications has become competitive for it provides better signal coverage and higher bandwidth as compared to conventional terrestrial communication technologies. To achieve the satellite communications, phased-array antennas that can achieve beamforming is demanded. Generally, the beamforming may be achieved by properly adjusting the relative phases and gains transmitted and/or received by each element of the phased array antenna. However, it can be challenging to design a hardware system for processing all the signals transmitted and received by the phased-array robustly and flexibly.
This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.
One aspect of the present disclosure provides a beamforming antenna device. The beamforming antenna device includes a plurality of antenna elements, and a plurality of sub-arrays. The sub-arrays are coupled to the plurality of antenna elements, wherein each of the sub-arrays is coupled to its adjacent sub-arrays of the plurality of sub-arrays, and at least a portion of the plurality of sub-arrays form a sub-array chain.
Another aspect of the present disclosure provides a method for operating a beamforming antenna device. The beamforming antenna device includes a plurality of antenna elements and a plurality of sub-arrays coupled to the antenna elements. The method includes propagating a clock signal originated from a master sub-array of the plurality of sub-array sequentially through the rest of the plurality of sub-arrays in a manner of node-to-node transmission, receiving a plurality of antenna signals by the plurality of antenna elements, deriving in-phase signals by utilizing at least a portion of the plurality of sub-arrays in a sub-array chain to perform phase align operations according to antenna signals received by antenna elements that are coupled to the sub-arrays in the sub-array chain, and aggregating the in-phase signals along the sub-array chain to generate a beamformed signal.
Since the beamforming antenna device provided by the embodiments of the present disclosure has a distributed structure, it allows the user to flexibly configure the data path for in-phase signal aggregation. For example, a sub-array chain structure can be implemented by configuring the sub-arrays in the beamforming antenna devices. In such case, each sub-arrays only requires a small number of input/output ports (i.e., low fan-in/fan-out). Furthermore, the structure of chain node also provides great extensibility. That is, when the size of the phased-array increases, the chain node can extend its support by simply cascading more sub-arrays to the chain. In addition, with the flexible structure of the sub-array network, a bypass path can be provided when a sub-array in the sub-array chain is failed, thereby improving the reliability of the beamforming antenna device.
A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims when considered in connection with the Figures, where like reference numbers refer to similar elements throughout the Figures.
The following description of the disclosure accompanies drawings, which are incorporated in and constitute a part of this specification, and which illustrate embodiments of the disclosure, but the disclosure is not limited to the embodiments. In addition, the following embodiments can be properly integrated to complete another embodiment.
References to “one embodiment,” “an embodiment,” “exemplary embodiment,” “other embodiments,” “another embodiment,” etc. indicate that the embodiment(s) of the disclosure so described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Further, repeated use of the phrase “in the embodiment” does not necessarily refer to the same embodiment, although it may.
In order to make the present disclosure completely comprehensible, detailed steps and structures are provided in the following description. Obviously, implementation of the present disclosure does not limit special details known by persons skilled in the art. In addition, known structures and steps are not described in detail, so as not to unnecessarily limit the present disclosure. Preferred embodiments of the present disclosure will be described below in detail. However, in addition to the detailed description, the present disclosure may also be widely implemented in other embodiments. The scope of the present disclosure is not limited to the detailed description, and is defined by the claims.
In a receiving mode, the antenna elements 110_1_1 to 110_N_X may receive antenna signals SA1_1 to SAN_X. Since the signals SA1_1 to SAN_X may have different delays (i.e., corresponding to different phases), the beamforming antenna device 100 needs to align the phases of the received signals SA1_1 to SAN_X and aggregate the in-phase signals so as to generate the beamformed signal.
In such case, the antenna signals SA1_1 to SAN_X can be transmitted to the corresponding phase-align arrays 120_1 to 120_N for frontend processing and analog-to-digital conversion. For example, the phase-align array 120_1 may receive the signals SA1_1 to SA1_X received by the antenna elements 110_1 to 110_X, the phase-align array 120_2 may receive the signals SA2_1 to SA2_X received by the antenna elements 110_2_1 to 110_2_X, and so on. After the analog-to-digital conversion, the phase-align arrays 120_1 to 120_N can perform phase align operations to the digital signals so as to generate the in-phase signals of the antenna signals.
Afterwards, the phase-align arrays 120_1 to 120_N can further aggregate the in-phase signals to generate partial aggregation result A_1 to A_N respectively, and the sub-arrays 130 can further aggregate the partial aggregation results received from the corresponding phase-align arrays. Finally, the root sub-array 131 can aggregate all the partial aggregation results so that the beamformed signal can be derived accordingly.
According to the tree structure of the beamforming antenna device 100 shown in
To tackle the issues caused by the tree structure, one embodiment of the present disclosure provides a multi-dimension sub-array network, which allows to align the signal phases and aggregate the in-phase signals in a chain structure.
It is noted that the beamforming antenna device is not limited to the embodiments as shown in
In the present embodiment, each of the sub-arrays 622 can include a plurality of switch units for controlling its electrical connections to the adjacent sub-arrays 622, therefore, each sub-array 622 is allowed to receive signals or data from any of its adjacent sub-arrays, and to transmit signals or data to any of its adjacent sub-arrays. In some embodiments, instead of being disposed within the sub-array 622, the switch units for controlling the electrical connection between adjacent sub-arrays 622 may also be disposed outside of the sub-arrays 622 (i.e., outside of the FPGA).
The distributed structure of the sub-array network 620 provides the user with great flexibility and extensibility when creating the data processing paths. That is, by properly configuring the switch units of the sub-arrays 622, desired data paths can be formed to aggregate the received antenna signals so as to derive the beamformed signal. Also, when the size of the phased array is changed, a corresponding data path can also be configured accordingly. That is, in addition to the tree structure adopted by the beamforming antenna device 100, the sub-array network 620 allows the user to build other types of data paths flexibly.
For example, in some embodiments, a chain structure can be built with some of the sub-arrays 622 in the sub-array network 620 for performing phase alignment and signal aggregation.
In the present embodiment, the sub-arrays 622_1 to 622_N in the sub-array chain C1 can be coupled to a portion of the antenna elements 610 for receiving antenna signals and forming a corresponding beam. As shown in
In the receiving mode, the sub-arrays 622_1 to 622_N in the sub-array chain C1 can derive in-phase signals by performing phase align operations according to the antenna signals SA1_1 to SAN_X, and aggregate the in-phase signals along the sub-array chain C1 to generate the beamformed signal.
For example, as shown in
Similarly, the sub-array 622_2 can derive the in-phase signals SB2_1 to SB2_X according to antenna signals SA2_1 to SA2_X received by antenna elements 610 coupled to the sub-array 622_2. Furthermore, the sub-array 622_2 can receive the partial aggregation result PA1 from the sub-array 622_1, and combine the partial aggregation result PA1 and the in-phase signals SB2_1 to SB2_X to generate a partial aggregation result PA2. In such case, the partial aggregation result PA2 is substantially equal to the aggregation result of the in-phase signals SB1_1 to SB1_X and SB2_1 to SB2_X.
The partial aggregation result PA2 is then transmitted to the sub-array 622_3, and the sub-array 622_3 can further aggregate the partial aggregation result PA2 with the in-phase signals SB3_1 to SB3_X derived according to the antenna signals SA3_1 to SA3_X, and so on. As a result, the aggregation of all in-phase signals can be achieved along the sub-array chain C1, and the beamformed signal can thus be derived according to the final aggregation result generated by the sub-array 622_N.
Since the structure of the sub-array chain C1 allows to achieve beamforming with each sub-array 622_1 to 622_N receiving data from only one other sub-array, the number of input/output ports (e.g., the number of SERDES ports) required by the sub-arrays 622_1 to 622_N can be significantly reduced. Furthermore, due to the flexibility provided by the beamforming antenna device 600, it is also feasible to form bypass paths along the sub-array chain C1, and thus, the sub-array chain C1 can be protected from broken by a single node failure.
In
Specifically, in a normal state, the switch unit SW1 can be configured to transmit the partial aggregation result PA1 outputted by the sub-array 622_1 to the processing units of the sub-array 622_2 so that the partial aggregation result PA1 can be combined with the in-phase signals SB2_1 to SB2_X. Afterwards, the switch unit SW2 can transmit the partial aggregation result PA2 generated by the sub-array 622_2 to the sub-array 622_3.
However, in a bypass state, the switch unit SW2 can be configured to transmit the partial aggregation result PA1 outputted by the sub-array 622_1 to the sub-array 622_3 directly without aggregating other signals.
In the present embodiment, the switch units in the sub-arrays 622 can be multiplexers and can be configured to change its state during the processing of the beamforming antenna device 600, therefore, the data paths of the sub-array chain C1 can be refined dynamically, thereby reducing the failure rate and improving the reliability. Furthermore, in addition to the data paths for beamforming signals, the sub-arrays may further include more switch units for controlling other signal paths. For example, the clock signal CK1 and the system reference signal SR1 that are used for synchronizing the sub-arrays 622 can be propagated in a node-to-node, in which one node may represent one sub-array, manner by configuring the corresponding switch units in the sub-arrays 622 of the sub-array network 620.
In the present embodiments, since each sub-array 622 may be implemented by a FPGA, clock domains of the sub-arrays 622 can be independent of each other. In such case, to synchronize all the sub-arrays 622 in the sub-array network 620, a master sub-array 622 may be selected to provide a clock signal CK1. For example, as shown in
In some embodiments, since all the sub-arrays 622 in the sub-array network 620 can have the similar structure, all the sub-arrays 622 may include a clock source that is able to provide the clock signal. In such case, all the sub-arrays 622 may be a candidate of the master sub-array or master node, and each of the sub-arrays 622 may adopt an clock switch unit to select a clock input signal from its neighboring sub-array 622 or the clock signal generated by its own clock source depending on whether it has been selected to be the master sub-array or not.
Also, when the sub-array chain C1 is activated to receive the antenna signals, the system reference signal SR1 may be transmitted to notify the sub-arrays 622 in the sub-array chain C1 for performing the phase align operations synchronously. In some embodiments, the system reference signal SR1 can also be generated by the master node, and can be sequentially propagated through the rest of the sub-arrays 622 in the manner of node-to-node transmission.
Next, the clock signal CK1 and the system reference signal SR1 can be propagated to the sub-arrays 622_1 to 622_N in the sub-array chain C1 in step S120 and S130. In such case, the sub-arrays 622_1 to 622_N in the sub-array chain C1 would begin to receive the antenna signals received by the antenna elements 610 that are coupled to the sub-arrays 622_1 to 622_N in step S140. In step S150, the sub-arrays 622_1 to 622_N can derive the in-phase signals of the antenna signals by performing the phase align operations. Finally, in step S160, the sub-arrays 622_1 to 622_N can aggregate the in-phase signals along the sub-array chain C1 so as to generate the beamformed signal.
In some embodiments, since timing differences and the phase differences may be caused by the transmission along the sub-array chain C1, it can be crucial for the sub-arrays 622_1 to 622_N to compensate the timing difference and the phase difference when deriving the in-phase signals. In such case, to synthesize the delays on each sub-arrays 622 in the sub-array network 620 for calibration can help to improve the accuracy of beamforming.
In some embodiments, the delays on each sub-arrays 622 in the sub-array network 620 can be synthesized according to the summation of near-by delays between adjacent sub-arrays (i.e., the timing difference and the phase difference caused by transmission between two adjacent sub-arrays). More details about the calibration operation will be introduced with
In such case, the selected clock signal outputted by the multiplexer MUX1 can be fed to the data process unit A1, the analog-to-digital converter B1, and the digital-to-analog converter B2 of the sub-array 722_1. Furthermore, the selected clock signal can be outputted to the clock output terminals CKOT1 and CKOT2 so as to propagate the clock signal to other sub-arrays adjacent to the sub-array 722_1. However, in some cases, if the sub-array 722_1 is not enabled for signal processing, then the clock received by the clock input terminals CKIT1 and CKIT2 may be bypassed to the clock output terminals CKOT1 and CKOT2 through the multiplexer MUX2 and MUX3. In some embodiments, the clock network of the sub-array 722_1 may include more clock input terminals and/or more clock output terminals according to the number of adjacent sub-arrays that are coupled to the sub-array 722_1 in the beamforming antenna device.
In such case, the selected system reference signal outputted by the multiplexer MUX4 can be fed to the data process unit A1, the analog-to-digital converter B1, and the digital-to-analog converter B2 of the sub-array 722_1. Furthermore, the selected system reference signal can be outputted to the system output terminals SROT1 and SROT2 so as to propagate the system reference signal to other sub-arrays adjacent to the sub-array 722_1. However, in some cases, if the sub-array 722_1 is not enabled for signal processing, then the system reference signal received by the system input terminals SRIT1 and SRIT2 may be bypassed to the system output terminals SROT1 and SROT2 through the multiplexer MUX5 and MUX6. In some embodiments, the system signal network of the sub-array 722_1 may include more system input terminals and/or more system output terminals according to the number of adjacent sub-arrays that are coupled to the sub-array 722_1 in the beamforming antenna device.
As shown in
In the present embodiment, each of the frontend circuits 922C_1 to 922C_N can receive signals from an antenna element (not shown) in the receiving mode and transmit signals to the antenna element in the transmitting mode. Each of the data conversion circuits 922B_1 to 922B_N can convert an analog receiving signal into a digital receiving signal for processing in the receiving mode and convert a digital transmitting signal into an analog transmitting signal for transmission in the transmitting mode. Each of the data processing units 922A_1 to 922A_N is coupled to a corresponding data conversion circuit of the data conversion circuits 922B_1 to 922B_N, and can perform a phase align operation to the digital receiving signal in the receiving mode and generate the digital transmitting signal in the transmitting mode.
For example, in the transmitting mode, the data process unit 922A_1 may transmit a digital transmitting signal to the data conversion circuit 922B_1, and the data conversion circuit 922B_1 can convert the digital transmitting signal into an analog transmitting signal and send it to the frontend circuit 922C_1 through the switches 922D_1 and 922E_1. Finally, the frontend circuit 922C_1 can send the analog transmitting signal to the corresponding antenna element 110 for transmission.
Also, in the receiving mode, the frontend circuit 922C_1 may receive the analog receiving signal from the corresponding antenna element, and the analog receiving signal can be transmitted to the data conversion circuit 922B_1 through the switches 922D_1 and 922E_1. The data conversion circuit 922B_1 can convert the analog receiving signal into a digital receiving signal so that the data processing unit 922A_1 can process the digital receiving data to derive the in-phase signal accordingly.
In the transmitting mode, the switches 922D_1 and 922E_1 of the sub-array 922_1 may lead the analog transmitting signal from the data conversion circuit 922B_1 to the frontend circuit 922C_1 for transmission. However, to synthesize the near-by transmitting delay between the two adjacent sub-arrays in a transmitting calibration mode, the analog transmitting signal generated by one sub-array may be transmitted to a frontend circuit of another sub-array through the switches of the sub-arrays.
For example, in the transmitting calibration mode, the sub-array 922_1 can send a first test signal to the frontend circuit 922C_N of the sub-array 922_2, and the sub-array 922_2 can send a second test signal to the frontend circuit 922C_N of the sub-array 922C_N so as to estimate a transmitting delay between the sub-array 922_1 and the sub-array 922_2.
Specifically, in the transmitting calibration mode, the data process unit 922A_1 of the sub-array 922_1 can transmit the first test signal (e.g., a training sequence such as a chirp signal) to the frontend circuit 922C_N of the sub-array 922_2 through the data conversion circuit 922B_1, the switch 922D_1 of the sub-array 922_1, and the switch 922E_N of the sub-array 922_2. After the frontend circuit 922C_N receives the first test signal, it can further transmit the received signal to the data processing unit 922A_N of the sub-array 922_2 through the switches 922D_N′ and 922E_N′ and the data conversion circuit 922B_N′ in the calibration path 904 of the sub-array 922_2.
Next, the data process unit 922A_N of the sub-array 922_2 can also transmit a second test signal, which has a same waveform as that of the first test signal, to the frontend circuit 922C_N of the first sub-array 922_2 with the aid of the switches 922D_N and 922_E_N of the sub-array 922_2. After the frontend circuit 922C_N of the sub-array 922_2 receives the second test signal, it can further transmit the received signal to the data processing unit 922A_N of the sub-array 922_2 through the switches 922D_N′ and 922E_N′ and the data conversion circuit 922B_N′ in the calibration path 904 of the sub-array 922_2.
In such case, the waveforms of the first test signal and the second test signal received by the sub-array 922_2 may turn out to have different waveforms due to the near-by delay. In some embodiments, the sub-array network 920 may transform the waveforms from the time domain to the frequency domain by using Fast Fourier Transform (FFT) so as to estimate the timing difference and the phase difference between the signals received by the sub-array 922_2. Consequently, the near-by transmitting delay between these two sub-arrays 922_1 and 922_2 can be estimated.
With similar approaches, the sub-array network 920 is able to estimate all the near-by transmitting delays between adjacent sub-array, and thus, the breamforming antenna device 920 can further obtain the transmitting delay for each of the sub-array 922 in the sub-array chain C2 with respect to the reference sub-array (e.g., the sub-array 922_1) according to all the estimated the near-by delays. For example, if a near-by delay between the sub-arrays 922_i and 922_(i+1) is denoted as Ui, where i is a positive integer smaller than N, then the receiving delay of the sub-array 922_N with respect to the sub-array 922_1 would be Σi=1i=N-1Ui.
In addition, in a receiving calibration mode, the sub-array 922_1 can send a first test signal to the frontend circuit 922C_1 of the sub-array 922_1 and send a second test signal, which has a same waveform as that of the first test signal, to the frontend circuit 922C_N of the sub-array 922_2 so as to estimate a receiving delay between the sub-array 922_1 and the sub-array 922_2.
For example, in the receiving calibration mode, the data process unit 922A_1 of the sub-array 922_1 may transmit a first test signal to the frontend circuit 922C_1 of the sub-array 922_1 through the data conversion circuit 922B_1, the switches 922D_1 and 922E_1 in the main path 902 of the sub-array 922_1. After the frontend circuit 922C_1 of the sub-array 922_1 receives the first test signal, it can further transmit the received signal to the data processing unit 922A_N of the sub-array 922_2 through the switch 922E_1′ of the sub-array 922_1 and the switch 922D_N′ and the data conversion circuit 922B_N′ in the calibration path 904 of the sub-array 922_2.
Next, the data process unit 922A_1 of the sub-array 922_1 can also transmit a second test signal to the frontend circuit 922C_N of the sub-array 922_2 with the aid of the switch 922D_1 of the sub-array 922_1 and the switch 922E_N of the sub-array 922_2. After the frontend circuit 922C_N receives the second test signal, it can further transmit the received signal to the data processing unit 922A_N of the sub-array 922_2 through the switches 922E_N′ and 922D_N′, and the data conversion circuit 922B_N′ of the sub-array 922_2. As a result, with the transmitting delay estimated previously, the sub-array network 920 can further estimate the receiving delay between the sub-array 922_1 and the sub-array 922_2 according to the waveforms of the signals received by the sub-array 922_2.
In the present embodiment, to present the calibration network of the sub-array network 920 in the calibration modes (i.e., the transmitting calibration mode and the receiving calibration mode aforementioned) clearly,
Furthermore, in some embodiments, the internal delays among the frontend circuits 922C_1 to 922C_N within the sub-array 922_1 may also be estimated by performing an intra-node calibration. In some embodiments, such internal delay can be synthesized with the aids of the first switches 922D_1 to 922D_N and the second switches 922E_1 to 922E_N.
As shown in
In an intra-node calibration mode of the sub-array 922_1, for example, the data process unit 922A_2 may transmit same test signals to the frontend circuits 922C_2 and 922C_1 through the switches 922D_2, 922E_2, and 922E_1, and the test signals can be transmitted to the data processing unit 922A_1 through the switches (not shown) in the calibration path 904, so that the intra-node delay between the frontend circuit 922C_2 and the frontend circuit 922C_1 can be estimated according to the waveforms of the signals received by the frontend circuits 922C_1 and 922C_2. Similar approaches can be applied to the rest of frontend circuits 922C_3 to 922C_N with respect to the sub-array 922_1 so as to obtain the full intra-node delay.
Although the switch unit SW3 shown in
By performing calibrations to estimate the delays on each sub-arrays in the sub-array chain, the phase alignment can be performed more accurately, thereby improving the quality of the beamformed signals.
In summary, the beamforming antenna devices provided by the embodiments of the present disclosure have distributed structures, and thus allow the user to flexibly configure the data path for in-phase signal aggregation. For example, a sub-array chain structure can be implemented by configuring the sub-arrays in the beamforming antenna devices. In such case, each sub-arrays only requires a small number of input/output ports (i.e., low fan-in/fan-out). Furthermore, the structure of sub-array chain also provides great extensibility. That is, when the size of the phased-array increases, the sub-array chain can extend its support by simply cascading more sub-arrays to the chain. In addition, with the flexible structure of the sub-array network, a bypass path can be provided when a sub-array in the sub-array chain is failed, thereby improving the reliability of the beamforming antenna device.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the operations discussed above can be implemented in different methodologies and replaced by other operations, or a combination thereof.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the operation, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, operations, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such operations, machines, manufacture, compositions of matter, means, methods, and steps.
This application claims the benefit of prior-filed U.S. provisional application No. 63/385,153, filed on Nov. 28, 2022, which is incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63385153 | Nov 2022 | US |
