Claims
- 1. A Bi-CMOS logic circuit comprising:
- first and second bipolar transistors connected in series between a first power source and a second power source, an output signal being drawing from a connection node at which said first and second bipolar transistors are connected in series;
- first impedance means, connected between the base and the emitter of said first bipolar transistor, for providing a first impedance;
- second impedance means, connected between the base of said second bipolar transistor and the emitter thereof, for providing a second impedance;
- a first MOS transistor connected between the collector of said first bipolar transistor and the base thereof;
- a second MOS transistor connected between the collector of said second bipolar transistor and the base thereof, an input signal being applied in common to the gates of said first and second MOS transistors; and
- a third MOS transistor connected between the base of said first bipolar transistor and said second power source, said third MOS transistor having a gate connected to the base of said second bipolar transistor.
- 2. A Bi-CMOS logic circuit as claimed in claim 1, wherein each of said second and third MOS transistors is an N-channel MOS transistor, and said first MOS transistor is a P-channel MOS transistor.
- 3. A Bi-CMOS logic circuit as claimed in claim 1, wherein each of said first and second impedance means comprises a resistor.
- 4. A Bi-CMOS logic circuit comprising:
- first and second bipolar transistors connected in series between a first power source and a second power source, an output signal being drawn from a connection node at which said first and second bipolar transistors are connected in series;
- first impedance means, connected between the base and the emitter of said first bipolar transistor, for providing a first impedance;
- second impedance means, connected between the base of said second bipolar transistor and the emitter thereof, for providing a second impedance;
- a first group of n MOS transistors connected in parallel between the base and collector of said first bipolar transistor where n is an integer, said n MOS transistors of the first group having respective gates respectively receiving n corresponding input signals;
- a second group of n MOS transistors connected in series between the base and the collector of said second bipolar transistor, said n MOS transistors of said second group having respective gates respectively receiving said corresponding n input signals; and
- a discharge MOS transistor connected between the base of said first bipolar MOS transistor and said second power source, said discharge MOS transistor having the gate thereof connected to the base of said second bipolar transistor.
- 5. A Bi-CMOS logic circuit as claimed in claim 1, wherein said n MOS transistors of the first group are respectively P-channel MOS transistors, and said n MOS transistors of the second group and said discharge MOS transistor are respectively N-channel MOS transistors.
- 6. A Bi-CMOS logic circuit as claimed in claim 4, wherein each of said first and second impedance means comprises a resistor.
Priority Claims (2)
Number |
Date |
Country |
Kind |
1-127402 |
May 1989 |
JPX |
|
1-281317 |
Oct 1989 |
JPX |
|
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation-in-part of application Ser. No. 525,058, filed May 18, 1990 for Bi-CMOS Logic Circuit, commonly assigned with the present invention.
US Referenced Citations (7)
Foreign Referenced Citations (2)
Number |
Date |
Country |
0099100 |
Jan 1984 |
EPX |
64-68021 |
Mar 1989 |
JPX |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
525058 |
May 1990 |
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