This invention relates to suppression of electrical transients.
It has long been known that electrical circuits and devices can be damaged by electrical transients at their inputs. Accordingly, transient suppression has been extensively investigated, and various approaches have been developed to date. One such approach is the use of a transient blocking unit (TBU), which is an arrangement of two or more normally-on transistors configured to switch off current flow in response to an over-voltage or over-current condition. One early reference describing TBUs is U.S. Pat. No. 5,742,463, by Richard A. Harris. TBUs are placed in series with the load being protected.
In many cases of interest, it is desirable for TBUs to be able to withstand high voltages in the current blocking state. One known configuration is where transistors Q1 and Q2 on
An improved bi-directional TBU is provided having a dual-gate central transistor. The gates of the central transistor are connected to the rest of the TBU such that high voltages can only appear between a gate and the central transistor terminal further from that gate. In this manner, the total device size required to provide a given breakdown voltage can be significantly reduced compared to a conventional symmetric lateral transistor having a single gate.
a shows a TBU according to an embodiment of the invention.
b shows an illustrative transistor device geometry suitable for use in embodiments of the invention.
c shows an exemplary device structure corresponding to the embodiment of
a shows dual gate geometry corresponding to the embodiment of
b shows a connection of a dual gate transistor that is not suitable for practicing the invention.
In order to better appreciate the present invention, it is helpful to consider the implications of designing the circuit of
Such symmetry of breakdown voltages is not often encountered in practice. Many high voltage transistors have a vertical geometry, where it is difficult or even impossible to design for symmetric breakdown voltages. In lateral device designs, it is easier to provide symmetric breakdown voltages, but the resulting designs tend to lead to costly devices.
This issue can be appreciated in connection with
This issue of large device size is one of the main reasons that known high voltage TBU circuits tend to have the two outer transistors (e.g., Q1 and Q2 on
However, it is possible to significantly alleviate the issue of large device size for a center HV transistor in a TBU by exploiting the following property of the TBU application: it is not required for the center transistor in a TBU to simultaneously provide high breakdown voltages between the gate and both other terminals T1 and T2. Instead, at some times (i.e., when T1 is acting as the drain) a high gate to T1 breakdown voltage is needed, and at other times (i.e., when T2 is acting as the drain), a high gate to T2 breakdown voltage is needed, depending on the polarity of the transient being blocked.
a shows a TBU according to an embodiment of the invention. A key aspect of this example is transistor Q6 being a dual-gate transistor and having gates G3 and G4. Since practice of the invention does not depend critically on the difference between source and drain, the drain/source terminals of the transistors are labeled as follows: transistor Q4 has terminals T1 and T2, transistor Q5 has terminals T3 and T4, and transistor Q6 has terminals T5 and T6. Transistors Q4 and Q5 have gates G1 and G2 respectively. Transistors Q4, Q5, and Q6 are all depletion mode transistors. Gate G1 controls a first current between terminals T1 and T2. Gate G2 controls a second current between terminals T3 and T4. Gates G3 and G4 are independent and both control a third current between terminals T5 and T6.
Terminal T2 is connected to T5, and T6 is connected to T3, so the three transistors are connected in series. The gate connections are as follows: G1 is connected to T3, G2 is connected to T2, G3 is connected to T1, and G4 is connected to T4. Terminals T1 and T4 are the input/output terminals of the TBU, which provides an automatic shut-off function of a controllable current from T1 to T4 responsive to an over-voltage or over-current condition. The TBU is thereby capable of protecting a load 104 from over-voltage or over-current conditions.
The significance of this example can be better appreciated in connection with
Suppose that a gate to terminal separation of at least Lmin is required to provide a specified breakdown voltage. With the arrangement of
In TBUs according to embodiments of the invention, it is preferred for the center transistor to be a high voltage transistor (e.g., breakdown voltage >50 V, more preferably breakdown voltage >100 V) as opposed to a low voltage device. It is further preferred for the center transistor to be a GaN high voltage transistor, such as a high electron mobility transistor (HEMT) or a metal-semiconductor field effect transistor (MESFET). The GaN material system is preferred for the center transistor, because it is difficult/costly to fabricate high performance HV lateral FETs in Silicon. For example, providing breakdown voltages above 50 V in a Silicon JFET tends to be highly cost ineffective. However, practice of the invention does not depend critically on material system or transistor type.
c shows an exemplary GaN HEMT device structure suitable for use in embodiments of the invention. In this example, source and drain 204 and 206, as well as gates 208 and 210 are disposed on an n-type AlGaN layer 212, which in turn is disposed on an undoped GaN substrate 214. Passivation layers 216a-c protect AlGaN layer 212. Dual gate transistors (e.g., as described above) are known in the art in relation to applications other than TBU circuits. For example, in U.S. Pat. No. 5,821,813 and in U.S. Pat. No. 6,801,088, one gate is used a signal input and the other gate is employed as a bias input. Use of one gate for signal and the other gate for bias is similar to the arrangement of a pentode tube, in which the gates are located at the same end of the device, and cathode and anode (corresponding to source and drain) are not reversible.
It is important in TBUs according to embodiments of the invention to connect the gates of the dual-gate transistor correctly to the remainder of the TBU circuit.
In contrast,
Therefore, the order of the gates as shown on the schematic of
More specifically, for negative ITBU exceeding a predetermined first threshold, a voltage between terminals T1 and T2 provides a voltage at G3 tending to switch off Q9, which then acts to switch off Q7, thereby shutting off the TBU. Similarly, for positive ITBU exceeding a predetermined second threshold, a voltage between terminals T3 and T4 provides a voltage at G4 tending to switch off Q9, which then acts to switch off Q8, thereby shutting off the TBU.
Diodes D1 and D4 act to block current flow to or from the gates of Q7 and Q8. In some cases, the voltage handling capability of the gates of Q7 and Q8 may be insufficient to handle the high voltage developed across Q9. In such cases, resistance can be included in series with diodes D1 and D4 (or as a replacement to the diodes) to ensure the bypass current generated by this high voltage is limited to a level that the gates of Q7 and Q8 can handle. Also, in some cases, the junction voltages of Q7 and Q8 can be such that it is not necessary to provide diodes D1 and D4 to prevent current flow to or from the gates of Q7 and Q8.
In some cases, transistors Q7 and Q8 may exhibit current collapse, which is a transient decrease in channel conductivity responsive to a high applied voltage. For example, GaN transistors are prone to exhibit current collapse. In such cases, it is preferable to add optional diodes D2 and D3 as shown, which serve to protect Q7 and Q8 from damage cause by high reverse voltages. More specifically, Q7 is relevant for blocking negative transients, so its corresponding diode D2 permits the flow of positive current (i.e., build-up of high reverse voltage is prevented). Similarly, Q8 is relevant for blocking positive transients, so its corresponding diode D3 permits the flow of negative current. Here also, build-up of high reverse voltage is prevented by the diode shunt.
In some cases, resistors may be placed in series with one or more of diodes D1-D4 in order to adjust the biasing of the transistors. Such bias adjustment is within the skill of an ordinary art worker.
This application claims the benefit of U.S. provisional patent application 60/860,528, filed on Nov. 21, 2006, entitled “Dual gate GaN transient blocking units”, and hereby incorporated by reference in its entirety.
Number | Date | Country | |
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60860528 | Nov 2006 | US |