Patent Application
20250202497
This application claims priority to foreign French patent application No. FR 2314251, filed on Dec. 15, 2023, the disclosure of which is incorporated by reference in its entirety.
The invention relates to the field of circuits for converting a digital signal into an analogue signal, more particularly to the design of a current analogue-to-digital converter having a high linearity constraint.
A digital-to-analogue converter is an electronic device that transforms digital signals into analogue signals. It is used when digital data need to be converted into an analogue form, for example in order to be used in audio systems or to control analogue equipment. The digital-to-analogue converter works by converting the digital data, generally expressed in binary form, into a corresponding analogue voltage and/or current.
Digital-to-analogue converters are used in numerous applications such as audio systems, industrial control systems, wireless communications and measuring instruments. They are essential to allowing interaction between digital and analogue systems by converting the digital data into analogue signals that can be understood by the analogue equipment.
More particularly, a current digital-to-analogue converter circuit is an electronic device that transforms digital signals into proportional analogue currents. Unlike a voltage digital-to-analogue converter, which generates an analogue voltage at the output, a current digital-to-analogue converter produces an analogue current at the output. Ideally, the output current is directly proportional to the digital input value. This current can then be converted into a voltage across a load resistor.
The conversion process in a current digital-to-analogue converter circuit involves the use of an array comprising a plurality of elementary current source branches. Each digital input value selects a (or multiple) source branch constituting a specific path for the current by activating or deactivating corresponding switches. This generates various output currents proportional to the digital input values.
The design of a current digital-to-analogue converter is mainly limited by the matching of the transistors, the dependency of the current on the supply voltage or on the earth, and also by the output impedance of the elementary current source branches that make up the converter. As far as the matching and the dependency of the power supplies are concerned, these can be adjusted by using appropriate dimensions for the transistors in the elementary current sources.
However, for an N-bit current digital-to-analogue converter, it is necessary to have 2N−1 elementary current source branches. The output impedance of the current digital-to-analogue converter depends on the number of activated current sources. For a code ramp extending from 0 to 2N−1, the variation in the output impedance of the converter brings about a systematic integrated nonlinearity error.
In order to understand the problem of linearity in current digital-to-analogue converters,
For a digital-to-analogue converter, the measured real maximum current value Imax-reel is less than the theoretically calculated ideal maximum current value Imax-ideal. The nonlinearity is maximum for a midrange number of activated elementary sources, between the minimum number and the maximum number of activated elementary sources. INL (Integrated Non Linearity) is a measurement that assesses the linearity of a digital-to-analogue converter. It is a measurement of the greatest difference observed between the second curve C2 and the third curve C3 corresponding to perfectly linear operation between zero and the real maximum current value Imax-reel. More specifically, INL quantifies the differences between the real analogue current values produced by the converter and the ideal values of the third curve C3 that are expected over the entire conversion range. INL is generally expressed in LSB (Least Significant Bit). An INL of 0 LSB means that the DAC produces perfectly linear voltage values without any error.
Against this background, several problems have been clearly identified with current digital-to-analogue converters known from the prior art; more specifically, problems relating to errors due to the nonlinearity of the behaviour of the analogue-to-digital converter for a large number of activated elementary source branches.
Moreover, when designing a digital-to-analogue converter circuit, the output impedance needs to be higher than a critical threshold that depends on the specified INL, on the load resistance and on the number of bits of the digital-to-analogue converter. Typically, for a specified INL of the order of ½ LSB (Least Significant Bit), the target value of the output impedance becomes difficult to achieve for digital-to-analogue converters beyond 8-10 bits.
More generally, the invention can be used for converters having a linearity constraint by reducing the difference between theoretical behaviour and real behaviour.
We will start by introducing solutions known to those skilled in the art for improving the linearity of an analogue-to-digital converter having a plurality of elementary current source branches.
The first solution according to the prior art consists in stacking a plurality of cascoded transistors in each branch. The cascoded transistors are dimensioned so as to increase the output impedance of the converter circuit and thus reduce the amplitude of the nonlinearity. The disadvantage of this solution is not only a considerable increase in the surface area occupied by the circuit but also a reduction in the range of variation of the output voltage across the terminals of the load resistor at the output of the converter.
The second solution according to the prior art consists in adding a digital correction module in order to correct conversion errors due to the nonlinearity of the behaviour of the current digital-to-analogue converter. The digital correction circuit can use techniques such as gamma correction, linearity correction and interpolation correction to adjust the values of the analogue signals produced by the converter. The disadvantage of this solution is that it requires the introduction of additional complexity to the system, which results in a considerable increase in the surface area taken up by the circuit and to an increase in its power consumption. More specifically, the solution according to the prior art is based on the construction of a lookup table, which consists in matching the digital code received at the input to a modified code that allows steps to be taken to ensure that the measured curve approximates the ideal curve as far as possible. This requires the implementation of a large memory in order to store this table. This results in a considerable increase in the surface area taken up by the circuit.
To compensate for the limitations of the existing solutions, the invention proposes an analogue-to-digital converter circuit in which the bias circuit comprises at least one amplifier circuit that increases the output impedance seen by the elementary current source branches. Several embodiments of the invention are put forward with implementation variants of the proposed solution.
The subject of the invention is an electronic circuit configured to convert an N-bit digital input signal into an output current, N being a non-zero natural number, said circuit comprising:
According to a particular aspect of the invention, the first amplifier circuit is an operational amplifier having a noninverting input connected to the output node, an inverting input connected to the drain of the first bias cascode transistor, and an output connected to the gate of the follower transistor.
According to a particular aspect of the invention, the second amplifier circuit is an operational amplifier having a noninverting input configured to receive a first bias voltage, an inverting input connected to the source of the first bias cascode transistor, and an output connected to the gate of the first bias cascode transistor and intended to generate said regulated voltage.
According to a particular aspect of the invention, the second amplifier circuit comprises a second current generator and a first amplification transistor, which is supplied with power by said dedicated second current generator and has: a gate connected to the source of the first bias cascode transistor; and a drain connected to the gate of the first bias cascode transistor.
According to a particular aspect of the invention, the first bias branch comprises a second bias cascode transistor connected between the first generator of the reference current and the first bias current mirror transistor.
According to a particular aspect of the invention, the bias circuit moreover comprises a third amplifier circuit having a noninverting input configured to receive a second bias voltage, an inverting input connected to the source of the second bias cascode transistor, and an output connected to the gate of the second bias cascode transistor.
According to a particular aspect of the invention, the second bias voltage corresponds to the first bias voltage.
According to a particular aspect of the invention, the bias circuit moreover comprises a second amplification transistor supplied with power by a dedicated third current generator and having a gate connected to the source of the second bias cascode transistor and having a drain connected to the gate of the second bias cascode transistor.
The subject of the invention is also a phase-configurable photonic device comprising:
The subject of the invention is also an optical phased array configured to direct a light beam in a predetermined direction, comprising: a plurality of phase-configurable photonic devices according to the invention, which are supplied with power by a common laser source; each phase-configurable photonic device being controlled by a dedicated digital control signal generated by control means.
Other features and advantages of the present invention will become more apparent upon reading the description that follows with reference to the appended drawings below.
A target load circuit is connected to the digital-to-analogue converter circuit D1. The target load circuit is intended to receive the output current Iout. The target load current may be, as an enlightening, nonlimiting example, a resistive element or an inductive element or a capacitive element or an electronic circuit to be supplied with power by the output current Iout. In the remainder of the description, the target load circuit is produced by a resistive element R1, but the invention remains compatible with any load circuit receiving the output current Iout according to the application context of the invention. A target load circuit formed by at least one inductive element produces a power converter, for example. A target load circuit formed by at least one capacitive element produces a sampling circuit, for example. A target load circuit to be supplied with power by the output current Iout is an amplifier or a logic circuit, for example.
In the example shown, the resistive element R1 is connected between the supply node 12 and the output node 11. The resistive element R1 is intended to carry the output current Iout, the level of which depends on the digital input signal BW. The resistive element R1 is thus used to convert the output current Iout into a voltage drop between the supply node 12 and the output node 11 and thus into an analogue output signal Vout.
Alternatively, the resistive element R1 uses the output current Iout to produce an amount of heat by way of the Joule effect. This is useful for applications that require local and modulable heating around the resistive element R1.
The digital-to-analogue converter circuit D1 comprises 2N−1 elementary source branches BCj connected in parallel between the output node 11 and the electrical earth GND. Each elementary source branch BCj comprises a control transistor M1j, an elementary cascode transistor M2j and an elementary current recopying transistor M3j.
For each elementary source branch BCj of rank j, the drain of the control transistor M1j is connected to the output node 11 common to all the source branches; the drain of the elementary cascode transistor M2j is connected to the source of the control transistor M1j; the drain of the elementary current recopying transistor M3j is connected to the source of the elementary cascode transistor M2j; the source of the elementary current recopying transistor M3j is connected to the electrical earth GND; the gate of the control transistor M1j is controlled by one bit of the digital input signal BW and the respective gates of the elementary cascode transistor M2j and the elementary current recopying transistor M3j are biased by the bias circuit 20. Thus, the output impedance rds of the two transistors M2j, M3j of the elementary source branch BCj is partly determined by the bias circuit 20. The combination of the transistors M2j, M3j of the elementary source branch BCj behaves like a current source having an output impedance rds. The control transistor M1j acts as a current switch in the elementary source branch BCj. When the control transistor M1j is in the on state, a current path is set up from the supply node 12 to the electrical earth GND through the load impedance R1 and then the elementary source branch BCj associated with said control transistor. Thus, each elementary source branch BCj has an ability to generate an elementary current Isrc through the load impedance R1. If the dimensioning of the transistors of the source branches is identical, the elementary currents are identical. In this case, ideally, when the bits of the digital input signal BW activate M source branches, the output current Iout passing through the load impedance R1 is equal to M times the elementary current Isrc. The transistors of each elementary source branch BCj are dimensioned so as to work under saturation conditions for a predetermined maximum output current value Iout, a predetermined supply voltage VDD and a predetermined value of the output impedance.
To take account of the significance of the bits in the digital input signal BW=[Bit0 Bit1 Bit2 Bits BitN-1], the distribution of the bits with regard to the control transistors M1j is produced as follows: the bit of rank i=0 Bit0 having the least significance (as an illustrative, nonlimiting example) controls the gate of the control transistor M10 of the elementary source branch BC0; the bit of rank i=1 Bit1 having the next significance controls the gates of the control transistors M11 and M12 of the next 2i=1 source branches BC1 and BC2; the bit of rank i=2 Bit2 having the next significance controls the gates of the control transistors M13 to M16 of the next 2i=2 source branches BC3 to BC6 and so on as far as the bit BitN-1 of rank N−1 that controls the gates of the control transistors of the last 2N-1 source branches BCj. The sequential order of the distribution has been described to make it easier to understand the distribution of control, but it is not obligatory. In general terms, the bit of rank i=0 to N−1 controls the gates of the control transistors of 2i source branches BCj chosen from the 2N-1 source branches of the converter circuit D1. Thus, when the bit of rank i Biti (and therefore of significance i) is in logic state “1”, the associated 2i source branches BC are on. This leads to the injection of a current associated with said bit Biti; the injected current is proportional to the significance of said bit Biti and is equal to 2i*Isrc.
It is also conceivable to add a digital circuit (not shown) that is configured to convert the digital input signal BW in order to convert the most significant bits into thermometric codes for controlling the gates of the control transistors M1j, which reduces the disadvantages relating to the differential nonlinearity (DNL) of the converter.
The bias circuit 20 comprises a current mirror formed by a first bias branch BS1 carrying a reference current Iref and a second bias branch BS2 coupled to the first bias branch BS1. The first bias branch BS1 comprises a first generator SC1 of said reference current Iref, a first bias current mirror transistor M2.
The second bias branch BS2 comprises, in this order: a follower transistor M3, a first bias cascode transistor M4 and a second bias current mirror transistor M5, which are connected in series from the supply node 12 to the electrical earth GND.
The specific implementation shown for the current mirror formed by the bias branches BS1, BS2 is presented as a nonlimiting example. The invention remains compatible with all current mirror architectures in general terms.
Advantageously, and optionally, the first bias branch BS1 comprises a second bias cascode transistor M1. The second bias cascode transistor M1 improves the current mirroring from the first bias branch BS1 to the second bias branch BS2. In an implementation without a second bias cascode transistor M1, the first bias current mirror transistor M2 is connected as a diode directly connected to the first generator SC1.
More specifically, the first current generator SC1 is connected between the supply node 12 and the drain of the second bias cascode transistor M1. The drain of the first bias current mirror transistor M2 is connected to the source of the second bias cascode transistor M1. The source of the first bias current mirror transistor M2 is connected to the electrical earth GND. The gate of the bias current mirror transistor M2 is connected to the output of the first current generator SC1. In the first embodiment, the second bias cascode transistor M1 is biased by a reference voltage (also called a setpoint voltage) Vcasc,ref originating from an external source (not shown).
The gate of the first bias current mirror transistor M2 is connected to the drain of the second bias cascode transistor M1 and to the gate of the second bias current mirror transistor M5. The cascoded connection of the second bias cascode transistor M1 imposes a drain voltage on the second bias current mirror transistor M2. The drain of the follower transistor M3 is connected to the supply node 12. The drain of the first bias cascode transistor M4 is connected to the source of the follower transistor M3. The drain of the second bias current mirror transistor M5 is connected to the source of the first bias cascode transistor M4. The source of the second bias current mirror transistor M5 is connected to the electrical earth GND. Connecting the gates of the first mirror transistor M2 and the second mirror transistor M5 and having a potential that is very close on the drains of M2 and M5 ensures that the reference current Iref (or a multiple of Iref) of the first bias branch BS1 is properly mirrored into the second bias branch BS2, in particular because this limits the Early effect.
For each elementary source branch BCj, the gate of the elementary cascode transistor M2j is connected to the gate of the first bias cascode transistor M4 of the second bias branch BS2. This couples each elementary source branch BCj to the second bias branch BS2. Moreover, for each elementary source branch BCj, the gate of the elementary current recopying transistor M3j is connected to the gate of the first bias current mirror transistor M2 of the first bias branch BS1. This couples each elementary source branch BCj to the first bias branch BS1. The dual coupling of each elementary source branch BCj mirrors the reference current (or a multiple of the current) onto any one of the source branches BCj when said source branch is in the on state.
The bias circuit 20 also comprises a first amplifier circuit RC1 configured to copy the output voltage Vout onto the drain of the first bias cascode transistor M4. This achieves a behaviour of the second bias branch BS2 similar to that of the source branches BCj, which see the variations in the output voltage Vout during operation of the digital-to-analogue converter circuit D1. The improvement in the similarity of the voltage variations seen by the second bias branch BS2 and the source branches BCj improves the linearity of the digital-to-analogue converter D1. By way of example, the amplifier circuit RC1 is an operational amplifier having a noninverting input connected to the output node 11, an inverting input connected to the drain of the first bias cascode transistor M4, and an output connected to the gate of the follower transistor M3.
The bias circuit 20 moreover comprises a second amplifier circuit RC2, which is configured to generate a regulated voltage Vcasc,src on the gate of the first bias cascode transistor M4 from at least the voltage of the source of said first bias cascode transistor M4. The combination of the second amplifier circuit RC2 with the bias cascode transistor M4 forms a regulated cascode. Furthermore, the second amplifier circuit RC2 is connected so as to regulate the gate voltage of the first bias cascode transistor M4 and thus keep the drain of the second bias current mirror transistor M5 at a first predetermined bias voltage Vcasc.
According to the first embodiment, the second amplifier circuit RC2 is produced by an operational amplifier having a noninverting input configured to receive a first bias voltage Vcasc, an inverting input connected to the source of the first bias cascode transistor M4, and an output connected to the gate of the first bias cascode transistor M4 and intended to generate the regulated voltage Vcasc,src. This connection of the second amplifier circuit RC2 increases the output impedance of the converter circuit D1 and thus improves the linearity of the output current lout on the basis of the number of activated source branches BCj. The reason is that using the second amplifier RC2, with gain A, connected as a “regulated cascode”, multiplies the output impedance rout by a factor of A+1 compared to a cascode connection according to the prior art, without the second amplifier RC2. Advantageously, the output power of the second amplifier circuit RC2 is greater than four times that of the first amplifier circuit RC1. This allows the second amplifier circuit RC2 to control the gates of the 2N−1 load transistors M2j in addition to the gate of the first bias cascode transistor M4.
We have described a combination of technical elements that is formed by: firstly, the first amplifier RC1, which mirrors the output voltage Vout into the second bias branch BS2; and, secondly, the second amplifier circuit RC2, which regulates the gate voltage of the first bias cascode transistor M4. This combination achieves improved linearity of the output current Iout on the basis of the number of activated source branches BCj (and therefore on the basis of the bits in logic state “1”). This improves the linearity of the output current while avoiding expanding or adding multiple cascode stages in the source branches BCj. The solution according to the invention thus saves surface area taken up by the converter circuit compared with the solutions of the prior art without adversely affecting linearity.
Advantageously, and optionally, each elementary source branch BCj is not limited to a single elementary cascode transistor M2j and thus comprises a plurality of elementary cascode transistors M2j, M2j′, M2j″ . . . . Advantageously, and optionally, the second bias branch BS2 is not limited to a single first bias cascode transistor M4 and thus comprises a plurality of bias cascode transistors M4, M4′, M4″ . . . . The biasing of at least one bias cascode transistor among said plurality of bias cascode transistors is regulated by at least one amplifier circuit RC2 connected as described above.
In this embodiment, the second amplifier circuit comprises a second current generator IRC2 and a first amplification transistor MRC2, which is supplied with power by said dedicated second current generator IRC2. The gate of the first amplification transistor MRC2 is connected to the drain of the second bias current mirror transistor M5 (and therefore to the source of said first bias cascode transistor M4). The drain of the first amplification transistor MRC2 is connected to the gate of the first bias cascode transistor M4. In this embodiment, the first bias voltage Vcasc corresponds to the gate-source voltage VGS, MRC2 of the first amplification transistor MRC2. The first amplification transistor MRC2 is connected as a common source amplifier. The choice of the intensity of the current IRC2 and the dimensioning in terms of width and length of the first amplification transistor MRC2 generate a regulated voltage Vcasc, src on the gate of the first bias cascode transistor M4 from the voltage of the source of said first bias cascode transistor M4.
Similarly, in this embodiment, the third amplifier circuit comprises a third current generator IRC3 and a second amplification transistor MRC3, which is supplied with power by said dedicated third current generator IRC3. The gate of the second amplification transistor MRC2 is connected to the drain of the first bias current mirror transistor M2 (and therefore to the source of the second bias cascode transistor M1). The drain of the second amplification transistor MRC3 is connected to the gate of the second bias cascode transistor M1. In this embodiment, the second bias voltage Vcasc corresponds to the gate-source voltage VGS,MRC3 of the second amplification transistor MRC3. The second amplification transistor MRC3 is connected as a common source amplifier. The choice of the intensity of the current IRC3 and the dimensioning in terms of width and length of the second amplification transistor MRC3 generate a regulated voltage Vcasc,ref on the gate of the second bias cascode transistor M1 from the voltage of the source of said second bias cascode transistor M1.
We emphasize that the implementation choices for producing the second and third amplifier circuits are independent. It is possible to opt for: firstly a differential operational amplifier to produce the second amplifier circuit and secondly connection of an amplification transistor as a common source to produce the third amplifier circuit, or vice versa.
In general terms for all embodiments of the invention, the combination of the first amplifier circuit RC1 and the second amplifier circuit RC2 (or MRC2) has a synergy that regulates the bias of the drain and the source of the first bias cascode transistor M4 at the same time and thus regulates the bias of the gate of said first bias cascode transistor M4. Regulating the bias of said gate reduces the difference between the real behaviour and the theoretical behaviour of the converter circuit of the digital-to-analogue converter D1.
The invention has been explained using NMOS transistors as a nonlimiting illustrative example. Nothing prevents the same solution from being implemented using PMOS transistors. Alternatively, a person skilled in the art can adapt the proposed architecture described in
The invention can be used in the context of a first phase-configurable photonic device DP. The photonic device DP comprises a waveguide WG, a transmitting antenna GC, a resistive element R1 and an electronic digital-to-analogue converter circuit D1 according to any one of the embodiments of the invention.
The waveguide WG is configured to guide an input light beam REMin generated by a laser source SR. The waveguide WG is a microstructure integrated on a substrate made from a semiconductor material. The laser source may be external or integrated on the same semiconductor substrate.
The transmitting antenna GC is connected to the output of the waveguide WG and configured to transmit an out-of-phase light beam REMout. The transmitting antenna GC is produced by a grating coupler integrated on the semiconductor substrate.
The resistive element R1 corresponds to the target load circuit connected to the output node 11 of the electronic digital-to-analogue converter circuit D1. The resistive element R1 is intended to heat the waveguide WG by way of the Joule effect so as to manage the propagation index of the waveguide WG in order to configure the phase of the out-of-phase light beam REMout.
Local modification of the propagation index modifies the phase of the fraction of the signal transmitted by laser source SR that passes through the waveguide WG and that continues as far as the transmitting antenna GC. The resistance of the resistive element R1 is between 10Ω and 100 kΩ. The digital-to-analogue converter circuit D1 is configured to control the intensity of the current carried by the resistive element R1 on the basis of a digital control signal BWC. The digital control signal BWC is generated by a control unit CONT. The digital control signal BWC is coded according to the desired heating, which depends on the targeted phase shift.
The second photonic device OPA comprises a plurality of phase-configurable photonic devices DPm of rank m=0 to M−1. The phase-configurable photonic devices DPm form a photonic array. Each phase-configurable photonic device DPm receives a dedicated digital control signal BWCm from the control unit CONT. All of the waveguides WG of the photonic devices DPm are supplied with power by a common laser source SR. The common laser source SR generates an input light beam REMin that is divided into M fractions. Each fraction is guided by the waveguide WG of an associated photonic device DPm. Ideally, the phase-configurable photonic devices DPm are configured so as to create a constant phase shift (modulo 2.pi) for each phase-configurable photonic device DPm of rank m in relation to the next phase-configurable photonic device DPm+1 of rank m+1. The output light beam is obtained by superimposing the various out-of-phase light beams REM0, REM1 to REMM-1.
As a nonlimiting example, the photonic device D2 comprises an array of 256 phase-configurable photonic devices DPm and thus 256 digital-to-analogue converter circuits D1 in a 5×5 mm2 CMOS circuit. In this context, the solution according to the invention has a particular advantage associated with a reduced surface area of the 256 digital-to-analogue converter circuits D1 combined with improved linearity. The improved linearity introduces a more precise phase shift between the various antennas of the OPA.
The implementation of the converter circuit according to the invention has been described for a transmitting photonic device as a nonlimiting example. The invention also remains compatible, and has the same advantages, for a photonic device in which the antenna GC is configured to receive. In this case, the antennas GC receive a stream from the scene and it is possible to favour one receiving direction by modulating the phases of the antennas.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2314251 | Dec 2023 | FR | national |
