Claims
- 1. A bias circuit receiving a control signal, comprising:
an input connected to receive the control signal; a bias circuit output for applying an output bias voltage; a reference voltage generator that generates the output bias voltage responsive to a first transition in the control signal; and a voltage follower having an input connected to receive the output bias voltage from the reference voltage generator and an output connected to the bias circuit output, the voltage follower operating in transient conditions with respect to the output bias voltage to source a boost current at its output to rapidly charge the bias circuit output.
- 2. The bias circuit of claim 1 further including a first protection circuit operating responsive to a second transition in the control signal to pull the input of the voltage follower to ground.
- 3. The bias circuit of claim 2 further including a second protection circuit also operating responsive to the second transition in the control signal to pull the bias circuit output to ground.
- 4. The bias circuit of claim 2 wherein the voltage follower comprises a first transistor having a gate and the first protection circuit comprises a second transistor drain to source connected between the gate of the first transistor and ground, the second transistor having a gate receiving the control signal.
- 5. The bias circuit of claim 1 wherein the voltage follower comprises a source follower configured transistor.
- 6. The bias circuit of claim 1 further comprising a current source connected between the voltage follower output and ground.
- 7. The bias circuit of claim 6 wherein the current source and the reference voltage generator are connected in a current mirror configuration.
- 8. The bias circuit of claim 1 further including:
a storage circuit including an isolation transistor having a gate and a floating gate transistor; wherein the bias circuit output is connected to the gate of the isolation transistor for applying the output bias voltage and the boost current to the storage circuit.
- 9. The bias circuit of claim 8 wherein the bias circuit including the storage circuit is fabricated as an integrated circuit.
- 10. The bias circuit of claim 1 wherein the bias circuit is fabricated as an integrated circuit.
- 11. A bias circuit receiving a control signal, comprising:
an input connected to receive the control signal; a bias circuit output for applying an output bias voltage; a reference voltage generator connected to the bias circuit output that generates the output bias voltage responsive to a first transition in the control signal; and a source follower having an input connected to receive an indication of output bias voltage generation by the reference voltage generator and an output connected to the bias circuit output, the source follower operating responsive to the indication to source a boost current at its output to rapidly charge the bias circuit output.
- 12. The bias circuit of claim 11 further including a first protection circuit operating responsive to a second transition in the control signal to pull the input of the source follower to ground.
- 13. The bias circuit of claim 12 wherein said source follower has no intentional separate resistive element in its drain circuit.
- 14. The bias circuit of claim 12 further including a second protection circuit also operating responsive to the second transition in the control signal to pull the bias circuit output to ground.
- 15. The bias circuit of claim 11 wherein the source follower comprises a first transistor having a gate and the first protection circuit comprises a second transistor drain to source connected between the gate of the first transistor and ground, the second transistor having a gate receiving the control signal.
- 16. The bias circuit of claim 11 further including:
a storage circuit including an isolation transistor having a gate and a floating gate transistor; wherein the bias circuit output is connected to the gate of the isolation transistor for applying the output bias voltage and the boost current to the storage circuit.
- 17. The bias circuit of claim 16 wherein the bias circuit including the storage circuit is fabricated as an integrated circuit.
- 18. The bias circuit of claim 11 wherein the bias circuit is fabricated as an integrated circuit.
- 19. An apparatus for rapidly charging a load which may have substantial capacitance associated therewith, said apparatus comprising:
a voltage reference generator; a current driving stage; wherein said current driving stage operates in a class AB manner to allow high current upon demand to the load while still allowing for low quiescent current.
- 20. A bias circuit receiving a control signal, comprising:
a bias voltage generator including an input connected to receive the control signal and an output, the bias voltage generator producing a voltage signal that transitions from a first value to a second value in response to a change in the control signal; a boost circuit operating responsive to the transition of the voltage signal from the first value to generate a boost current; and means for combining the voltage signal and the boost current as an output bias voltage.
- 21. The bias circuit as in claim 20 wherein the boost circuit comprises a voltage follower having an input connected to receive the voltage signal from the bias voltage generator and an output connected to a bias circuit output, the voltage follower operating in transient conditions with respect to the voltage signal to source the boost current at its output to rapidly charge the bias circuit output.
- 22. The bias circuit as in claim 20 wherein the boost circuit comprises a source follower having an input connected to receive an indication of voltage signal generation by the bias voltage generator and an output connected to a bias circuit output, the source follower operating responsive to the indication to source a boost current at its output to rapidly charge the bias circuit output.
- 23. The bias circuit as in claim 20 further including a protection circuit operating responsive to the control signal to pull the boost circuit to ground.
- 24. The bias circuit as in claim 23 wherein the boost circuit comprises a transistor having a control gate, the protection circuit pulling the control gate of the transistor to ground.
- 25. The bias circuit as in claim 20 further including:
a storage circuit including an isolation transistor having a gate and a floating gate transistor; wherein the output bias voltage is applied to the gate of the isolation transistor.
- 26. The bias circuit as in claim 25 wherein the bias circuit including the storage circuit is fabricated as an integrated circuit.
- 27. The bias circuit of claim 20 wherein the bias circuit is fabricated as an integrated circuit.
- 28. A method for generating an output bias voltage, comprising the steps of:
generating a voltage signal that transitions from a first value to a second value in response to a change in a control signal; detecting transition of the voltage signal from the first value; generating a boost current in response to detected transition; and applying the boost current to an output for the voltage signal and thus rapidly achieve the output bias voltage.
- 29. The method as circuit as in claim 28 further including the steps of:
detecting transition of the voltage signal towards the second value; and terminating boost current generation in response to the detected transition.
- 30. Apparatus for rapidly charging a capacitive line to a bias voltage, the apparatus employing a bias driver, the bias driver comprising:
a voltage reference generator: an input receiving a control signal; a current driver circuit; wherein the control signal is effective to either activate or deactivate the bias driver, and when activated, the current driver operating to charge the capacitive line to a desired bias voltage responsive to said voltage reference generator with an amount of current greater than its quiescent value in order to achieve a rapid charging of said capacitive line.
- 31. The apparatus of claim 30 wherein the bias driver, when deactivated responsive to the control signal, consumes substantially zero power.
CROSS-REFERENCE TO RELATED PATENT
[0001] The present application is related to commonly-owned U.S. Pat. No. 5,900,756, issued May 4, 1999, the disclosure of which is incorporated by reference herein.