Print heads employ nozzles to dispense ink when commanded by electronic circuits such as operational amplifiers. One style of print head is a piezo head where voltages applied by the amplifiers to the piezo element of the print head cause ink to dispense from the head and associated nozzle. Current commercial piezo heads have drivers that use a cold switch circuit where there is a high power, high voltage operational amplifier that is located separately from the print head area, and connected typically by a single wire to the print head. This wire carries the waveform that all ink dispensing nozzles utilize. Another type of piezo head driver utilizes a per nozzle strategy to drive individual print nozzles, wherein each piezo nozzle is driven from a separate print driver circuit. In such cases, currents such as amplifier bias current and current that is generated due to the slew rate of the amplifier can be considerable since each of the respective currents in each circuit is multiplied by the number of driver circuits required to drive the associated print heads. In some cases, hundreds of print heads may be driven by hundreds of driver circuits, wherein the bias and slew rate currents can contribute to considerable power losses when considered in the aggregate.
The operational amplifier 120 can be operated in class A-B mode to drive the print nozzle 130. Class A, class A-B, or class B amplifiers can be employed in a single or a multiple stage configuration to generate amplified print command signals to the print nozzle 130. Multiple stage operation can also be provided for the amplifier 120 wherein one stage could be configured as class A, A-B, or class B and a subsequent stage (or subsequent stages) could be configured as class A, A-B or class B, for example. The reduced power savings is further enhanced since there can be hundreds of print nozzles 130—each requiring their own amplifier 120 to command ink dispersal from the respective print nozzles.
In one example, the operational amplifier 120 can be employed as a first stage amplifier to drive a second stage amplifier (illustrated in
For purposes of simplification of explanation, in the present example, different components of the systems described herein are illustrated and described as performing different functions. However, one of ordinary skill in the art will understand and appreciate that the functions of the described components can be performed by different components, and the functionality of several components can be combined and executed on a single component or be further distributed across more components. The components can be implemented, for example, as an integrated circuit or as discrete components, or as a combination of both. In other examples, the components could be distributed among different printed circuit boards, for example.
Transistors M1-5 and M7 can be configured as source followers, wherein M5 receives input IN− and M7 receives input IN+. Output voltage from the source follower M5 and M7 sets the source voltage of M6 and M8, respectively. The gate voltage of M6 and M8 can be set by the source voltage of M5 and M7 plus the diode connected voltages of M6 and M8. Transistor pairs M6, M3 and M8, M4 can be designed to be current mirrors and mirror quiescent current into M11 and M12, respectively. The current in the two side legs of the circuit, one side-leg circuit being formed of M9, M6, M5 and the other side-leg circuit being formed of M10, M8 and M7 are set by current mirror into M9 and M10, and hence are substantially constant. One purpose of these side legs is to set the gate voltages for M3 and M4, where if the effective voltage difference between IN+ and IN− is equal to zero, and the common mode voltage within normal operating range, then the current in the transistors M11 and M12 can be equal to each other. If the effective voltage difference between IN+ and IN− is greater than or less than zero, then there can be a corresponding increase in current in the M11 or M12 legs respectively, with a current magnitude that can increase to a value greater than the original quiescent value in M11 and M12.
Since the additional current in M11 and M12 can be provided by the source follower action of M1 and M2 versus M3 and M4, it can reach a large magnitude, substantially determined by the source impedances and allowable voltage ranges provided by these devices and generally not limited by the original quiescent current. In this manner, this first stage amplifier depicted by the circuit 400 provides class A-B operation, where there is a substantially constant base bias current when the effective voltage difference between IN+ and IN− is equal to zero, and then when an effective voltage difference between the IN+ and IN− inputs is introduced, such as when the circuit 400 is being commanded to slew, the inner leg of the circuit that is needed to effect the slew has a current on it that grows to a large value, greater than that of the initial, constant bias. The transistors M9, M10, and M13 also receive and process a reference current shown as IREFa to set the original quiescent current.
Transistors M11 and M12 form a second current mirror that receives positive and negative output current from the differential amplifier at the drain leads of M3 and M4, respectively. The positive and negative output current fed to the current mirror formed from M11 and M12 include a bias current component and a variable current component that is a function of the voltage applied at IN+ and IN−. It is the bias current component that is fed to the current mirror of M11 and M12 that is offset by the current reduction DAC 410. As shown, the DAC 410 diverts bias currents Idac1 and Idac2, wherein the amount of current diverted is a function of the programmed value of the DAC that can be set from firmware settings via a controller (not shown) for example. A second reference, IREFb, can be supplied to the DAC 410.
Output from the amplifier 400 can be generated as negative and positive output signals and shown as signals negout and posout, respectively. In one example, negout and posout signals can be coupled to the gate of an NMOS transistor to form the second half of a mirror circuit in order to mirror the current output of this first stage into subsequent stages. Such output from the amplifier 400 can be employed to drive a subsequent amplifier stage (e.g., class B amplifier), wherein the subsequent stage is employed to control a level shifted stage that drives a piezo print nozzle amplifier, for example. As described above with respect to
As noted above, width and length die dimensions can be adjusted to mitigate power losses and enhance switching performance in the circuit 400. For example (w=width and l=length, u means micron or micro), M9, M10 can be selected as w=3.75 u by l=1 u to mirror in a small current, about 2.74 uA, about half of IREFa to keep the current used in the outer legs of the circuit 400 (M9, 11 legs) to a minimum. This current is static, and hence causes power dissipation. In another example, M1, M2, M5, M7, NMOS dimensions can be selected as w=40 um and l=1 u. For M3, M4, M6, M8, PMOS dimensions can be selected as w=80 u, l=1 u, for example. Such w/l ratios selected provide enough gain for the amplifier, yet also provide approximately a 1000× increase in bias current when slewing (for an ideal, matched set of transistors). In practice, the bias current increase for slew can be smaller due to transistor mismatch, wherein several hundreds of times the base bias current is realized. In yet another example, M11, M12, dimensions can be selected w=40 u, l=1 u, wherein these dimensions provide a low impedance, as these are mirrored not only to the second stage of the amplifier for level shifting but also mirrored to the level shifter for the pass gate (if implemented), so width here is controlled because of capacitive loading on this set of mirrors, for example.
In view of the foregoing structural and functional features described above, an example method will be better appreciated with reference to
What have been described above are examples. It is, of course, not possible to describe every conceivable combination of components or methodologies, but one of ordinary skill in the art will recognize that many further combinations and permutations are possible. Accordingly, the disclosure is intended to embrace all such alterations, modifications, and variations that fall within the scope of this application, including the appended claims. As used herein, the term “includes” means includes but not limited to, the term “including” means including but not limited to. The term “based on” means based at least in part on. Additionally, where the disclosure or claims recite “a,” “an,” “a first,” or “another” element, or the equivalent thereof, it should be interpreted to include one or more than one such element, neither requiring nor excluding two or more such elements.
The present invention is a continuation patent application, claiming priority to Ser. No. 14/374,736, filed on 25 Jun. 2014, the entirety of which is incorporated herein by reference.
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Number | Date | Country | |
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Parent | 14374736 | US | |
Child | 15084115 | US |