Patent Application
20230170882
The present disclosure generally relates to electronic circuits for protection of active solid-state devices from unwanted parasitic turn-on, and more specifically to such electronic circuits for protection of gallium nitride (hereinafter “GaN”) high-electron-mobility transistor (hereinafter “HEMT”), devices used as power switches.
A power switch 102 such as shown in
For the case of a positive voltage change across the drain-source (henceforth called +dv/dt), the current tends to raise the gate voltage, and may turn on the power switch (e.g., a power FET or a power HEMT), causing catastrophic failure of the power switch and/or other power devices connected in series. This phenomena may be referred to as a Miller turn-on, or a parasitic-turn-on, or a self-turn-on, or a false-turn-on. Note that in power switch applications, +dv/dt at a switch typically occurs when the power switch is in its off state. Usually, a driver circuit 114 of the power switch 102 (which may also be referred to as a buffer, a driver, a driver buffer, a driver circuit buffer, a driver core, or the like), as shown in
A strong enough driver buffer stage, when operable, will typically be able to drain out a parasitic current rapidly, and keep the power switch off. However, in general, when a supply voltage for a driver circuit is not present, or is below a required level, then a driver circuit buffer stage would not be functional, or would be only partially functional, and then the driver circuit buffer would fail to suppress the parasitic turn-on of the power switch. Two example cases are described below.
In a universal half-bridge (UHB), the driver of the high-side gets its supply from an ad hoc bootstrapping circuit, which relies on the switching of the low-side of the UHB for its working. Therefore, at the very beginning, when no switching has yet happened, the supply voltage of the high-side starts at zero, and it might take several cycles of switching before the bootstrapping circuit supply reaches sufficient level for the driver to be operational. Under such a scenario, whenever the low side switch is turned on, the high side experiences a +dv/dt while the buffer stage of the driver circuit is not functional.
Another possible case is when in a UHB application, the main power supply, that is, the input supply to the power loop, is turned on, and the driver supply to the low side is still not up and ready. Under this case, the net dv/dt of the main supply will get divided between the high-side and the low-side switches, and this may turn on either or both of them.
The above example scenarios are not limited to UHB, but are rather common occurrences across a variety of power electronics topologies.
In the past, protection circuits (e.g., Miller clamp circuits) intended to prevent a power switch, e.g., a power FET or a power HEMT, from false turn-on either increased the switching losses of the power switch circuit or increased quiescent current of the circuits, particularly when fabricated in GaN technology. Additionally, all such protection circuits required a stable supply voltage for the driver circuit and/or for the protection circuit to be present to provide proper bias current to all active solid-state devices in the protection circuit.
The accompanying figures where like reference numerals refer to identical or functionally similar elements throughout the separate views, and which together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with the present disclosure, in which:
It is to be understood that the present disclosure will be described in terms of given illustrative examples. However, other semiconductor architectures, structures, substrate materials, and process features and steps may be varied within the scope of the present disclosure.
It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Reference in the specification to “one embodiment” or “an embodiment” of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
Various embodiments may include a design for an integrated circuit chip, which may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer may transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
Methods as described herein may be used as part of a process in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher-level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip can be then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, such as for example, and not for limitation, chargers for mobile phones and laptops, supply for desktops, servers and mobile base-stations, LED and motor drives, AC-DC, DC-DC, and DC-AC converters, power factor correction and LLC-topology converters, converters for automotive uses including its chargers, and many other commercial applications and military applications.
In view of the discussion above and the problems experienced by power switches in the past, it should be noted that gallium nitride (hereinafter “GaN”) high-electron-mobility transistor (hereinafter “HEMT”) devices are often used as semiconductor power switches which are devices capable of switching at high speed. In fact, the high switching speed is one of the main driving forces for widespread deployment of GaN in a number of practical applications. The high speed of GaN makes a high dv/dt unwanted parasitic turn-on signal even more likely to occur, and hence a Miller clamp protection circuit becomes an even more important feature.
Further, commercially available GaN switches (by which is intended to mean switches based on GaN technology only, and not on a cascade of silicon and GaN technologies) typically have a low turn-on gate threshold. Most reported numbers are about 1.5V at room temperature, which is a considerably lower gate turn-on voltage than, for example, a 3V and above of a threshold gate turn-on voltage typical for silicon power FETs. This means that even a small rise in gate voltage due to an unwanted parasitic +dv/dt voltage signal can cause a GaN power switch to
turn on.
Various embodiments of the invention, as will be discussed more fully below, provide an integrated solution to the past troublesome issues of unwanted parasitic turn-on gate voltage at the gate of a power switch that can turn on the power switch even while a supply voltage for a driver circuit and/or for a protection circuit is absent.
Further, in certain embodiments, all the devices of the integrated solution can be realized by including only GaN HEMT devices and resistors or capacitors that can be fabricated using available GaN processes, and can be easily integrated with a power GaN switch device itself.
The solution, according to various embodiments, enjoys the advantage of a single GaN die, which provides excellent response and performance parameters, while also providing reduction of fabrication cost and complexity arising from using another separate die for part of an overall circuit.
Prior attempts to solve the problem (e.g., to prevent a power FET switch from false turn-on) have been typically accompanied by increasing switching losses of the power FET circuit, by increasing quiescent current of the circuit such as if fabricated in GaN technology, by requiring external components and negative supply voltage, or by a combination of these accompanying problems, and which in all cases have required a stable supply voltage to be present for a driver circuit and/or for a protection circuit.
Although, various examples shown and described herein may include GaN technology and/or GaN HEMT based technology, an example solution circuits' topology and its application are understood to be independent of the device technology platform, and can be easily extended to silicon or to other present or future semiconductor technology platforms.
Referring now to the drawings in which like numerals represent the same or similar elements,
For example, and not for limitation; when a drain node 104 (see
As illustrated in the example shown in
As shown in
Any +dv/dt voltage signal between the drain 104 node and the source 106 node is detected by the capacitor C1120, and the +dv/dt signal is coupled through the capacitor 120 which charges/discharges net1 in the Miller clamp protection circuit 116.
In summary, the bias-less Miller clamp protection circuit 116 includes a capacitor C1120, or a device M1120 operating like a capacitor (as shown in
For example, a positive dv/dt voltage signal between the drain 104 node and the source 106 node will increase the voltage level in net1. A rise in voltage in net1 will pass through the voltage clamp 118 to cause a rise in voltage in net2. The rise in voltage in net2 will dynamically turn on the switch M2124 in the Miller clamp protection circuit 116, subject to a limit in the increasing voltage provided by a voltage clamp circuit 118 in the Miller clamp protection circuit 116. When the switch M2124 turns on, it effectively clamps the voltage signal at the gate G 108 of the power switch M0102. While the switch M2124 is turned on, the input voltage at the gate G 108 of the power switch M0102 is maintained at a voltage level that closely tracks a voltage level at the source 106 node of the power switch M0102. A Kelvin source could be provided to the Miller clamp protection circuit 116 as shown to help maintain the voltage level at the gate G 108 (coupled via the switch M2124 when it is turned on) substantially the same voltage as the voltage level at the source 106 node of the power switch M0102. The power switch M0102 thereby will remain turned off while an unwanted parasitic voltage signal may be generated from the drain 104 node and coupled to the gate G 108 node of the power switch M0102.
If the dv/dt signal between the drain 104 node and the source 106 node is negative, then net1/net2 will go negative, subject to a limit provided by the voltage clamp 118. Under this scenario, switch M2 remains off, and the disclosed set of circuit components does not interfere with a normal operation of the driver circuit 114 and the gate of the switch device 102. It is to be noted that a negative dv/dt signal across the drain 104 node and the source 106 node is expected when the power switch M0102 turns on, and the disclosed set of circuit components not interfering with a normal operation of the driver circuit 114 and the gate of the switch device 102 will be a desired feature under such a scenario.
The purpose of the voltage clamp 118 is to limit the voltage range at node net1 and net2 so as to protect the switch M2124 and other devices connected to these nets.
An optional R1122 can be provided for adjusting the reset time of the Miller clamp protection circuit 116.
An optional disable clamp 126 can be provided such that in response to a disable signal being coupled to an input 128 of the disable clamp 126, it causes the disable clamp 126 to clamp a voltage level at net1 and net2, and thereby turn off the switch M2124. This optional disable clamp 126 can disable the operation of the Miller voltage clamp 118.
A resistor R2118, as shown in the net1 circuit, can serve the purpose of limiting the voltage at the net2 circuit. The resistor R2 could be shorted if not needed.
The resistor R1122 provides a discharge path, and can be adjusted to set a time constant for net1 and net2, which in turn determines the reset time of the overall Miller clamp 116, according to various embodiments. Under an extreme case, if desired, R1122 can be removed (open-circuited) altogether.
The diode combination of D1 and D2 in the voltage clamp 118 clamps the positive voltage at net1, and the diode D3 in the voltage clamp 118 clamps the negative voltage at net2. Depending on need and available devices, the number of diodes can be increased or they can be changed with Zener diodes or some other suitable clamping devices.
The disable clamp device M3126 will be off (open-circuit) if a driver-supply is not available, or if the disable signal 128 is low. Under this condition, disable clamp device M3126 will not interfere with the operation of the rest of the Miller clamp protection circuit 116. When disable signal 128 goes high, the disable clamp device M3126 will turn on and will disable the overall operation of the Miller clamp protection circuit 116.
The switch device M2124, as explained earlier, is the power-switch-gate's clamp device, and when the switch device M2124 is turned on, it provides the clamping action to the gate 108 of the power switch device M0102.
In the voltage clamp circuit 118, the negative clamp on net1 consists of one GaN device M4 connected as a diode which replaces diode D3 in
More specifically, the graph of
The gate voltage at the input gate 108 of the power switch 102 is shown for a scenario in which the inventive Miller clamp protection circuit 116 is used, as shown in the middle plot of a voltage signal 406.
The gate voltage at the input gate 108 of the power switch 102 is shown for an alternative scenario in which the inventive Miller clamp protection circuit 116 is not used, as shown in the top plot of a voltage signal 404.
A comparison of the middle plot of the voltage signal 406 to the top plot of the voltage signal 404 shows how the inventive Miller clamp protection circuit 116 dynamically protects the input gate 108 of the power switch 102 from unwanted parasitic dv/dt voltage signals.
On the one hand, without the inventive Miller clamp protection circuit 116 between the driver circuit 114 and the gate 108 of the power switch 102, the input voltage at the gate 108, as shown in the top plot of the voltage signal 404, experiences a sustained voltage increase of about 1.5V to 1.7V which turns on the power switch 102 in response to an unwanted parasitic dv/dt voltage signal. This can cause catastrophic damage to the power switch 102 and to other circuit components in series with the power switch 102.
On the other hand, with the inventive Miller clamp protection circuit 116 in circuit between the driver circuit 114 and the input gate 108 of the power switch 102, the input voltage at the gate 108 of the power switch 102, as shown in the middle plot of the voltage signal 406, experiences only a quick small pulse voltage signal. In the example shown in
In summary, according to various embodiments, the novel Miller clamp protection circuit 116 as discussed above can be used to dynamically protect, for example and not for limitation, semiconductor switch devices. This novel Miller clamp protection circuit 116 works in a bias-less fashion. That is, it works even under the case when no supply voltage is available for powering the driver circuit 114 and/or for powering the protection circuit 116. This is a significant advantage of various embodiments of the disclosed invention, and which was not previously available in past attempted solutions to this often-pernicious problem.
The circuit topology of the novel Miller clamp protection circuit 116, as has been discussed above, is different from past attempted solutions to the problem. No other known previous solution has used a capacitor, or an equivalent circuit element, to sense a fast changing parasitic voltage dv/dt at a drain 104 node of an active solid-state switch device 102, and then for example when a positive voltage change dv/dt signal develops across the drain-to-source nodes 104, 106, of the switch device 102, a clamp device 118 is turned on thereby dynamically protecting the input gate 108 node of the switch device 102 from an unwanted parasitic signal that would otherwise turn on the switch device 102. According to various embodiments, a disable clamp circuit 126 in the protection circuit 116 is provided to disable the clamp device 118 and thereby to avoid interference with a normal operation of a driver circuit 114 coupled with the gate 108 of the switch device 102.
An advantageous feature of the inventive protection circuit 116 is that it does not need a supply voltage be applied to the driver circuit 114 and/or to the protection circuit 116 for the protection circuit 116 to operate to dynamically protect the switch 102 from unwanted parasitic turn on. This is possible because the inventive circuit uses the electrical energy from the dv/dt event itself to dynamically turn on the protection circuit 116. This feature makes the protection circuit 116 useful in a number of scenarios where a supply voltage for the driver circuit 114 and/or for the protection circuit 116 is either not available, or is still ramping up. For example, during an overall startup operation of an integrated circuit 100 the protection circuit 116 can operate to protect, for example, power switches 102 from unwanted parasitic turn on which otherwise would likely cause catastrophic damage to the power switches 102 and to other circuit elements in series with the power switches 102.
Moreover, inside an integrated circuit chip 100, for example, this protection circuit 116 circuit can effectively operate to dynamically protect the active solid-state switches 102 in an electronic circuit 100 in the integrated circuit 100 without needing any external connection pin at the chip 100, without any external circuit electrically coupled to the protection circuit 116, without any external positive or negative voltage supply electrically coupled to the protection circuit 116, and without any external passive component electrically coupled to the protection circuit 116.
Furthermore, according to various embodiments, the inventive protection circuit 116 does not consume any quiescent current. That is, for example, the bias-less Miller clamp protection circuit 116 does not consume any current during normal operation of the electronic circuit 100 in the integrated circuit 100.
Lastly, the inventive protection circuit 116 can be used in a variety of environments, including for protecting semiconductor switches for both low-side and high-side in half-bridge applications.
It should be noted that, according to various embodiments, in a method of operation of an electronic circuit inside an integrated circuit chip, the electronic circuit comprising a semiconductor switch device including a drain node, a source node, and a gate, the gate for receiving a driving electrical signal from an output of a driver circuit in the electronic circuit, and a bias-less Miller clamp protection circuit, electrically coupled to the output of the driver circuit and to the gate of the semiconductor switch device, the method comprises:
electrically coupling a parasitic Miller turn-on signal from the drain node into the bias-less Miller clamp protection circuit; and clamping, by the bias-less Miller clamp protection circuit, the gate of the semiconductor switch device to prevent the semiconductor switch device turning from an off state to an on state, in response to the parasitic Miller turn-on signal being electrically coupled into the bias-less Miller clamp protection circuit, wherein the bias-less Miller clamp protection circuit does not consume any current during normal operation of the electronic circuit.
Further, it should be noted that according to various embodiments, in a method of operation of an electronic circuit inside an integrated circuit chip, the electronic circuit comprising a semiconductor switch device including a drain node, a source node, and a gate, the gate for receiving a driving electrical signal from an output of a driver circuit in the electronic circuit, and a bias-less Miller clamp protection circuit, electrically coupled to the output of the driver circuit and to the gate of the semiconductor switch device, the method comprises:
electrically coupling a parasitic Miller turn-on signal from the drain node into the bias-less Miller clamp protection circuit; and clamping, by the bias-less Miller clamp protection circuit, the gate of the semiconductor switch device to prevent the semiconductor switch device turning from an off state to an on state, in response to the parasitic Miller turn-on signal being electrically coupled into the bias-less Miller clamp protection circuit, wherein the bias-less Miller clamp protection circuit does not cause any interference to operation of the driver circuit and the gate of the semiconductor switch device during normal operation of the electronic circuit.
Although specific embodiments of the invention have been disclosed, those having ordinary skill in the art will understand that changes can be made to the specific embodiments without departing from the scope of the invention. The scope of the invention is not to be restricted, therefore, to the specific embodiments, and it is intended that the appended claims cover any and all such applications, modifications, and embodiments within the scope of the present invention.
It should be noted that some features of the present invention might be used in one embodiment thereof without use of other features of the present invention. As such, the foregoing description should be considered as merely illustrative of the principles, teachings, examples, and exemplary embodiments of the present invention, and not a limitation thereof.
In addition, these disclosed embodiments are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others.
