BIAS VOLTAGE GENERATING CIRCUIT, SIGNAL GENERATOR CIRCUIT AND POWER AMPLIFIER

Abstract

A bias voltage generating circuit includes an amplifier circuit and a negative feedback circuit. The amplifier circuit is configured to generate a bias voltage according to a first voltage input and a second voltage input. The negative feedback circuit is coupled to the amplifier circuit, and configured to control the first voltage input. The negative feedback circuit includes a first voltage generator and a second voltage generator. The first voltage generator, coupled to the amplifier circuit, is biased by the bias voltage and configured to amplify a third voltage input to generate the first voltage input. The second voltage generator, coupled to the first voltage generator, is configured to generate the third voltage input. A ratio of the first voltage input to the third voltage input is locked according to a ratio of the second voltage input to the third voltage input.

Description

BACKGROUND

The present disclosure relates to bias voltage generation and, more particularly, to a bias voltage generating circuit capable of controlling a transconductance of a main circuit, a signal generator circuit and a power amplifier with immunity to process, voltage and temperature (PVT) variations.

Electrical characteristics of a chip may be sensitive to manufacturing variations and environmental variations. For example, a voltage gain or an amplifier gain of the chip can be affected by PVT variations, resulting in system instability. To improve the system performance, some calibration techniques may be applied to the chip. However, in multi-chip system applications (e.g. phased array beamforming), different chips can present different characteristics from each other, which increases the cost of system calibration. Thus, there is a need in the art for an improved design to reduce the adverse effects resulting from the PVT variations.

SUMMARY

The described embodiments provide a bias voltage generating circuit capable of controlling a transconductance of a main circuit, a signal generator circuit and a power amplifier with immunity to process, voltage and temperature (PVT) variations.

Some embodiments described herein may include a bias voltage generating circuit. The bias voltage generating circuit includes an amplifier circuit and a negative feedback circuit. The amplifier circuit is configured to generate a bias voltage according to a first voltage input and a second voltage input. The negative feedback circuit is coupled to the amplifier circuit, and configured to control the first voltage input. The negative feedback circuit includes a first voltage generator and a second voltage generator. The first voltage generator, coupled to the amplifier circuit, is biased by the bias voltage and configured to amplify a third voltage input to generate the first voltage input. The second voltage generator, coupled to the first voltage generator, is configured to generate the third voltage input. A ratio of the first voltage input to the third voltage input is locked according to a ratio of the second voltage input to the third voltage input.

Some embodiments described herein may include a signal generator circuit. The signal generator circuit includes a main circuit and a bias voltage generating circuit. The main circuit is biased by a bias voltage, and configured to amplify an input signal to generate an output signal. The bias voltage generating circuit is coupled to the main circuit. The bias voltage generating circuit includes an amplifier circuit, a first voltage generator and a second voltage generator. The amplifier circuit is configured to generate the bias voltage according to a first voltage input and a second voltage input. The first voltage generator, coupled to the amplifier circuit, is biased by the bias voltage and configured to amplify a third voltage input to generate the first voltage input. Direct current (DC) biasing of the main circuit is the same as DC biasing of the first voltage generator. The second voltage generator, coupled to the first voltage generator, is configured to generate the third voltage input. A ratio of the first voltage input to the third voltage input is locked according to a ratio of the second voltage input to the third voltage input.

Some embodiments described herein may include a power amplifier. The power amplifier includes a power stage and a preamplifier. The power stage is driven by a drive signal to generate an output signal. The preamplifier, coupled to the power stage, is configured to provide an alternating current (AC) component of the drive signal. The preamplifier includes a main circuit, a first amplifier circuit, a first voltage generator and a second voltage generator. The main circuit, biased by a bias voltage, is configured to amplify an input signal to generate the AC component of the drive signal. The first amplifier circuit is configured to generate the bias voltage according to a first voltage input and a second voltage input. The first voltage generator, coupled to the first amplifier circuit, is biased by the bias voltage and configured to amplify a third voltage input to generate the first voltage input. The second voltage generator, coupled to the first voltage generator, is configured to generate the third voltage input. A ratio of the first voltage input to the third voltage input is locked according to a ratio of the second voltage input to the third voltage input. The power amplifier further includes a third voltage generator. The third voltage generator, coupled to the power stage, is configured to provide a direct current (DC) component of the drive signal.

With the use of the proposed bias scheme, a bias circuit can keep a small-signal gain of a main circuit (biased by the bias circuit) constant/stable against PVT variations. In addition, the proposed bias scheme can be applied to large signal operation to thereby keep output power of a power amplifier constant/stable against PVT variations. The proposed bias scheme can reduce the influence of PVT variations on a chip gain, decrease the cost of measurement and calibration for a single chip, and effectively reduce the gain variations across mass-produced chips to thereby decrease system calibration cost.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a diagram illustrating an exemplary signal generator circuit in accordance with some embodiments of the present disclosure.

FIG. 2 illustrates an implementation of the signal generator circuit shown in FIG. 1 in accordance with some embodiments of the present disclosure.

FIG. 3A illustrates a constant-voltage bias scheme in accordance with some embodiments.

FIG. 3B illustrates a constant-current bias scheme in accordance with some embodiments.

FIG. 4 illustrates another implementation of the signal generator circuit shown in FIG. 1 in accordance with some embodiments of the present disclosure.

FIG. 5 illustrates another implementation of the signal generator circuit shown in FIG. 1 in accordance with some embodiments of the present disclosure.

FIG. 6 illustrates another implementation of the signal generator circuit shown in FIG. 1 in accordance with some embodiments of the present disclosure.

FIG. 7 illustrates another implementation of the signal generator circuit shown in FIG. 1 in accordance with some embodiments of the present disclosure.

FIG. 8 illustrates another implementation of the signal generator circuit shown in FIG. 1 in accordance with some embodiments of the present disclosure.

FIG. 9 illustrates an implementation of the resistance detection circuit shown in FIG. 8 in accordance with some embodiments of the present disclosure.

FIG. 10A illustrates an implementation of the resistance detection circuit shown in FIG. 9 in accordance with some embodiments of the present disclosure.

FIG. 10B illustrates another implementation of the resistance detection circuit shown in FIG. 9 in accordance with some embodiments of the present disclosure.

FIG. 11A illustrates another implementation of the resistance detection circuit shown in FIG. 9 in accordance with some embodiments of the present disclosure.

FIG. 11B illustrates another implementation of the resistance detection circuit shown in FIG. 9 in accordance with some embodiments of the present disclosure.

FIG. 12 is a diagram illustrating a power amplifier in accordance with some embodiments.

FIG. 13 is a diagram illustrating an exemplary power amplifier in accordance with some embodiments of the present disclosure.

FIG. 14 illustrates an implementation of the voltage generator shown in FIG. 13 in accordance with some embodiments of the present disclosure.

FIG. 15 illustrates another implementation of the voltage generator shown in FIG. 13 in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, it will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present.

The present disclosure describes exemplary bias voltage generating circuits, each of which can provide a bias voltage to a main circuit and accordingly lock/control a gain of the main circuit. The exemplary bias voltage generating circuit can keep a gain of the main circuit stable against PVT variations, thereby improving system stability and reducing system calibration cost. For example, the exemplary bias voltage generating circuit can utilize a negative feedback loop to lock a gain of an amplifier, which has the same direct current (DC) bias point as that of the main circuit. The exemplary bias voltage generating circuit can lock/control a transconductance of the main circuit by locking/controlling a transconductance of the amplifier. In some embodiments, at least a portion of the main circuit may be implemented using a small-signal amplifier, such as a low-frequency amplifier, a tuned amplifier or a low-noise amplifier.

The proposed bias scheme can be applied to small signal operation and large signal operation. For example, the present disclosure further describes exemplary signal generator circuits and power amplifiers. The exemplary signal generator circuit can utilize the proposed bias scheme to keep a small-signal gain thereof constant/stable against PVT variations. The exemplary power amplifier can utilize the proposed bias scheme to keep output power thereof constant/stable against PVT variations. Further description is provided below.

FIG. 1 is a diagram illustrating an exemplary signal generator circuit in accordance with some embodiments of the present disclosure. The signal generator circuit 100 can be arranged to generate an output signal Sour according to an input signal S_IN. The signal gain, i.e. a ratio of the output signal Sour to the input signal S_IN, can be controllable or kept constant. In some examples, the signal gain can be expressed in terms of a constant or controllable transconductance.

The signal generator circuit 100 can include a main circuit 102 and a bias voltage generating circuit 106. The main circuit 102 is biased by a bias voltage V_B, and configured to generate the output signal S_OUT by amplifying the input signal S_IN. The main circuit 102 can be used for small-signal amplification. By way of example but not limitation, the main circuit 102 can be implemented using a small-signal amplifier, such as a low-frequency small-signal amplifier, a small-signal tuned amplifier or a small-signal low-noise amplifier.

The bias voltage generating circuit 106 (also referred to as a bias circuit) is coupled to the main circuit 102, and configured to provide the bias voltage V_B to the main circuit 102. The bias voltage generating circuit 106 includes, but is not limited to, an amplifier circuit 110, a voltage generator 120 and a voltage generator 130. The amplifier circuit 110 can be configured to generate the bias voltage V_B according to a voltage input V₁ and a voltage input V₂. For example, the amplifier circuit 110 is configured to amplify a difference between the voltage inputs V₁ and V₂ to generate the bias voltage V_B.

The voltage generator 120 is coupled to the amplifier circuit 110 and biased by the bias voltage V_B. The voltage generator 120 is configured to amplify a voltage input V₃ to generate the voltage input V₁. In other words, the voltage generator 120 and the main circuit 102 can perform signal amplification under the same bias voltage V_B.

The voltage generator 130, coupled to the voltage generator 120, can be configured to generate the voltage input V₃. A voltage gain of the voltage generator 120 (i.e. a ratio of the voltage input V₁ to the voltage input V₃) can be locked according to a ratio of the voltage input V₂ to the voltage input V₃. Note that the voltage generators 120 and 130 can act as a negative feedback circuit 108 that is configured to control the voltage input V₁. For example, the negative feedback circuit 108 can control the voltage input V₁ to be equal to the voltage input V₂. The negative feedback circuit 108 can operate together with the amplifier circuit 110 to lock the voltage gain of the voltage generator 120 (i.e. the ratio of the voltage input V₁ to the voltage input V₃) to the ratio of the voltage input V₂ to the voltage input V₃.

In the present embodiment, the voltage generator 130 can be further configured to provide the voltage input V₂. The voltage generator 130 can adjust at least one of the voltage input V₂ and the voltage input V₃, thereby adjusting the ratio of the voltage input V₁ to the voltage input V₃.

In operation, the voltage generator 130 can generate the voltage inputs V₂ and V₃. The voltage generator 120, biased by the bias voltage V_B, can amplify the voltage input V₃ by a voltage gain to generate the voltage input V₁. The negative feedback circuit 108 can operate together with the amplifier circuit 110 to lock the voltage gain according to the ratio of the voltage input V₂ to the voltage input V₃. Note that direct current (DC) biasing of the main circuit 102 can be the same as DC biasing of the voltage generator 120. For example, a bias point of a transistor in the main circuit 102 can be the same or substantially the same as a bias point of a corresponding transistor in the voltage generator 120. These two transistors can have the same transconductance. Thus, when a transconductance of the voltage generator 120 is kept constant, the main circuit 102 can have a constant transconductance. For example, a ratio of an output current to an input voltage of the main circuit 102 can be kept constant.

By locking or controlling a gain of a voltage generator that is supplied with a bias voltage of a main circuit, the proposed bias scheme can reduce the influence of PVT variations on a chip gain, thereby decreasing the cost of measurement and calibration for a single chip. In addition, the proposed bias scheme can effectively reduce the gain variations across mass-produced chips, thus decreasing system calibration cost.

To facilitate understanding of the present disclosure, some embodiments are given as follows for further description of the proposed bias scheme. Those skilled in the art should appreciate that other embodiments employing the architecture shown in FIG. 1 are also within the contemplated scope of the present disclosure.

FIG. 2 illustrates an implementation of the signal generator circuit 100 shown in FIG. 1 in accordance with some embodiments of the present disclosure. The signal generator circuit 200 includes a main circuit 202_1 and a bias voltage generating circuit 206, which can represent embodiments of the main circuit 102 and the bias voltage generating circuit 106 shown in FIG. 1 respectively.

In the present embodiment, the main circuit 202_1 may be implemented using a radio frequency (RF) small-signal differential low-noise amplifier (LNA). The main circuit 202_1 can be configured to receive an RF input signal R_IN and a reference signal (i.e. a common-mode voltage V_CM) to generate a voltage input V₄, and amplify the voltage input V₄ to generate the output signal Sour. The RF input signal R_IN can serve as an embodiment of the input signal S_IN shown in FIG. 1.

The main circuit 202_1 includes, but is not limited to, an input matching network 203 and a differential pair 204. The input matching network 203 is coupled to the RF input signal R_IN and the common-mode voltage V_CM, and arranged to output the voltage input V₄ to a pair of input terminals T_I11 and T_I12. The voltage input V₄ includes a pair of differential signals V_I11 and V_I12, and a common-mode component of the pair of the differential signals V_I11 and V_I12 is equal to or substantially equal to the common-mode voltage V_CM. In the example of FIG. 2, the input matching network 203 may include a capacitor C₁₀, a resistive element R₁₀, an inductor L₁₀ and a capacitor C₂₀. The input matching network 203 can be represented by an equivalent circuit having a resistive element R_s and an inductor L_g connected in series.

The differential pair 204 is biased by the bias voltage V_B, and arranged to amplify the voltage input V₄ to generate the output signal Sour (e.g. a voltage difference between the output terminals T_O11 and T_O12). In the example of FIG. 2, the differential pair 204 may include a plurality of transistors M₁₀-M₁₄, a plurality of inductors L_s and L_d, a variable capacitor C_d and a resistive element R₁₁.

The bias voltage generating circuit 206 includes an amplifier circuit 210, a voltage generator 220 and a voltage generator 230, which can represent embodiments of the amplifier circuit 110, the voltage generator 120 and the voltage generator 130 shown in FIG. 1 respectively. In the present embodiment, the amplifier circuit 210 can be implemented using a differential difference amplifier (DDA). The voltage input V₁ can represent a voltage difference between a pair of differential signals V_A11 and V_A12 inputted to a pair of input terminals T_A11 and T_A12; the voltage input V₂ can represent a voltage difference between a pair of differential signals V_A21 and V_A22 inputted to a pair of input terminals T_A21 and T_A22. The amplifier circuit 210 is configured to amplify a voltage difference between the voltage inputs V₁ and V₂ to generate the bias voltage V_B. Note that a common-mode voltage of respective voltage signals at the input terminals TAIL and T_A12 can be different from that of respective voltage signals at the input terminals T_A21 and T_A22. For example, the amplifier circuit 210 can be a DDA with a constant transconductance input stage.

The voltage generator 220 can be arranged to amplify a voltage difference between the input terminals T_I21 and T_I22 (i.e. the voltage input V₃) to generate the voltage input V₁ (i.e. a voltage difference between the output terminals T_O21 and T_O22). The voltage gain of the voltage generator 220 can be expressed as a product of a transconductance and a load resistance of the voltage generator 220. For example, the voltage generator 220 can be implemented using a differential pair 224, which may include a plurality of transistors M₂₀-M₂₄ and a plurality of resistive elements R₂₁ and R₂₂. The respective control terminals of the transistors M₂₁ and M₂₂ are coupled to the input terminals T_I21 and T_I22, respectively; the resistive elements R₂₁ and R₂₂ are coupled to the output terminals T_O21 and T_O22, respectively. The voltage gain of the voltage generator 220 can be expressed as g_mR_t, which represents a product of a transconductance g_m and a load resistance R_t of the voltage generator 220. The transconductance g_m can be a transconductance of the transistor M₂₁, and the load resistance R_t can be a resistance of the resistive element R₂₁.

In the embodiment shown in FIG. 2, the width-to-length (W/L) ratio of the transistor M_1i in the differential pair 204 can be m times that of the transistor M_2i in the differential pair 224, where i=0, . . . , 4. For example, the width of the transistor M_1i is m times that of the transistor M_2i, while the length of the transistor M_1i is equal to that of the transistor M_2i. In addition, the resistive elements R₂₁ and R₂₂ in the differential pair 224 have the same resistance R_t, which is 2m times the resistance of the resistive element Ru in the differential pair 204. The bias current of the differential pair 204 can be m times the bias current of the differential pair 224.

The voltage generator 230 can be configured to provide the voltage inputs V₂ and V₃, and adjust a ratio of the voltage input V₂ to the voltage input V₃. The voltage generator 230 can operate together with the voltage generator 220 to provide a negative feedback path to thereby control the voltage input V₁ to be equal to the voltage input V₂. In addition, the voltage generator 230 can be configured to provide a common-mode component of the voltage input V₃ to the main circuit 202_1. The common-mode component of the voltage input V₃ can serve as the common-mode voltage V_CM.

For example, the voltage generator 230 may include a resistor ladder 232 and a plurality of output terminals T_R1-T_R4. The resistor ladder 232 includes a set of resistors and a set of nodes. The set of resistors includes a plurality of resistors R connected in series between a reference voltage Vref and a reference voltage V_SS (e.g. a ground voltage). The resistors R can have a same resistance. The set of nodes may include a plurality of nodes N₁-N₁₆, and can be arranged to provide a set of node voltages V_N1-V_N16 according to the reference voltage Vref and the reference voltage V_SS.

The output terminal T_R1 can be coupled to a first node in the set of nodes, and the output terminal T_R2 can be coupled to a second node in the set of nodes. The voltage difference between the first node and the second node can serve as the voltage input V₂. Similarly, the output terminal T_R3 can be coupled to a third node in the set of nodes, and the output terminal T_R4 can be coupled to a fourth node in the set of nodes. The voltage difference between the third node and the fourth node can serve as the voltage input V₃. Note that a node voltage at a middle node, which is located between the third node and the fourth node, can be provided to the main circuit 202_1 to serve as the common-mode voltage V_CM. The node voltage at the middle node can be equal to or substantially equal to an average of the respective node voltages at the third and the fourth nodes. In other words, the voltage generator 230 can provide a common-mode component of the voltage input V₃ to the main circuit 202_1.

In operation, the output terminals T_R3 and T_R4 can be coupled to the nodes N₉ and N₇, respectively. The voltage difference between the node voltages V_N9 and V_N7, i.e. (9/16>Vref-7/16Vref), is used as the voltage input V₃. The differential pair 224 can amplify the voltage input V₃ to generate the voltage input V₁, which can be determined by the expression V₁=g_m R_t×V₃. In addition, the output terminals T_R1 and T_R2 can be coupled to the nodes N₁₅ and N₁₃, respectively. The voltage difference between the node voltages V_N15 and V_N13, i.e. (15/16Vref-13/16Vref), is used as the voltage input V₂. When the voltage input V₁ is equal to or substantially equal to the voltage input V₂, the voltage gain of the voltage generator 220 can be determined by the expression g_mR_t×V₃=V₂. Thus, the voltage gain (i.e. g_mR_t) can be locked to V₂/V₃, which equals 1 in the example of FIG. 2.

Note that the voltage inputs V₂ and V₃ can be represented by X/16Vref and Y/16Vref, respectively, where X represents the number of resistors connected between the output terminals T_R1 and T_R2, and Y represents the number of resistors connected between the output terminals T_R3 and T_R4. The voltage gain g_mR_t is equal to X/Y, which is insensitive to (or unaffected by) resistance variations in the resistor R and voltage variations in the reference voltage Vref. In other words, the voltage gain g_mR_t can be locked to a constant value X/Y. The bias voltage generating circuit 206 can be referred to as a constant-g_mR_t bias circuit.

In addition, the transconductance g_m (e.g. the transconductance of the transistor M₂₁) can be locked to a constant value. For example, the transconductance g_m can be locked to a constant value when the load resistance R_t (e.g. the resistance of the resistive element R₂₁) is a constant. As another example, the transconductance g_m can be locked to a constant value when V₂/V₃ varies with a change in the load resistance R_t.

In the present embodiment, the equivalent transconductance G_m of the main circuit 202_1 can be determined by the following expression:

$G_m={\mathrm{jg}}_{m1}\frac{\sqrt{\left(L_s+L_g\right)C_{\mathrm{gs}}}}{\left(\frac{g_{m1}{L}_s}{C_{\mathrm{gs}}}+R_s\right)C_{\mathrm{gs}}},$

where g_m1 and C_gs represent a transconductance and an intrinsic gate-to-source capacitance of the transistor M₁₁, respectively. When the transconductance g_m1 of the transistor M₁₁ is a constant, the equivalent transconductance G_m of the main circuit 202_1 can be kept constant. For example, the DC biasing of the differential pair 204 can be the same as that of the differential pair 224. The transconductance g_m1 of the transistor M₁₁ can be a constant when the transconductance of the transistor M₂₁ (i.e. g_m) is locked to a constant value.

Compared with the constant-voltage bias scheme and the constant-current bias scheme, the proposed bias scheme can effectively reduce the influence of PVT variations on the chip gain. For example, referring firstly to FIG. 3A, consider a case where a constant voltage V_BG is applied to the transistor M₁₀ shown in FIG. 2. The constant voltage V_BG can be provided by a bandgap voltage reference. In the example of FIG. 3A, the associated transconductance G_mA is proportional to the electron mobility un and a difference between the constant voltage V_BG and the threshold voltage VTH of the transistor M₁₁:

$G_{\mathrm{mA}}=\frac{\Delta I}{\mathrm{\Delta V}}=\frac{I_1-I_2}{V_{G1}-V_{G2}}\propto {\mu }_n\left(V_{\mathrm{BG}}-V_{\mathrm{TH}}\right).$

Referring to FIG. 3B, consider a case where a constant current I_BX is applied to the transistor M₁₀ shown in FIG. 2. The constant current I_BX can be provided by a constant current generator which includes an operational amplifier A0, a transistor M_B0, a resistor R_B and a transistor M_B1. The resistor R_B can be an off-chip resistor or a high precision resistor. The constant voltage V_BG, provided by a bandgap voltage reference, is applied to the operation amplifier A0 to provide constant currents I_B0 and I_B1. The constant current I_B1 flowing through the transistor M_B1 is mirrored to the transistor M₁₀ to thereby produce the constant current I_BX. In the example of FIG. 3B, the associated transconductance G_mB is proportional to the square root of the electron mobility un:

$G_{\mathrm{mB}}=\frac{\Delta I}{\mathrm{\Delta V}}=\frac{I_1-I_2}{V_{G1}-V_{G2}}\propto \sqrt{{\mu }_n}.$

In view of the above, the main circuit 202_1 shown in FIG. 2, when biased using the constant-voltage bias scheme or the constant-current bias scheme, would have a transconductance which is easily affected by PVT variations. In contrast, with the use of the proposed constant-g_mRt bias scheme, the main circuit 202_1 shown in FIG. 2 can have a transconductance that can be unaffected by PVT variations.

The proposed bias scheme can be applied to various types of main circuits to maintain a constant or controllable transconductance. For example, referring to FIG. 4, another implementation of the signal generator circuit 100 shown in FIG. 1 is illustrated in accordance with some embodiments of the present disclosure. The circuit topology of the signal generator circuit 400 is identical/similar to that of the signal generator circuit 200 shown in FIG. 2 except for the main circuit 402. In the present embodiment, the main circuit 402 can be implemented using a low-frequency small-signal differential amplifier. The main circuit 402 includes, but is not limited to, the transistors M₁₀-M₁₄ shown in FIG. 2, and the resistive elements R₄₁ and R₄₂. Each of the resistive elements R₄₁ and R₄₂ has a resistance 1/m times that of the resistive element R₂₁/R₂₂. The common-mode voltage V_CM provided from the bias voltage generating circuit 206 can serve as a common-mode component of the input signal S_IN (i.e. a common-mode component of the pair of differential signals V₁₂₁ and V₁₂₂) applied to the transistors M₁₁ and M₁₂.

As those skilled in the art can appreciate the operation of the signal generator circuit 400 after reading the above paragraphs directed to FIG. 1 and FIG. 2, further description is omitted here for brevity.

Referring to FIG. 5, another implementation of the signal generator circuit 100 shown in FIG. 1 is illustrated in accordance with some embodiments of the present disclosure. The circuit topology of the signal generator circuit 500 is identical/similar to that of the signal generator circuit 200 shown in FIG. 2 except for the main circuit 502. In the present embodiment, the main circuit 502 can be implemented using an RF small-signal differential tuned amplifier. The main circuit 502 may include the transistors M₁₀-M₁₄, the inductor L_d, the variable capacitor Ca and the resistive element Ru shown in FIG. 2, and further includes the resistive elements R₅₁ and R₅₂ and the capacitors C₅₁ and C₅₂. A differential input signal is inputted to the transistors M₁₁ and M₁₂ through the capacitors C₅₁ and C₅₂. The common-mode voltage V_CM provided from the bias voltage generating circuit 206 can be applied to the transistors M₁₁ and M₁₂ through the resistive elements R₅₁ and R₅₂, respectively.

As those skilled in the art can appreciate the operation of the signal generator circuit 500 after reading the above paragraphs directed to FIG. 1 and FIG. 2, further description is omitted here for brevity.

In some embodiments, the proposed bias scheme can be used for a main circuit having single-ended circuit structure. For example, referring to FIG. 6, an implementation of the signal generator circuit 100 shown in FIG. 1 is illustrated in accordance with some embodiments of the present disclosure. The circuit topology of the signal generator circuit 600 is identical/similar to that of the signal generator circuit 200 shown in FIG. 2 except for the main circuit 602.

In the embodiment shown in FIG. 6, the main circuit 602 can be implemented using an RF small-signal single-ended LNA. The main circuit 602 is configured to receive the RF input signal R_IN and a reference signal (i.e. the common-mode voltage V_CM) to generate the voltage input V₄, and amplify the voltage input V₄ to generate the output signal Sour. The main circuit 602 may include the transistors M₆₀-M₆₂, the capacitors C₆₀-C₆₃, the resistive elements R₆₀ and R₆₁, the inductors L_S6 and L_D6, and a variable capacitor C_D6. The W/L ratio of the transistor M₆₀ can be m times that of the transistor M₂₀, the W/L ratio of the transistor M₆₁ can be 2m times that of the transistor M₂₁, and W/L ratio of the transistor M₆₂ can be 2m times that of the transistor M₂₃. In addition, the resistance of the resistive element R₆₁ can be 1/2m times that of the resistive element R₁₁. The RF input signal R_IN is coupled to the capacitor C₆₀ to produce an alternating current (AC) component of the voltage input V₄ applied to the transistor M₆₁. The common-mode voltage V_CM, provided by the bias voltage generating circuit 206, is coupled to the resistive element R₆₀ to provide a DC component of the voltage input V₄.

As those skilled in the art can appreciate the operation of the signal generator circuit 600 after reading the above paragraphs directed to FIG. 1 and FIG. 2, further description is omitted here for brevity.

In some embodiments, the proposed bias scheme can utilize a single bias voltage generating circuit to bias more than one main circuit. Referring to FIG. 7 and also to FIG. 2, the single bias voltage generating circuit 206 can be shared by the main circuits 202_1-202_8. By way of example but not limitation, each of the main circuits 202_2-202_8 can be implemented using an RF small-signal differential LNA, which can have a circuit topology identical to that of the main circuit 202_1. The bias voltage generating circuit 206 can further supply both of the bias voltage V_B and the common-mode voltage V_CM to the main circuits 202_2-202_8, thereby reducing the overall power consumption of the signal generator circuit 200. In addition, by locking a product of the transconductance g_m and the load resistance R_t of the bias voltage generating circuit 206 to a predetermined value, the proposed bias scheme can keep a transconductance of each main circuit constant.

In the embodiment shown in FIG. 7, the bias voltage generating circuit 206 can be coupled to an external resistive element R_OC, which can be a high precision resistor or an off-chip resistor located outside the bias voltage generating circuit 206. The bias voltage generating circuit 206 can be configured to measure or detect the load resistance according to a reference voltage at the reference terminal T_OC. When the load resistance is temperature independent, the bias voltage generating circuit 206 can measure the load resistance only once; when the load resistance is temperature dependent, the bias voltage generating circuit 206 can measure the load resistance multiple times to trace the load resistance. As a product of the transconductance g_m and the load resistance R_t can be locked to a predetermined value, the bias voltage generating circuit 206 can control the transconductance according to the predetermined value and the measured load resistance.

FIG. 8 illustrates another implementation of the signal generator circuit 100 shown in FIG. 1 in accordance with some embodiments of the present disclosure. The structure of the signal generator circuit 800 is substantially identical/similar to that of the signal generator circuit 200 shown in FIG. 2 except that the bias voltage generating circuit 806 includes a resistance detection circuit 840. The resistance detection circuit 840, coupled to the voltage generator 830, can be configured to detect the load resistance R_t of the voltage generator 220 to generate a control signal CS. The voltage generator 830 can be configured to adjust the ratio of the voltage input V₂ to the voltage input V₃ according to the control signal CS, thereby adjusting the product of the transconductance g_m and the load resistance R_t (i.e. g_mR_t). As the value of load resistance R_t can be measured and the value of the product g_mR_t is controllable, the proposed bias scheme can control the transconductance g_m to reach a target value. For example, when the ratio of the voltage input V₂ to the voltage input V₃ (equivalent to the product g_mR_t) can change in response to a change in the load resistance R_t, the transconductance g_m can be kept constant.

In the present embodiment, the voltage generator 830 includes, but is not limited to, the resistor ladder 232 shown in FIG. 2 and a selection circuit 834. The selection circuit 834 can be configured to select one from among a set of nodes in the resistor ladder 232 according to the control signal CS, and couple the selected node to an output terminal, thereby providing a node voltage at the selected node to the amplifier circuit 210 through the output terminal.

For example, the set of nodes in the resistor ladder 232 may include the nodes N₁-N₁₆ and N_1M-N_15M, and the node N_iM is substantially the midpoint between the nodes N_i and N(+n), where i=1, 2, . . . , 15. The node voltage at the node N_iM is substantially an average of the node voltage at the node N_i and the node voltage at the node N_(i+1). The selection circuit 834 can couple a first node and a second node in the set of nodes to the output terminals T_R1 and T_R2, respectively, thereby providing the voltage input V₂ (i.e. a voltage difference between the first node and the second node) to the amplifier circuit 210.

In operation, the resistance detection circuit 840 can detect that the load resistance R_t is equal to a first value. The selection circuit 834 can couple the nodes N₁₅ and N₁₃ to the output terminals T_R1 and T_R2 respectively, such that the voltage gain of the voltage generator 220 (i.e. g_mR_t) can be locked to one. The value of the transconductance g_m can be equal to an inverse of the first value. When the resistance detection circuit 840 detects that the load resistance R_t increases to a second value which is P times the first value, the selection circuit 834 can control the product g_mR_t to be equal to P, thereby keeping the value of the transconductance g_m constant. For example, the selection circuit 834 can couple the nodes N_15M and N_12M to the output terminals T_R1 and T_R2, respectively, according to the control signal CS when the second value is 1.5 times the first value. In other words, when the value of the load resistance R_t is obtained, the voltage generator 830 can adjust the voltage input V₂ to make the transconductance g_m reach a target value.

Some implementations of the resistance detection circuit 840 are given as follows for illustrative purposes. However, this is not intended to be limiting. The resistance detection circuit 840 can be implemented using other circuit structures without departing from the scope of the present disclosure.

FIG. 9 illustrates an implementation of the resistance detection circuit 840 shown in FIG. 8 in accordance with some embodiments of the present disclosure. The resistance detection circuit 940 includes, but is not limited to, a resistive network 950, a current generator 960 and a processing circuit 970. The resistive network 950 includes N resistive elements R₉₁-R_9N that are coupled to N connection nodes N₉₁-N_9N respectively, where N is a positive integer. The resistance of each resistive element can change in response to a change in a load resistance, such as the load resistance R_t of the voltage generator 220 shown in FIG. 8. By way of example but not limitation, each resistive element and the resistive element R₂₁/R₂₂ shown in FIG. 8 are fabricated using the same process and formed in the same chip. A change in resistance of each resistive element can reflect, or is related to, a change in resistance of the resistive element R₂₁/R₂₂. In addition, the resistive network 950 can be configured to generate a detection voltage VD according to N input voltages V₉₁-V_9N at the N connection nodes N₉₁-N_9N.

The current generator 960 is coupled to the N connection nodes N₉₁-N_9N, and coupled to the external resistive element R_OC through the reference terminal T_OC. The current generator 960 can be configured to generate N currents I₉₁-I_9N according to a reference current I_OC flowing through the external resistive element R_OC. The N currents I₉₁-I_9N can flow through the N resistive elements R₉₁-R_9N to generate the N input voltages V₉₁-V_9N at the N connection nodes N₉₁-N_9N, respectively. For example, the reference current I_OC can be unaffected by (or insensitive to) PVT variations. The current generator 960 can be configured to mirror the reference current I_OC to produce the N currents I₉₁-I_9N.

The processing circuit 970, coupled to the resistive network 950 and the reference terminal T_OC, can be configured to generate the control signal CS according to the detection voltage VD and a reference voltage V_OC at the reference terminal T_OC. For example, the processing circuit 970 can generate the control signal CS by comparing the detection voltage VD with the reference voltage V_OC.

FIG. 10A illustrates an implementation of the resistance detection circuit 940 shown in FIG. 9 in accordance with some embodiments of the present disclosure. The resistance detection circuit 1040A includes a resistive network 1050, a current generator 1060A and a processing circuit 1070, which can represent embodiments of the resistive network 950, the current generator 960 and the processing circuit 970 shown in FIG. 9 respectively.

In the present embodiment, the resistive network 1050 utilizes one resistive element R₉₁ (i.e. N=1) to produce the detection voltage VD. The resistive element R₉₁ includes, but is not limited to, a resistor ladder 1052 and a selection circuit 1054. The resistor ladder 1052 may include a set of resistors and a set of nodes. The set of resistors includes a plurality of resistors R connected in series between the connection node N₉₁ and a reference voltage V_SS (e.g. a ground voltage). The resistance of each resistor R is equal to 1/n times the load resistance R_t, where n is a natural number. For example, when the load resistance R_t is much greater than the resistance of the external resistive element R_OC, n can be a number that is greater or much greater than one. In addition, the set of nodes includes a plurality of nodes N₀-N_k (k is a positive integer greater than one), and is arranged to provide a set of node voltages V_N1-V_NK according to the input voltage V₉₁ at the connection node N₉₁ and the reference voltage V_SS.

The selection circuit 1054 can be configured to select one from among the set of nodes, and couple the selected node to the processing circuit 1070. The node voltage at the selected node serves as the detection voltage VD. For example, the selection circuit 1054 can include k switches, each of which is selectively coupled between a corresponding node and an output terminal TOD. When one of the k switches is switched on, the others are switched off.

The current generator 1060A includes, but is not limited to, an amplifier 1062, a transistor M_100A and a transistor M_101A. The reference voltage V_OC at the reference terminal T_OC is equal to or substantially equal to a reference voltage V_BG, which can be provided by a bandgap voltage reference. In the example of FIG. 10A, the current 191 flowing through the transistor M_101A can be equal to or substantially equal to the reference current I_OC flowing through the transistor M_100A.

The processing circuit 1070 can be configured to generate the control signal CS by comparing the detection voltage VD with the reference voltage V_OC. For example, the processing circuit 1070 may include a comparator 1072, a counter 1074 and a controller 1076. The comparator 1072 is configured to compare the reference voltage V_OC at the reference terminal T_OC and the detection voltage VD at the output terminal TOD. The counter 1074 is configured to generate a count value CV indicating a difference between the reference voltage V_OC and the detection voltage VD. The controller 1076 can be configured to generate the control signals CS_SW and CS according to the count value CV. The control signal CS_SW is provided for controlling the selection circuit 1054, and the control signal CS is provided for controlling the selection circuit 834 shown in FIG. 8.

Consider an example where the node Nm is selected and the count value CV indicates that the detection voltage VD is equal to or substantially equal to the reference voltage V_OC. The load resistance R_t can be determined by the expression:

$I_{\mathrm{OC}}\times R_{\mathrm{OC}}=I_1\times \frac{m}{n}{R}_t.$

When the reference current I_OC and the current I₁ have the same level, the load resistance R_t can be determined by the expression R_t=n/mR_OC. In some embodiments, the load resistance R_t can be measured or calibrated only once when it is temperature independent. In some embodiments, the load resistance R_t can be measured or calibrated multiple times to trace a change in resistance when it is temperature dependent.

FIG. 10B illustrates another implementation of the resistance detection circuit 940 shown in FIG. 9 in accordance with some embodiments of the present disclosure. The circuit topology of the resistance detection circuit 1040B is identical/similar to that of the resistance detection circuit 1040A shown in FIG. 10A except for the current generator 1060B. In the present embodiment, the current generator 1060B may be implemented using the transistors M_100B and M_100B. The current 191 flowing through the transistor M_101B can be equal to or substantially equal to the reference current I_OC flowing through the transistor M_100B. As those skilled in the art can appreciate the operation of the resistance detection circuit 1040B after reading the above paragraphs directed to FIG. 10A, further description is omitted here for brevity.

FIG. 11A illustrates another implementation of the resistance detection circuit 940 shown in FIG. 9 in accordance with some embodiments of the present disclosure. The circuit topology of the resistance detection circuit 1140A is identical/similar to that of the resistance detection circuit 1040A shown in FIG. 10A except for the resistive network 1150 and the current generator 1160A.

The resistive network 1150 can utilize the resistive elements R₉₁ and R₉₂ to produce the detection voltage VD. The resistance of the resistive element R₉₁ is different from the resistance of the resistive element R₉₂. In the present embodiment, the resistance of the resistive element R₉₁ is m times the load resistance R_t (i.e. m×R_t), and the resistance of the resistive element R₉₂ is n times the load resistance R_t (i.e. n×R_t), where m and n are different numbers. For example, when the load resistance R_t is much less than the resistance of the external resistive element R_OC, both m and n can be numbers that are greater or much greater than one.

The resistive network 1150 further includes, but is not limited to, a resistor ladder 1152 and a selection circuit 1154. The resistor ladder 1152 may include a set of resistors and a set of nodes. The set of resistors includes a plurality of resistors R_big connected in series between the connection nodes N₉₁ and N₉₂. The resistance of each resistor R_big is much greater than the load resistance R_t. The set of nodes includes a plurality of nodes N₀-N_k (k is a positive integer greater than one), and is arranged to provide a set of node voltages V_N1-V_NK according to the input voltage V₉₁ and the input voltage V92. The selection circuit 1154 can be configured to select one from among the set of nodes, and couple the selected node to the processing circuit 1070. A node voltage at the selected node can serve as the detection voltage VD.

The current generator 1160A includes, but is not limited to, an amplifier 1162 and a plurality of transistors M_110A-M_112A. The reference voltage V_OC at the reference terminal T_OC is equal to or substantially equal to a reference voltage V_BG, which can be provided by a bandgap voltage reference. In the example of FIG. 11A, each of the current I₉₁ (flowing through the transistor M_111A) and the current 192 (flowing through the transistor M_112A) can be equal to or substantially equal to the reference current I_OC flowing through the transistor M_110A.

Consider an example where the node Na is selected and the count value CV indicates that the detection voltage VD is equal to or substantially equal to the reference V_OC. The load resistance R_t can be determined by the expression:

$I_{\mathrm{OC}}\times R_{\mathrm{OC}}=\frac{{\mathrm{bR}}_{\mathrm{big}}\left(I_1\times {\mathrm{mR}}_t\right)+{\mathrm{aR}}_{\mathrm{big}}\left(I_2\times {\mathrm{nR}}_t\right)}{R_{\mathrm{big}}},$

where a is a positive integer, and b is equal to (k−a). When the reference current I_OC, the current I₁ and the current I₂ have the same level, the load resistance R_t can be determined by the expression R_t=a+b/an+bm R_OC. In some embodiments, the load resistance R_t can be measured or calibrated only once when it is temperature independent. In some embodiments, the load resistance R_t can be measured or calibrated multiple times to trace a change in resistance when it is temperature dependent.

FIG. 11B illustrates another implementation of the resistance detection circuit 940 shown in FIG. 9 in accordance with some embodiments of the present disclosure. The circuit topology of the resistance detection circuit 1140B is identical/similar to that of the resistance detection circuit 1140A shown in FIG. 11A except for the current generator 1160B. In the present embodiment, the current generator 1160B may be implemented using the transistors M_110B-M_112B. Each of the current 191 (flowing through the transistor M_111B) and the current 192 (flowing through the transistor M_112B) can be equal to or substantially equal to the reference current I_OC flowing through the transistor M_110B. As those skilled in the art can appreciate the operation of the resistance detection circuit 1140B after reading the above paragraphs directed to FIG. 10A, FIG. 10B and FIG. 11A, further description is omitted here for brevity.

Referring again to FIG. 8, as the product of the transconductance g_m and the load resistance R_t can be controlled, the proposed bias scheme can control the transconductance g_m to be temperature independent or temperature dependent. For example, when the load resistance R_t is a constant, the bias voltage generating circuit 806 can control the transconductance g_m to be a constant by locking the product g_mR_t to be a fixed value, thereby making the transconductance G_m of the main circuit 202_1 a constant. In other words, the transconductance g_m/G_m can be kept constant over temperature. As another example, when the load resistance R_t has a positive temperature coefficient, the bias voltage generating circuit 806 can control the transconductance g_m to have a negative temperature coefficient by locking g_mR_t to be a fixed value, thereby making the transconductance G_m of the main circuit 202_1 have a negative temperature coefficient. As still another example, when the load resistance R_t has a negative temperature coefficient, the bias voltage generating circuit 806 can control the transconductance g_m to have a positive temperature coefficient by locking g_mR_t to be a fixed value, thereby making the transconductance G_m of the main circuit 202_1 have a positive temperature coefficient.

In some embodiments, the proposed bias scheme can be applied to large signal operation, such as operation of a power amplifier. Referring firstly to FIG. 12, a power stage of the power amplifier 1200 (e.g. a class AB amplifier) can include a transistor M₁₂₁, an inductor L₁₂₁ and a matching network 1201. The transistor M₁₂₁ is driven by a drive voltage V_DIN. The matching network 1201 includes an inductor L₁₂₂, capacitors C₁₂₁ and C₁₂₂, and a resistor R₁₂₀. In the embodiment of FIG. 12, changes in PVT can cause variations in a drain current I_D of the transistor M₁₂₁, resulting in output power variations.

For example, a threshold voltage of the transistor M₁₂₁ changes with temperature, causing variations in the drain current I_D. When temperature rises, the threshold voltage of the transistor M₁₂₁ decreases, resulting in an increase in the drain current I_D; when temperature decreases, the threshold voltage of the transistor M₁₂₁ increases, resulting in a decrease in the drain current I_D. As another example, electron mobility changes with temperature, causing variations in the drain current I_D. When temperature rises, the electron mobility decreases, resulting in a decrease in the drain current I_D; when temperature decreases, the electron mobility increases, resulting in an increase in the drain current I_D. Note that the electron mobility and the threshold voltage have opposite effects on the drain current I_D when temperature changes.

The proposed bias scheme can be applied to a power amplifier to keep output power of the power amplifier constant/stable against PVT variations. FIG. 13 is a diagram illustrating an exemplary power amplifier in accordance with some embodiments of the present disclosure. The power amplifier 1300 can be implemented as a class AB amplifier for illustrative purposes. Those skilled in the art can appreciate that the proposed bias scheme can be applied to other types/classes of amplifiers without departing from the scope of the present disclosure.

The power amplifier 1300 includes a power stage 1310 and a driver stage 1320. The power stage 1310 can be driven by a drive signal DS to generate an output signal R_OUT. The power stage 1310 includes, but is not limited to, a plurality of transistors M₁₃₁-M₁₃₄ and a plurality of matching networks 1302, 1304 and 1306. The drive signal DS includes an input signal AS_IN and an input voltage V_BX, and the input signal AS_IN includes a pair of differential input voltages V_A1 and V_A2. The input voltage V_A1/V_A2 serves as an AC component of the drive signal DS, and the input voltage V_BX serves as a DC component of the drive signal DS. The matching network 1302 is coupled to the input signal AS_IN and the input voltage V_BX, and arranged to output the drive voltages V_G1 and V_G2 (e.g. a pair of differential voltages) to the transistors M₁₃₁ and M₁₃₂, respectively.

The matching network 1302 may include, but is not limited to, a plurality of capacitors C₁₃₁-C₁₃₃, and a plurality of resistors R₁₃₁ and R₁₃₂. The input voltage V_A1 is capacitively coupled to the transistor M₁₃₁ to provide an AC component of the drive voltage V_G1, and the input voltage V_BX is coupled to the transistor M₁₃₁ through the resistor R₁₃₁ to provide a DC component of the drive voltage V_G1. The input voltage V_A2 is capacitively coupled to the transistor M₁₃₂ to provide an AC component of the drive voltage V_G2, and the input voltage V_BX is coupled to the transistor M₁₃₂ through the resistor R₁₃₂ to provide a DC component of the drive voltage V_G2. In addition, the matching network 1304 may include a resistor R₁₃₃ and a capacitor C₁₃₄. The matching network 1306 may include a plurality of inductors L₁₃₁ and L₁₃₂, and a plurality of capacitors C₁₃₅ and C₁₃₆.

The driver stage 1320 can be configured to provide the drive signal DS, thereby keeping a transistor current (e.g. a drain current I_D1/I_D2) substantially constant or stable against PVT variations. Constant/stable transistor current can contribute to constant/stable output power. For example, as a change in electron mobility due to a rise in temperature can cause a decrease in drain current, the drive signal DS may include a signal component having a positive temperature coefficient to compensate for the effect of changes in electron mobility on the drain current I_D1/I_D2. As another example, as a change in threshold voltage due to a rise in temperature can cause an increase in drain current, the drive signal DS may include a signal component having a negative temperature coefficient to compensate for the effect of changes in threshold voltage on the drain current I_D1/I_D2.

In the present embodiment, the driver stage 1320 may include the signal generator circuit 100 shown in FIG. 1 and a voltage generator 1330. The signal generator circuit 100 can serve as a preamplifier that is configured to provide an AC component of the drive signal DS (i.e. the input voltage V_A1/V_A2). The main circuit 102 can be configured to generate the AC component of the drive signal DS (i.e. the input voltage V_A1/V_A2) by amplifying the input signal S_IN (e.g. an RF input signal). In addition, the voltage generator 1330 is coupled to the power stage 1302, and configured to provide the DC component of the drive signal DS (i.e. the input voltage V_BX).

One of the signal generator circuit 100 and the voltage generator 1330 can be used to compensate for the effect of changes in electron mobility on the drain current I_D1/I_D2, and the other can be used to compensate for the effect of changes in threshold voltage on the drain current I_D1/I_D2. For example, the signal generator circuit 100 can be configured to provide the input voltage V_A1/V_A2 (i.e. an AC component of the drive signal DS) having a positive temperature coefficient, thereby compensating for the effect of changes in electron mobility on the drain current I_D1/I_D2. As another example, the voltage generator 1330 can be configured to provide the input voltage V_BX (i.e. a DC component of the drive signal DS) having a negative temperature coefficient, thereby compensating for the effect of changes in threshold voltage on the drain current I_D1/I_D2.

In the embodiment shown in FIG. 13, the voltage generator 120 can be configured to provide the transconductance g_m having a positive temperature coefficient, and the main circuit 102 can be configured to provide the transconductance G_m having a positive temperature coefficient according to the transconductance g_m. For example, the voltage generator 130 can control the ratio of the voltage input V₂ to the voltage input V₃ to thereby control a product of the transconductance g_m and the load resistance R_t. When the load resistance R_t has a negative temperature coefficient, the transconductance g_m can have a positive temperature coefficient if the product g_mR_t is locked to a fixed value or adjusted to a suitable value.

Note that the signal generator circuit 100 can be implemented using the signal generator circuit 200 shown in FIG. 2, the signal generator circuit 400 shown in FIG. 4, the signal generator circuit 500 shown in FIG. 5, the signal generator circuit 600 shown in FIG. 6, the signal generator circuit 800 shown in FIG. 8, or other signal generator circuits utilizing the proposed bias scheme. As those skilled in the art can appreciate the operation of the signal generator circuit 100 after reading the above paragraphs directed to FIG. 1 to FIG. 11, similar description is omitted here for brevity.

FIG. 14 illustrates an implementation of the voltage generator 1330 shown in FIG. 13 in accordance with some embodiments of the present disclosure. The input voltage V_BX outputted from an output terminal T_OBX can have a zero, positive or negative temperature coefficient. In the present embodiment, the voltage generator 1430 may include transistors M₁₄₁ and M₁₄₂, an amplifier circuit 1436, diode-connected transistors Q₁ and Q₂, and resistive elements R₁₄₁-R₁₄₃.

A connection terminal of the transistor M₁₄₂ is coupled to the output terminal T_OBX. An output terminal T_OAP of the amplifier circuit 1436 is coupled to respective control terminals of the transistors M₁₄₁ and M₁₄₂, and an input terminal TIN of the amplifier circuit 1436 is coupled to a connection terminal of the transistor M₁₄₁ through the resistive element R₁₄₁. The input terminal TIN of the amplifier circuit 1436 is further coupled to a connection terminal T_Q1 of the diode-connected transistor Q₁. In addition, the resistive element R₁₄₂ is coupled between the output terminal T_OBX and an input terminal T_IP of the amplifier circuit 1436. The resistive element R₁₄₃ is coupled between the input terminal T_IP of the amplifier circuit 1436 and a connection terminal T_Q2 of the diode-connected transistor Q₂.

The input voltage V_BX can be determined by the following expression:

$V_{\mathrm{BX}}=V_{\mathrm{BE}2}+\left(1+\frac{R_{142}}{R_{143}}\right)\left(V_{\mathrm{BE}1}-V_{\mathrm{BE}2}\right),$

where the voltage V_BE1 represents a voltage drop across the diode-connected transistor Q₁ (e.g. a base-emitter voltage of a bipolar junction transistor (BJT)), and the voltage V_BE2 represents a voltage drop across the diode-connected transistor Q₂ (e.g. a base-emitter voltage of a BJT). Note that the voltage V_BE1 may have a positive temperature coefficient, and the voltage difference (V_BE1-V_BE2) may have a negative temperature coefficient. The voltage generator 1430A can generate the input voltage V_BX having a zero, positive or negative temperature coefficient by adjusting the resistance of the resistive element R₁₄₂ and/or the resistance of the resistive element R₁₄₃. In some embodiments, when the voltage generator 1430 is configured to generate the input voltage V_BX having a negative temperature coefficient, the input voltage V_BX can be coupled to the transistor M₁₃₁/M₁₃₂ shown in FIG. 13 to compensate for the effect of changes in threshold voltage on the drain current I_D1/I_D2.

FIG. 15 illustrates another implementation of the voltage generator 1330 shown in FIG. 13 in accordance with some embodiments of the present disclosure. The circuit structure of the voltage generator 1530 is identical/similar to that of the voltage generator 1430 shown in FIG. 14 except for the resistor network 1531 coupled to the input terminal T_IP. The resistive elements R₁₄₂ and R₁₄₃ shown in FIG. 14 can be implemented using the resistor ladder 1532. In the embodiment shown in FIG. 15, the resistor ladder 1532 includes a set of resistors and a set of nodes. The set of resistors includes a plurality of resistors R connected in series between the output terminal T_OBX and the connection terminal T_Q2 of the diode-connected transistor Q₂.

The resistor network 1531 further includes a selection circuit 1534. The selection circuit 1534 can be configured to select one from among the set of nodes, and couple the selected node to the input terminal T_IP. A first portion of the resistor ladder 1532, connected between the output terminal T_OBX and the selected node, can serve as the resistive element R₁₄₂ shown in FIG. 14; a second portion of the resistor ladder 1532, connected between the selected node and the connection terminal T_Q2, can serve as the resistive element R₁₄₃ shown in FIG. 14. In the example of FIG. 15, the selection circuit 1534 can include a plurality of switches, each of which is selectively coupled between input terminal T_IP and a corresponding node. When one of the switches is switched on, the others are switched off.

The circuit topologies described above are provided for illustrative purposes only, and are not intended to limit the scope of the present disclosure. In some embodiments, the voltage generator 1330 shown in FIG. 13 can be implemented using other circuit structures capable of provide a voltage having a negative temperature coefficient without departing from the scope of the present disclosure. In some embodiments, the power stage 1310 shown in FIG. 13 can be implemented using other circuit structures without departing from the scope of the present disclosure.

With the use of the proposed bias scheme, a bias circuit can keep a small-signal gain of a main circuit (biased by the bias circuit) constant/stable against PVT variations. In addition, the proposed bias scheme can be applied to large signal operation to thereby keep output power of a power amplifier constant/stable against PVT variations. The proposed bias scheme can reduce the influence of PVT variations on a chip gain, decrease the cost of measurement and calibration for a single chip, and effectively reduce the gain variations across mass-produced chips to thereby decrease system calibration cost.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A bias voltage generating circuit, comprising: an amplifier circuit, configured to generate a bias voltage according to a first voltage input and a second voltage input; anda negative feedback circuit, coupled to the amplifier circuit and configured to control the first voltage input, the negative feedback circuit comprising: a first voltage generator, coupled to the amplifier circuit, the first voltage generator being biased by the bias voltage, and configured to amplify a third voltage input to generate the first voltage input; anda second voltage generator, coupled to the first voltage generator, the second voltage generator being configured to generate the third voltage input, wherein a ratio of the first voltage input to the third voltage input is locked according to a ratio of the second voltage input to the third voltage input.

2. The bias voltage generating circuit of claim 1, wherein the ratio of the first voltage input to the third voltage input is a product of a transconductance and a load resistance of the first voltage generator; the ratio of the second voltage input to the third voltage input changes in response to a change in the load resistance, and the transconductance is kept constant.

3. The bias voltage generating circuit of claim 1, wherein the ratio of the first voltage input to the third voltage input is a product of a transconductance and a load resistance of the first voltage generator; the bias voltage generating circuit further comprises: a resistance detection circuit, coupled to the second voltage generator, the resistance detection circuit being configured to detect the load resistance to generate a control signal, wherein the second voltage generator is configured to provide the second voltage input according to the control signal.

4. The bias voltage generating circuit of claim 3, wherein the resistance detection circuit comprises: a resistive network, having N resistive elements coupled to N connection nodes respectively, N being a positive integer, wherein a resistance of each resistive element changes in response to a change in the load resistance, and the resistive network is configured to generate a detection voltage according to N input voltages at the N connection nodes;a current generator, coupled to the N connection nodes and coupled to an external resistive element through a reference terminal, the current generator being configured to generate N currents according to a reference current flowing through the external resistive element, wherein the N currents flow through the N resistive elements to generate the N input voltages at the N connection nodes, respectively; anda processing circuit, coupled to the resistive network and the reference terminal, the processing circuit being configured to generate the control signal according to the detection voltage and a first reference voltage at the reference terminal.

5. The bias voltage generating circuit of claim 4, wherein N=1 and the resistive element comprises: a resistor ladder, comprising a set of resistors and a set of nodes, the set of resistors comprising a plurality of resistors connected in series between the connection node and a second reference voltage, the set of nodes being arranged to provide a set of node voltages according to the input voltage at the connection node and the second reference voltage; anda selection circuit, configured to select one from among the set of nodes and couple the selected node to the processing circuit, wherein a node voltage at the selected node serves as the detection voltage;wherein the processing circuit is configured to generate the control signal by comparing the detection voltage with the first reference voltage.

6. The bias voltage generating circuit of claim 4, wherein the N resistive elements comprises a first resistive element and a second resistive element; a resistance of the first resistive element is different from a resistance of the second resistive element; the N connection nodes comprises a first connection node and a second connection node; the first connection node is coupled to the first resistive element, and the second connection node is coupled to the second resistive element; the resistive network further comprises: a resistor ladder, comprising a set of resistors and a set of nodes, the set of resistors comprising a plurality of resistors connected in series between the first connection node and the second connection node, the set of nodes being arranged to provide a set of node voltages according to the input voltage at the first connection node and the input voltage at the second connection node; anda selection circuit, configured to select one from among the set of nodes and couple the selected node to the processing circuit, wherein a node voltage at the selected node serves as the detection voltage;wherein the processing circuit is configured to generate the control signal by comparing the first reference voltage and the detection voltage.

7. The bias voltage generating circuit of claim 1, wherein the second voltage generator comprises: a resistor ladder, comprising a set of resistors and a set of nodes, the set of resistors comprising a plurality of resistors connected in series between a first reference voltage and a second reference voltage, the set of nodes being arranged to provide a set of node voltages according to the first reference voltage and the second reference voltage;a first output terminal, coupled to a first node in the set of nodes;a second output terminal, coupled to a second node in the set of nodes, wherein a voltage difference between the first node and the second node serves as the second voltage input;a third output terminal, coupled to a third node in the set of nodes; anda fourth output terminal, coupled to a fourth node in the set of nodes, wherein a voltage difference between the third node and the fourth node serves as the third voltage input.

8. The bias voltage generating circuit of claim 7, wherein the second voltage generator further comprises: a selection circuit, configured to select the first node from among the set of nodes and couple the first node to the first output terminal.

9. A signal generator circuit, comprising: a main circuit, biased by a bias voltage and configured to provide an output signal according to an input signal; anda bias voltage generating circuit, coupled to the main circuit, the bias voltage generating circuit comprising: an amplifier circuit, configured to generate the bias voltage according to a first voltage input and a second voltage input;a first voltage generator, coupled to the amplifier circuit, the first voltage generator being biased by the bias voltage and configured to amplify a third voltage input to generate the first voltage input, wherein direct current (DC) biasing of the main circuit is the same as DC biasing of the first voltage generator; anda second voltage generator, coupled to the first voltage generator, the second voltage generator being configured to generate the third voltage input, wherein a ratio of the first voltage input to the third voltage input is locked according to a ratio of the second voltage input to the third voltage input.

10. The signal generator circuit of claim 9, wherein the main circuit is configured to receive the input signal and a reference signal to generate a fourth voltage input, and amplify the fourth voltage input to generate the output signal; the second voltage generator is further configured to provide a common-mode component of the third voltage input to the main circuit, and the common-mode component of the third voltage input serves as the reference signal.

11. The signal generator circuit of claim 9, wherein the first voltage generator and the second voltage generator are arranged to provide a negative feedback path to control the first voltage input to be equal to the second voltage input.

12. The signal generator circuit of claim 9, wherein the ratio of the first voltage input to the third voltage input is a product of a transconductance and a load resistance of the first voltage generator; the ratio of the second voltage input to the third voltage input changes in response to a change in the load resistance, and the transconductance is kept constant.

13. The signal generator circuit of claim 9, wherein the ratio of the first voltage input to the third voltage input is a product of a transconductance and a load resistance of the first voltage generator; the bias voltage generating circuit further comprises: a resistance detection circuit, coupled to the second voltage generator, the resistance detection circuit being configured to detect the load resistance to generate a control signal, wherein the second voltage generator is configured to provide the second voltage input according to the control signal.

14. The signal generator circuit of claim 9, wherein the second voltage generator comprises: a resistor ladder, comprising a set of resistors and a set of nodes, the set of resistors comprising a plurality of resistors connected in series between a first reference voltage and a second reference voltage, the set of nodes being arranged to provide a set of node voltages according to the first reference voltage and the second reference voltage;a first output terminal, coupled to a first node in the set of nodes;a second output terminal, coupled to a second node in the set of nodes, wherein a voltage difference between the first node and the second node serves as the second voltage input;a third output terminal, coupled to a third node in the set of nodes; anda fourth output terminal, coupled to a fourth node in the set of nodes, wherein a voltage difference between the third node and the fourth node serves as the third voltage input.

15. A power amplifier, comprising: a power stage, driven by a drive signal to generate an output signal;a preamplifier, coupled to the power stage, the preamplifier being configured to provide an alternating current (AC) component of the drive signal, the preamplifier comprising: a main circuit, biased by a bias voltage and configured to amplify an input signal to generate the AC component of the drive signal;a first amplifier circuit, configured to generate the bias voltage according to a first voltage input and a second voltage input;a first voltage generator, coupled to the first amplifier circuit, the first voltage generator being biased by the bias voltage and configured to amplify a third voltage input to generate the first voltage input; anda second voltage generator, coupled to the first voltage generator, the second voltage generator being configured to generate the third voltage input, wherein a ratio of the first voltage input to the third voltage input is locked according to a ratio of the second voltage input to the third voltage input; anda third voltage generator, coupled to the power stage, the third voltage generator being configured to provide a direct current (DC) component of the drive signal.

16. The power amplifier of claim 15, wherein the AC component of the drive signal has a positive temperature coefficient, and the DC component of the drive signal has a negative temperature coefficient.

17. The power amplifier of claim 15, wherein the first voltage generator is configured to provide a first transconductance having a positive temperature coefficient, and the main circuit is configured to provide a second transconductance having a positive temperature coefficient according to the first transconductance.

18. The power amplifier of claim 17, wherein the ratio of the first voltage input to the third voltage input is a product of the first transconductance and a load resistance of the first voltage generator, and the load resistance of the first voltage generator has a negative temperature coefficient.

19. The power amplifier of claim 15, wherein an output terminal of the third voltage generator is arranged to provide the DC component of the drive signal; the third voltage generator comprises: a first transistor and a second transistor, wherein a connection terminal of the second transistor is coupled to the output terminal of the third voltage generator;a second amplifier circuit, wherein an output terminal of the second amplifier circuit is coupled to respective control terminals of the first transistor and the second transistor, and a first input terminal of the second amplifier circuit is coupled to a connection terminal of the first transistor;a first diode-connected transistor and a second diode-connected transistor, wherein a connection terminal of the first diode-connected transistor is coupled to the first input terminal of the second amplifier circuit; anda first resistive element and a second resistive element, wherein the first resistive element is coupled between the output terminal of the third voltage generator and a second input terminal of the second amplifier circuit, and the second resistive element is coupled between the second input terminal of the second amplifier circuit and a connection terminal of the second diode-connected transistor.

20. The power amplifier of claim 19, wherein the first resistive element is a first portion of a resistor ladder, and the second resistive element is a second portion of the resistor ladder; the resistor ladder comprises a set of resistors and a set of nodes; the set of resistors comprises a plurality of resistors connected in series between the output terminal of the third voltage generator and the connection terminal of the second diode-connected transistor; the third voltage generator further comprises: a selection circuit, configured to select one from among the set of nodes and couple the selected node to the second input terminal of the second amplifier circuit, wherein the first portion of the resistor ladder is connected between the output terminal of the third voltage generator and the selected node, and the second portion of the resistor ladder is connected between the selected node and the connection terminal of the second diode-connected transistor.