Claims
- 1. A BiCMOS circuit providing non-inverting logic operation comprising:
- a first bipolar transistor having its collector coupled to a first operating potential, its base connected to an input node and its emitter coupled to an output node;
- a first field-effect device coupled between said output node and a second operating potential;
- second and third field-effect devices coupled as a CMOS inverter connected between said first and second operating potentials, the output of said inverter being coupled to the gate of said first field-effect device;
- the gates of said second and third field-effect devices being connected to said input node such that when a logical high signal is applied to said input node said output node is driven to a high logic gate and when a logical low signal is applied to said input node said output node is driven to a low logic state approximately equal to said second operating potential.
- 2. The circuit of claim 1 wherein said first operating potential is a high positive potential, and said second operating potential is ground.
- 3. The circuit of claim 2 wherein said first bipolar transistor comprises an NPN transistor.
- 4. The circuit of claim 3 wherein said first and third field-effect devices comprise n-channel MOS transistors, and said second field-effect device comprises a p-channel MOS transistor.
- 5. The circuit of claim 4 wherein switching in said circuit from a high to a low state occurs when said input node falls one p-channel MOS threshold below said high positive supply potential.
- 6. The circuit of claim 4 wherein said inverting node of said inverter is coupled to the base of a second bipolar transistor having its emitter coupled to gate of said first field-effect device and its collector coupled to said first operating potential, said second bipolar transistor providing faster switching when said circuit drives relatively large capacitive loads.
- 7. The circuit of claim 6 further comprising a fourth field-effect device coupled between said emitter of said second bipolar transistor and said second operating potential, the gate of said fourth field-effect device being coupled to said input.
Parent Case Info
This is a continuation of application Ser. No. 07/540,342, filed Jun. 19, 1990, now U.S. Pat. No. 5,049,765.
US Referenced Citations (8)
Continuations (1)
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Number |
Date |
Country |
Parent |
540342 |
Jun 1990 |
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