Bidirectional active signal management in cables and other interconnects

Abstract

Transmit-side active signal management circuitry applies one or more active signal management processes to a digital signal at a transmit side of an interconnect. At the receive side of the interconnect, receive-side active signal management circuitry applies one or more corresponding active signal management processes, as appropriate, to the received digital signal to recover the information represented by the original digital signal. The interconnect can include a cable used to transmit the signals between a source device and a destination device, whereby one or both of the transmit-side active signal management circuitry and the receive-side active signal management circuitry is implemented at a corresponding cable receptacle of the cable. Alternately, one or both of the transmit-side active signal management circuitry and the receive-side active signal management circuitry can be implemented at a cable adaptor, thereby permitting the use of a passive cable interconnect to transmit the signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference symbols in different drawings indicates similar or identical items.

FIG. 1 is a block diagram illustrating a signal management system for improving transmitted signal quality and reach and reducing electromagnetic interference (EMI) in accordance with at least one embodiment of the present disclosure.

FIG. 2 is a diagram illustrating the signal management system of FIG. 1 implemented in a cable in accordance with at least one embodiment of the present disclosure.

FIG. 3 is a perspective view diagram illustrating a cable receptacle of the cable assembly of FIG. 2 in accordance with at least one embodiment of the present disclosure.

FIG. 4 is a diagram illustrating the signal management system of FIG. 1 as implemented in a cable adaptor in accordance with at least one embodiment of the present disclosure.

FIG. 5 is a perspective view diagram illustrating the cable adaptor of FIG. 4 in accordance with at least one embodiment of the present disclosure.

FIG. 6 is a block diagram illustrating an implementation of active signal management circuitry utilizing quasi differential to true differential signal conversion in accordance with at least one embodiment of the present disclosure.

FIG. 7 is a block diagram illustrating an implementation of active signal management circuitry utilizing quasi differential to true differential signal conversion in accordance with at least one embodiment of the present disclosure.

FIG. 8 is a block diagram illustrating an implementation of active signal management circuitry utilizing encoding and quasi differential to true differential signal conversion in accordance with at least one embodiment of the present disclosure.

FIG. 9 is a block diagram illustrating an implementation of active signal management circuitry utilizing true differential to quasi differential signal conversion and decoding in accordance with at least one embodiment of the present disclosure.

FIG. 10 is a block diagram illustrating an implementation of active signal management circuitry utilizing deserialization-serialization and encoding in accordance with at least one embodiment of the present disclosure.

FIG. 11 is a block diagram illustrating an implementation of active signal management circuitry utilizing deserialization-serialization and decoding in accordance with at least one embodiment of the present disclosure.

FIG. 12 is a block diagram illustrating an implementation of active signal management circuitry utilizing a quasi differential receiver and transmitter in accordance with at least one embodiment of the present disclosure.

FIG. 13 is a block diagram illustrating an implementation of active signal management circuitry utilizing a true differential receiver and transmitter in accordance with at least one embodiment of the present disclosure.

FIG. 14 is a circuit diagram illustrating an implementation of a quasi differential signal transmitter in accordance with at least one embodiment of the present disclosure.

FIG. 15 is a circuit diagram illustrating an implementation of a true differential signal transmitter in accordance with at least one embodiment of the present disclosure.

FIG. 16 is a circuit diagram illustrating an implementation of a quasi differential signal receiver in accordance with at least one embodiment of the present disclosure.

FIG. 17 is a circuit diagram illustrating an implementation of a true differential signal receiver in accordance with at least one embodiment of the present disclosure.

FIG. 18 is a circuit diagram illustrating an implementation of a quasi-to-true differential signaling converter in accordance with at least one embodiment of the present disclosure.

FIG. 19 is a circuit diagram illustrating an implementation of a true-to-quasi differential signaling converter in accordance with at least one embodiment of the present disclosure.

FIG. 20 is a diagram illustrating a bidirectional active signal management system employed at respective ends of a cable assembly in accordance with at least one embodiment of the present disclosure.

FIG. 21 is a diagram illustrating an alternate implementation of a bidirectional active signal management system employed at respective ends of a cable assembly in accordance with at least one embodiment of the present disclosure.

FIG. 22 is a diagram illustrating a direction detection module in accordance with at least one embodiment of the present disclosure.

FIG. 23 is a diagram illustrating an implementation of a signal processing path of a bidirectional active signal management system in accordance with at least one embodiment of the present disclosure.

FIG. 24 is a diagram illustrating another implementation of a signal processing path of a bidirectional active signal management system in accordance with at least one embodiment of the present disclosure.

FIG. 25 is a block diagram illustrating an implementation of active signal management circuitry utilizing a bit alignment module in accordance with at least one embodiment of the present disclosure.

FIG. 26 is a block diagram illustrating an implementation of active signal management circuitry utilizing a skew management module in accordance with at least one embodiment of the present disclosure.

FIG. 27 is a block diagram illustrating an implementation of active signal management circuitry utilizing a control symbol encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 28 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 29 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 30 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 31 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 32 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 33 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 34 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 35 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 36 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 37 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 38 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 39 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 40 is a state machine diagram illustrating an operation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

Claims

1. An apparatus comprising: a first bidirectional port;a second bidirectional port;active signal management circuitry having an input to receive an input digital signal and an output to provide an output digital signal, wherein the active signal management circuitry is configured to generate the output digital signal based on the input digital signal;a first transceiver comprising a first input and a first output coupled to the first bidirectional port, a second input selectively coupleable to the output of the active signal management circuitry, and a second output selectively coupleable to the input of the active signal management circuitry;a second transceiver comprising a first input and a first output coupled to the second bidirectional port, a second input selectively coupleable to the output of the active signal management circuitry, and a second output selectively coupleable to the input of the active signal management circuitry; anda switch component configured to: couple the second output of the first transceiver to the input of the active signal management circuitry and couple the output of the active signal management circuitry to the second input of the second transceiver in response to a first direction signal having a first state; andcouple the second output of the second transceiver to the input of the active signal management circuitry and couple the output of the active signal management circuitry to the second input of the second transceiver in response to a first direction signal having a second state.

2. The apparatus of claim 1, wherein: the first transceiver comprises: a first transmitter having an input coupled to the second input of the first transceiver and an output coupled to the first output of the first transceiver; anda first receiver having an input coupled to the first input of the first transceiver and an output coupled to the second output of the first transceiver; andthe second transceiver comprises: a second transmitter having an input coupled to the second input of the second transceiver and an output coupled to the first output of the second transceiver; anda second receiver having an input coupled to the first input of the second transceiver and an output coupled to the second output of the second transceiver.

3. The apparatus of claim 2, wherein: the first transmitter comprises a quasi differential signal transmitter;the first receiver comprises a quasi differential signal receiver;the second transmitter comprises a true differential signal transmitter; andthe second receiver comprises a true differential signal receiver.

4. The apparatus of claim 1, wherein the active signal management circuitry comprises: a noise source configured to provide a digital noise signal; anda modification module configured to modify a first digital signal using the digital noise signal to generate a second digital signal, wherein the first digital signal is based on the input digital signal and the output digital signal is based on the second digital signal.

5. The apparatus of claim 1, wherein the active signal management circuitry comprises: a symbol encoder configured to encode at least one occurrence of a substantially periodic data symbol in a first digital signal to generate a second digital signal, wherein the first digital signal is based on the input digital signal and the output digital signal is based on the second digital signal.

6. The apparatus of claim 5, wherein the input digital signal comprises a video signal and the substantially periodic data symbol comprises one of: a synch control word; and a recurring video data symbol.

7. The apparatus of claim 1, wherein the active signal management circuitry comprises: a symbol decoder configured to decode at least one encoded occurrence of a substantially periodic data symbol in a first digital signal to generate a second digital signal, wherein the first digital signal is based on the input digital signal and the output digital signal is based on the second digital signal.

8. The apparatus of claim 1, wherein the active signal management circuitry comprises: a deserializer configured to generate a first plurality of parallel digital signals based a first serialized digital signal, wherein the first serialized digital signal is based on the input digital signal; anda serializer configured to generate a second serialized digital signal based on a second plurality of parallel digital signals, wherein the second plurality of parallel digital signals is based on the first plurality of parallel digital signals and wherein the output digital signal is based on the second serialized digital signal.

9. The apparatus of claim 1, wherein the active signal management circuitry further comprises: an encoder/decoder configured to modify at least a subset of the first plurality of parallel digital signals to generate at least a subset of the second plurality of parallel digital signals.

10. The apparatus of claim 10, wherein the encoder/decoder comprises at least one of: an electromagnetic interference (EMI) encoder; an EMI decoder; a periodic symbol encoder; a periodic symbol decoder; an encryption module; and a decryption module.

11. The apparatus of claim 1, wherein the active signal management circuitry comprises at least one of: an encryption module; and a decryption module.

12. The apparatus of claim 1, wherein the active signal management circuitry comprises: a noise source to provide a digital noise signal; anda modification module to modify a first digital signal based on the digital noise signal to generate a second digital signal, wherein the first digital signal is based on the input digital signal and the output digital signal is based on the second digital signal.

13. The apparatus of claim 1, further comprising: a direction detection module to: configure the direction detection signal to have one of the first state or the second state in response to determining that the active signal management circuitry is connected at a transmit side of a transmission path; andconfigure the direction detection signal to have the other of the first state or the second state in response to determining that the active signal management circuitry is connected at a receive side of the transmission path.

14. The apparatus of claim 13, wherein a clock signal is transmitted from the transmit side to the receive side of the transmission path and wherein the direction detection module is configured to: increment a counter for each received clock cycle of the clock signal;configure the direction detection signal to have one of the first state or the second state in response to a count of the counter being less than a predetermined count; andconfigure the direction detection signal to have the other of the first state or the second state in response to the count of the counter being greater than the predetermined count.

15. The apparatus of claim 1, wherein the apparatus is an integrated circuit.

16. A cable apparatus comprising: a plurality of conductive interconnects;a first cable receptacle comprising a first receptacle interface coupleable to an interface of a first device;a second cable receptacle comprising a second receptacle interface coupleable to an interface of a second device;a first bidirectional circuit component disposed at the first cable receptacle and having a first port connected to a pin interface of the first cable receptacle and a second port coupled to a first conductive interconnect of the plurality of conductive interconnects, the first bidirectional circuit component comprising: first active signal management circuitry comprising an input to receive a first input digital signal and an output to provide a first output digital signal, the first active signal management circuitry configured to generate the first output signal based on the first input digital signal; anda first switching component configured to selectively couple one of the input or the output of the first active signal management circuitry to the first port and selectively couple the other of the input or the output of the first active signal management circuitry to the second port based on a state of a first direction signal.

17. The cable apparatus of claim 16, further comprising: a second bidirectional circuit component disposed at the second cable receptacle and having a third port connected to a pin interface of the second cable receptacle and a fourth port coupled to the first conductive interconnect of the cable body, the second bidirectional circuit component comprising: second active signal management circuitry comprising an input to receive a second input digital signal and an output to provide a second output digital signal, the second active signal management circuitry configured to generate the second output digital signal based on the second input digital signal; anda second switching component configured to selectively couple one of the input or the output of the second active signal management circuitry to the third port and selectively couple the other of the input or the output of the second active signal management circuitry to the fourth port based on a state of a second direction signal.

18. The cable apparatus of claim 16, wherein the first bidirectional circuit component further comprises: a direction detection module comprising an input coupled to a clock pin interface of the first receptacle interface and an output to provide the first direction detection signal, wherein the direction detection module is configured to configure the first direction detection signal to have an identified state based on a number of detected clock cycles of a clock signal received via the clock pin interface.

19. The cable apparatus of claim 16, wherein the cable apparatus comprises a cable.

20. The cable apparatus of claim 16, wherein the cable apparatus comprises a cable adaptor.

21. In a cable apparatus comprising a first cable receptacle comprising a first receptacle interface coupled to an interface of a first device, a second cable receptacle comprising a second receptacle interface coupleable to an interface of a second device, first active signal management circuitry disposed at the first cable receptacle and having a first port connected to a pin interface of the first cable receptacle and a second port coupled to a conductive interconnect, and second active signal management circuitry disposed at the second cable receptacle and having a third port connected to a pin interface of the second cable receptacle and a fourth port coupled to the conductive interconnect, a method comprising: determining which one of the first device or the second device comprises a transmitting device;in response to determining that the first device comprises the transmitting device: configuring the first active signal management circuitry to receive a first digital signal at the first port and provide a second digital signal to the second port;performing, at the first active signal management circuitry, a first active signal management process based on the first digital signal to generate the second digital signal; andconfiguring the second active signal management circuitry to receive the second digital signal at the fourth port and provide a third digital signal to the third port; andperforming, at the second active signal management circuitry, a second active signal management process based on the second digital signal to generate the third digital signal.

22. The method of claim 21, further comprising: in response to determining that the second device comprises the transmitting device: configuring the second active signal management circuitry to receive a first digital signal at the fourth port and provide a second digital signal to the third port;performing, at the second active signal management circuitry, a first active signal management process based on the first digital signal to generate the second digital signal; andconfiguring the first active signal management circuitry to receive the second digital signal at the second port and provide a third digital signal to the first port; andperforming, at the first active signal management circuitry, a second active signal management process based on the second digital signal to generate the third digital signal.

23. The method of claim 21, wherein determining which one of the first device or the second device comprises a transmitting device comprises: determining a first number of detected clock cycles via a clock pin receptacle of the first cable receptacle in response to coupling the first cable receptacle to the first device;determining a second number of detected clock cycles via a clock pin receptacle of the second cable receptacle in response to coupling the second cable receptacle to the second device; anddetermining as the transmit device the first device in response to the first number of detected clock cycles being greater than a clock cycle threshold; anddetermining as the transmit device the second device in response to the second number of detected clock cycles being greater than the clock cycle threshold.